1 /*
2 * Copyright (c) 2018 Kokoon Technology Limited
3 * Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
4 * Copyright (c) 2019 Endre Karlson
5 * Copyright (c) 2020 Teslabs Engineering S.L.
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9
10 #define DT_DRV_COMPAT st_stm32_adc
11
12 #include <errno.h>
13
14 #include <drivers/adc.h>
15 #include <device.h>
16 #include <kernel.h>
17 #include <init.h>
18 #include <soc.h>
19 #include <stm32_ll_adc.h>
20
21 #define ADC_CONTEXT_USES_KERNEL_TIMER
22 #include "adc_context.h"
23
24 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
25 #include <logging/log.h>
26 LOG_MODULE_REGISTER(adc_stm32);
27
28 #include <drivers/clock_control/stm32_clock_control.h>
29 #include <pinmux/pinmux_stm32.h>
30
31 #if defined(CONFIG_SOC_SERIES_STM32F3X)
32 #if defined(ADC1_V2_5)
33 #define STM32F3X_ADC_V2_5
34 #elif defined(ADC5_V1_1)
35 #define STM32F3X_ADC_V1_1
36 #endif
37 #endif
38
39 #if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
40 !defined(CONFIG_SOC_SERIES_STM32G0X) && \
41 !defined(CONFIG_SOC_SERIES_STM32L0X) && \
42 !defined(CONFIG_SOC_SERIES_STM32WLX)
43 #define RANK(n) LL_ADC_REG_RANK_##n
44 static const uint32_t table_rank[] = {
45 RANK(1),
46 RANK(2),
47 RANK(3),
48 RANK(4),
49 RANK(5),
50 RANK(6),
51 RANK(7),
52 RANK(8),
53 RANK(9),
54 RANK(10),
55 RANK(11),
56 RANK(12),
57 RANK(13),
58 RANK(14),
59 RANK(15),
60 RANK(16),
61 };
62
63 #define SEQ_LEN(n) LL_ADC_REG_SEQ_SCAN_ENABLE_##n##RANKS
64 static const uint32_t table_seq_len[] = {
65 LL_ADC_REG_SEQ_SCAN_DISABLE,
66 SEQ_LEN(2),
67 SEQ_LEN(3),
68 SEQ_LEN(4),
69 SEQ_LEN(5),
70 SEQ_LEN(6),
71 SEQ_LEN(7),
72 SEQ_LEN(8),
73 SEQ_LEN(9),
74 SEQ_LEN(10),
75 SEQ_LEN(11),
76 SEQ_LEN(12),
77 SEQ_LEN(13),
78 SEQ_LEN(14),
79 SEQ_LEN(15),
80 SEQ_LEN(16),
81 };
82 #endif
83
84 #define RES(n) LL_ADC_RESOLUTION_##n##B
85 static const uint32_t table_resolution[] = {
86 #if defined(CONFIG_SOC_SERIES_STM32F1X) || \
87 defined(STM32F3X_ADC_V2_5)
88 RES(12),
89 #elif !defined(CONFIG_SOC_SERIES_STM32H7X)
90 RES(6),
91 RES(8),
92 RES(10),
93 RES(12),
94 #else
95 RES(8),
96 RES(10),
97 RES(12),
98 RES(14),
99 RES(16),
100 #endif
101 };
102
103 #define SMP_TIME(x, y) LL_ADC_SAMPLINGTIME_##x##CYCLE##y
104
105 /*
106 * Conversion time in ADC cycles. Many values should have been 0.5 less,
107 * but the adc api system currently does not support describing 'half cycles'.
108 * So all half cycles are counted as one.
109 */
110 #if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F1X)
111 static const uint16_t acq_time_tbl[8] = {2, 8, 14, 29, 42, 56, 72, 240};
112 static const uint32_t table_samp_time[] = {
113 SMP_TIME(1, _5),
114 SMP_TIME(7, S_5),
115 SMP_TIME(13, S_5),
116 SMP_TIME(28, S_5),
117 SMP_TIME(41, S_5),
118 SMP_TIME(55, S_5),
119 SMP_TIME(71, S_5),
120 SMP_TIME(239, S_5),
121 };
122 #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
123 defined(CONFIG_SOC_SERIES_STM32F4X) || \
124 defined(CONFIG_SOC_SERIES_STM32F7X)
125 static const uint16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480};
126 static const uint32_t table_samp_time[] = {
127 SMP_TIME(3, S),
128 SMP_TIME(15, S),
129 SMP_TIME(28, S),
130 SMP_TIME(56, S),
131 SMP_TIME(84, S),
132 SMP_TIME(112, S),
133 SMP_TIME(144, S),
134 SMP_TIME(480, S),
135 };
136 #elif defined(CONFIG_SOC_SERIES_STM32F3X)
137 #ifdef ADC5_V1_1
138 static const uint16_t acq_time_tbl[8] = {2, 3, 5, 8, 20, 62, 182, 602};
139 static const uint32_t table_samp_time[] = {
140 SMP_TIME(1, _5),
141 SMP_TIME(2, S_5),
142 SMP_TIME(4, S_5),
143 SMP_TIME(7, S_5),
144 SMP_TIME(19, S_5),
145 SMP_TIME(61, S_5),
146 SMP_TIME(181, S_5),
147 SMP_TIME(601, S_5),
148 };
149 #else
150 static const uint16_t acq_time_tbl[8] = {2, 8, 14, 29, 42, 56, 72, 240};
151 static const uint32_t table_samp_time[] = {
152 SMP_TIME(1, _5),
153 SMP_TIME(7, S_5),
154 SMP_TIME(13, S_5),
155 SMP_TIME(28, S_5),
156 SMP_TIME(41, S_5),
157 SMP_TIME(55, S_5),
158 SMP_TIME(71, S_5),
159 SMP_TIME(239, S_5),
160 };
161 #endif /* ADC5_V1_1 */
162 #elif defined(CONFIG_SOC_SERIES_STM32L0X) || \
163 defined(CONFIG_SOC_SERIES_STM32G0X) || \
164 defined(CONFIG_SOC_SERIES_STM32WLX)
165 static const uint16_t acq_time_tbl[8] = {2, 4, 8, 13, 20, 40, 80, 161};
166 static const uint32_t table_samp_time[] = {
167 SMP_TIME(1, _5),
168 SMP_TIME(3, S_5),
169 SMP_TIME(7, S_5),
170 SMP_TIME(12, S_5),
171 SMP_TIME(19, S_5),
172 SMP_TIME(39, S_5),
173 SMP_TIME(79, S_5),
174 SMP_TIME(160, S_5),
175 };
176 #elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
177 defined(CONFIG_SOC_SERIES_STM32L5X) || \
178 defined(CONFIG_SOC_SERIES_STM32WBX) || \
179 defined(CONFIG_SOC_SERIES_STM32G4X)
180 static const uint16_t acq_time_tbl[8] = {3, 7, 13, 25, 48, 93, 248, 641};
181 static const uint32_t table_samp_time[] = {
182 SMP_TIME(2, S_5),
183 SMP_TIME(6, S_5),
184 SMP_TIME(12, S_5),
185 SMP_TIME(24, S_5),
186 SMP_TIME(47, S_5),
187 SMP_TIME(92, S_5),
188 SMP_TIME(247, S_5),
189 SMP_TIME(640, S_5),
190 };
191 #elif defined(CONFIG_SOC_SERIES_STM32L1X)
192 static const uint16_t acq_time_tbl[8] = {5, 10, 17, 25, 49, 97, 193, 385};
193 static const uint32_t table_samp_time[] = {
194 SMP_TIME(4, S),
195 SMP_TIME(9, S),
196 SMP_TIME(16, S),
197 SMP_TIME(24, S),
198 SMP_TIME(48, S),
199 SMP_TIME(96, S),
200 SMP_TIME(192, S),
201 SMP_TIME(384, S),
202 };
203 #elif defined(CONFIG_SOC_SERIES_STM32H7X)
204 static const uint16_t acq_time_tbl[8] = {2, 3, 9, 17, 33, 65, 388, 811};
205 static const uint32_t table_samp_time[] = {
206 SMP_TIME(1, _5),
207 SMP_TIME(2, S_5),
208 SMP_TIME(8, S_5),
209 SMP_TIME(16, S_5),
210 SMP_TIME(32, S_5),
211 SMP_TIME(64, S_5),
212 SMP_TIME(387, S_5),
213 SMP_TIME(810, S_5),
214 };
215 #endif
216
217 /* Bugfix for STM32G4 HAL */
218 #if !defined(ADC_CHANNEL_TEMPSENSOR)
219 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_TEMPSENSOR_ADC1
220 #endif
221
222 /* External channels (maximum). */
223 #define STM32_CHANNEL_COUNT 20
224
225 struct adc_stm32_data {
226 struct adc_context ctx;
227 const struct device *dev;
228 uint16_t *buffer;
229 uint16_t *repeat_buffer;
230
231 uint8_t resolution;
232 uint8_t channel_count;
233 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
234 defined(CONFIG_SOC_SERIES_STM32G0X) || \
235 defined(CONFIG_SOC_SERIES_STM32L0X)
236 int8_t acq_time_index;
237 #endif
238 };
239
240 struct adc_stm32_cfg {
241 ADC_TypeDef *base;
242 void (*irq_cfg_func)(void);
243 struct stm32_pclken pclken;
244 const struct soc_gpio_pinctrl *pinctrl;
245 size_t pinctrl_len;
246 };
247
check_buffer_size(const struct adc_sequence * sequence,uint8_t active_channels)248 static int check_buffer_size(const struct adc_sequence *sequence,
249 uint8_t active_channels)
250 {
251 size_t needed_buffer_size;
252
253 needed_buffer_size = active_channels * sizeof(uint16_t);
254
255 if (sequence->options) {
256 needed_buffer_size *= (1 + sequence->options->extra_samplings);
257 }
258
259 if (sequence->buffer_size < needed_buffer_size) {
260 LOG_ERR("Provided buffer is too small (%u/%u)",
261 sequence->buffer_size, needed_buffer_size);
262 return -ENOMEM;
263 }
264
265 return 0;
266 }
267
adc_stm32_start_conversion(const struct device * dev)268 static void adc_stm32_start_conversion(const struct device *dev)
269 {
270 const struct adc_stm32_cfg *config = dev->config;
271 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
272
273 LOG_DBG("Starting conversion");
274
275 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
276 defined(CONFIG_SOC_SERIES_STM32F3X) || \
277 defined(CONFIG_SOC_SERIES_STM32L0X) || \
278 defined(CONFIG_SOC_SERIES_STM32L4X) || \
279 defined(CONFIG_SOC_SERIES_STM32L5X) || \
280 defined(CONFIG_SOC_SERIES_STM32WBX) || \
281 defined(CONFIG_SOC_SERIES_STM32G0X) || \
282 defined(CONFIG_SOC_SERIES_STM32G4X) || \
283 defined(CONFIG_SOC_SERIES_STM32H7X) || \
284 defined(CONFIG_SOC_SERIES_STM32WLX)
285 LL_ADC_REG_StartConversion(adc);
286 #else
287 LL_ADC_REG_StartConversionSWStart(adc);
288 #endif
289 }
290
291 #if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
292 !defined(CONFIG_SOC_SERIES_STM32F4X) && \
293 !defined(CONFIG_SOC_SERIES_STM32F7X) && \
294 !defined(CONFIG_SOC_SERIES_STM32F1X) && \
295 !defined(STM32F3X_ADC_V2_5) && \
296 !defined(CONFIG_SOC_SERIES_STM32L1X)
adc_stm32_calib(const struct device * dev)297 static void adc_stm32_calib(const struct device *dev)
298 {
299 const struct adc_stm32_cfg *config =
300 (const struct adc_stm32_cfg *)dev->config;
301 ADC_TypeDef *adc = config->base;
302
303 #if defined(STM32F3X_ADC_V1_1) || \
304 defined(CONFIG_SOC_SERIES_STM32L4X) || \
305 defined(CONFIG_SOC_SERIES_STM32L5X) || \
306 defined(CONFIG_SOC_SERIES_STM32WBX) || \
307 defined(CONFIG_SOC_SERIES_STM32G4X)
308 LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
309 #elif defined(CONFIG_SOC_SERIES_STM32F0X) || \
310 defined(CONFIG_SOC_SERIES_STM32G0X) || \
311 defined(CONFIG_SOC_SERIES_STM32L0X) || \
312 defined(CONFIG_SOC_SERIES_STM32WLX)
313 LL_ADC_StartCalibration(adc);
314 #elif defined(CONFIG_SOC_SERIES_STM32H7X)
315 LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET, LL_ADC_SINGLE_ENDED);
316 #endif
317 while (LL_ADC_IsCalibrationOnGoing(adc)) {
318 }
319 }
320 #endif
321
322 /*
323 * Enable ADC peripheral, and wait until ready if required by SOC.
324 */
adc_stm32_enable(ADC_TypeDef * adc)325 static int adc_stm32_enable(ADC_TypeDef *adc)
326 {
327 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
328 defined(CONFIG_SOC_SERIES_STM32L5X) || \
329 defined(CONFIG_SOC_SERIES_STM32WBX) || \
330 defined(CONFIG_SOC_SERIES_STM32G0X) || \
331 defined(CONFIG_SOC_SERIES_STM32G4X) || \
332 defined(CONFIG_SOC_SERIES_STM32WLX)
333
334 if (LL_ADC_IsEnabled(adc) == 1UL) {
335 return 0;
336 }
337
338 LL_ADC_ClearFlag_ADRDY(adc);
339 LL_ADC_Enable(adc);
340
341 /*
342 * Enabling ADC modules in L4, WB, G0 and G4 series may fail if they are
343 * still not stabilized, this will wait for a short time to ensure ADC
344 * modules are properly enabled.
345 */
346 uint32_t count_timeout = 0;
347
348 while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) {
349 if (LL_ADC_IsEnabled(adc) == 0UL) {
350 LL_ADC_Enable(adc);
351 count_timeout++;
352 if (count_timeout == 10) {
353 return -ETIMEDOUT;
354 }
355 }
356 }
357 #else
358 LL_ADC_Enable(adc);
359 #endif
360
361 return 0;
362 }
363
364
start_read(const struct device * dev,const struct adc_sequence * sequence)365 static int start_read(const struct device *dev,
366 const struct adc_sequence *sequence)
367 {
368 const struct adc_stm32_cfg *config = dev->config;
369 struct adc_stm32_data *data = dev->data;
370 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
371 uint8_t resolution;
372 int err;
373
374 switch (sequence->resolution) {
375 #if defined(CONFIG_SOC_SERIES_STM32F1X) || \
376 defined(STM32F3X_ADC_V2_5)
377 case 12:
378 resolution = table_resolution[0];
379 break;
380 #elif !defined(CONFIG_SOC_SERIES_STM32H7X)
381 case 6:
382 resolution = table_resolution[0];
383 break;
384 case 8:
385 resolution = table_resolution[1];
386 break;
387 case 10:
388 resolution = table_resolution[2];
389 break;
390 case 12:
391 resolution = table_resolution[3];
392 break;
393 #else
394 case 8:
395 resolution = table_resolution[0];
396 break;
397 case 10:
398 resolution = table_resolution[1];
399 break;
400 case 12:
401 resolution = table_resolution[2];
402 break;
403 case 14:
404 resolution = table_resolution[3];
405 break;
406 case 16:
407 resolution = table_resolution[4];
408 break;
409 #endif
410 default:
411 LOG_ERR("Invalid resolution");
412 return -EINVAL;
413 }
414
415 uint32_t channels = sequence->channels;
416 uint8_t index = find_lsb_set(channels) - 1;
417
418 if (channels > BIT(index)) {
419 LOG_ERR("Only single channel supported");
420 return -ENOTSUP;
421 }
422
423 data->buffer = sequence->buffer;
424
425 uint32_t channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL(index);
426 #if defined(CONFIG_SOC_SERIES_STM32H7X)
427 /*
428 * Each channel in the sequence must be previously enabled in PCSEL.
429 * This register controls the analog switch integrated in the IO level.
430 * NOTE: There is no LL API to control this register yet.
431 */
432 adc->PCSEL |= channels & ADC_PCSEL_PCSEL_Msk;
433 #endif
434
435 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
436 defined(CONFIG_SOC_SERIES_STM32L0X)
437 LL_ADC_REG_SetSequencerChannels(adc, channel);
438 #elif defined(CONFIG_SOC_SERIES_STM32G0X) || \
439 defined(CONFIG_SOC_SERIES_STM32WLX)
440 /* STM32G0 in "not fully configurable" sequencer mode */
441 LL_ADC_REG_SetSequencerChannels(adc, channel);
442 while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) {
443 }
444 #else
445 LL_ADC_REG_SetSequencerRanks(adc, table_rank[0], channel);
446 LL_ADC_REG_SetSequencerLength(adc, table_seq_len[0]);
447 #endif
448 data->channel_count = 1;
449
450 err = check_buffer_size(sequence, data->channel_count);
451 if (err) {
452 return err;
453 }
454
455 #if defined(CONFIG_SOC_SERIES_STM32G0X) || \
456 defined(CONFIG_SOC_SERIES_STM32WLX)
457 /*
458 * Writing ADC_CFGR1 register while ADEN bit is set
459 * resets RES[1:0] bitfield. We need to disable and enable adc.
460 */
461 if (LL_ADC_IsEnabled(adc) == 1UL) {
462 LL_ADC_Disable(adc);
463 }
464 while (LL_ADC_IsEnabled(adc) == 1UL) {
465 }
466 LL_ADC_SetResolution(adc, resolution);
467 adc_stm32_enable(adc);
468 #elif !defined(CONFIG_SOC_SERIES_STM32F1X) && \
469 !defined(STM32F3X_ADC_V2_5)
470 LL_ADC_SetResolution(adc, resolution);
471 #endif
472
473 #if defined(CONFIG_SOC_SERIES_STM32L0X) || \
474 defined(CONFIG_SOC_SERIES_STM32WLX)
475 /*
476 * setting OVS bits is conditioned to ADC state: ADC must be disabled
477 * or enabled without conversion on going : disable it, it will stop
478 */
479 LL_ADC_Disable(adc);
480 while (LL_ADC_IsEnabled(adc) == 1UL) {
481 }
482 #endif /* CONFIG_SOC_SERIES_STM32L0X */
483 #if defined(CONFIG_SOC_SERIES_STM32G0X) || \
484 defined(CONFIG_SOC_SERIES_STM32G4X) || \
485 defined(CONFIG_SOC_SERIES_STM32H7X) || \
486 defined(CONFIG_SOC_SERIES_STM32L0X) || \
487 defined(CONFIG_SOC_SERIES_STM32L4X) || \
488 defined(CONFIG_SOC_SERIES_STM32L5X) || \
489 defined(CONFIG_SOC_SERIES_STM32WBX) || \
490 defined(CONFIG_SOC_SERIES_STM32WLX)
491
492 switch (sequence->oversampling) {
493 case 0:
494 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_DISABLE);
495 break;
496 case 1:
497 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
498 #if defined(CONFIG_SOC_SERIES_STM32H7X)
499 LL_ADC_ConfigOverSamplingRatioShift(adc, sequence->oversampling,
500 #else /* CONFIG_SOC_SERIES_STM32H7X */
501 LL_ADC_ConfigOverSamplingRatioShift(adc, LL_ADC_OVS_RATIO_2,
502 #endif /* CONFIG_SOC_SERIES_STM32H7X */
503 LL_ADC_OVS_SHIFT_RIGHT_1);
504 break;
505 case 2:
506 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
507 #if defined(CONFIG_SOC_SERIES_STM32H7X)
508 LL_ADC_ConfigOverSamplingRatioShift(adc, sequence->oversampling,
509 #else /* CONFIG_SOC_SERIES_STM32H7X */
510 LL_ADC_ConfigOverSamplingRatioShift(adc, LL_ADC_OVS_RATIO_4,
511 #endif /* CONFIG_SOC_SERIES_STM32H7X */
512 LL_ADC_OVS_SHIFT_RIGHT_2);
513 break;
514 case 3:
515 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
516 #if defined(CONFIG_SOC_SERIES_STM32H7X)
517 LL_ADC_ConfigOverSamplingRatioShift(adc, sequence->oversampling,
518 #else /* CONFIG_SOC_SERIES_STM32H7X */
519 LL_ADC_ConfigOverSamplingRatioShift(adc, LL_ADC_OVS_RATIO_8,
520 #endif /* CONFIG_SOC_SERIES_STM32H7X */
521 LL_ADC_OVS_SHIFT_RIGHT_3);
522 break;
523 case 4:
524 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
525 #if defined(CONFIG_SOC_SERIES_STM32H7X)
526 LL_ADC_ConfigOverSamplingRatioShift(adc, sequence->oversampling,
527 #else /* CONFIG_SOC_SERIES_STM32H7X */
528 LL_ADC_ConfigOverSamplingRatioShift(adc, LL_ADC_OVS_RATIO_16,
529 #endif /* CONFIG_SOC_SERIES_STM32H7X */
530 LL_ADC_OVS_SHIFT_RIGHT_4);
531 break;
532 case 5:
533 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
534 #if defined(CONFIG_SOC_SERIES_STM32H7X)
535 LL_ADC_ConfigOverSamplingRatioShift(adc, sequence->oversampling,
536 #else /* CONFIG_SOC_SERIES_STM32H7X */
537 LL_ADC_ConfigOverSamplingRatioShift(adc, LL_ADC_OVS_RATIO_32,
538 #endif /* CONFIG_SOC_SERIES_STM32H7X */
539 LL_ADC_OVS_SHIFT_RIGHT_5);
540 break;
541 case 6:
542 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
543 #if defined(CONFIG_SOC_SERIES_STM32H7X)
544 LL_ADC_ConfigOverSamplingRatioShift(adc, sequence->oversampling,
545 #else /* CONFIG_SOC_SERIES_STM32H7X */
546 LL_ADC_ConfigOverSamplingRatioShift(adc, LL_ADC_OVS_RATIO_64,
547 #endif /* CONFIG_SOC_SERIES_STM32H7X */
548 LL_ADC_OVS_SHIFT_RIGHT_6);
549 break;
550 case 7:
551 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
552 #if defined(CONFIG_SOC_SERIES_STM32H7X)
553 LL_ADC_ConfigOverSamplingRatioShift(adc, sequence->oversampling,
554 #else
555 LL_ADC_ConfigOverSamplingRatioShift(adc, LL_ADC_OVS_RATIO_128,
556 #endif /* CONFIG_SOC_SERIES_STM32H7X */
557 LL_ADC_OVS_SHIFT_RIGHT_7);
558 break;
559 case 8:
560 LL_ADC_SetOverSamplingScope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);
561 #if defined(CONFIG_SOC_SERIES_STM32H7X)
562 LL_ADC_ConfigOverSamplingRatioShift(adc, sequence->oversampling,
563 #else
564 LL_ADC_ConfigOverSamplingRatioShift(adc, LL_ADC_OVS_RATIO_256,
565 #endif
566 LL_ADC_OVS_SHIFT_RIGHT_8);
567 break;
568 default:
569 LOG_ERR("Invalid oversampling");
570 adc_stm32_enable(adc);
571 return -EINVAL;
572 }
573 /* re-enable ADC after changing the OVS */
574 adc_stm32_enable(adc);
575 #else
576 if (sequence->oversampling) {
577 LOG_ERR("Oversampling not supported");
578 return -ENOTSUP;
579 }
580 #endif
581
582 if (sequence->calibrate) {
583 #if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
584 !defined(CONFIG_SOC_SERIES_STM32F4X) && \
585 !defined(CONFIG_SOC_SERIES_STM32F7X) && \
586 !defined(CONFIG_SOC_SERIES_STM32F1X) && \
587 !defined(STM32F3X_ADC_V2_5) && \
588 !defined(CONFIG_SOC_SERIES_STM32L1X)
589
590 /* we cannot calibrate the ADC while the ADC is enabled */
591 LL_ADC_Disable(adc);
592 while (LL_ADC_IsEnabled(adc) == 1UL) {
593 }
594 adc_stm32_calib(dev);
595 /* re-enable ADC after calibration */
596 adc_stm32_enable(adc);
597 #else
598 LOG_ERR("Calibration not supported");
599 return -ENOTSUP;
600 #endif
601 }
602
603 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
604 defined(STM32F3X_ADC_V1_1) || \
605 defined(CONFIG_SOC_SERIES_STM32L0X) || \
606 defined(CONFIG_SOC_SERIES_STM32L4X) || \
607 defined(CONFIG_SOC_SERIES_STM32L5X) || \
608 defined(CONFIG_SOC_SERIES_STM32WBX) || \
609 defined(CONFIG_SOC_SERIES_STM32G0X) || \
610 defined(CONFIG_SOC_SERIES_STM32G4X) || \
611 defined(CONFIG_SOC_SERIES_STM32H7X) || \
612 defined(CONFIG_SOC_SERIES_STM32WLX)
613 LL_ADC_EnableIT_EOC(adc);
614 #elif defined(CONFIG_SOC_SERIES_STM32F1X)
615 LL_ADC_EnableIT_EOS(adc);
616 #elif defined(STM32F3X_ADC_V2_5)
617 adc_stm32_enable(adc);
618 LL_ADC_EnableIT_EOS(adc);
619 #else
620 LL_ADC_EnableIT_EOCS(adc);
621 #endif
622
623 adc_context_start_read(&data->ctx, sequence);
624
625 return adc_context_wait_for_completion(&data->ctx);
626 }
627
adc_context_start_sampling(struct adc_context * ctx)628 static void adc_context_start_sampling(struct adc_context *ctx)
629 {
630 struct adc_stm32_data *data =
631 CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
632
633 data->repeat_buffer = data->buffer;
634
635 adc_stm32_start_conversion(data->dev);
636 }
637
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)638 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
639 bool repeat_sampling)
640 {
641 struct adc_stm32_data *data =
642 CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
643
644 if (repeat_sampling) {
645 data->buffer = data->repeat_buffer;
646 }
647 }
648
adc_stm32_isr(const struct device * dev)649 static void adc_stm32_isr(const struct device *dev)
650 {
651 struct adc_stm32_data *data = (struct adc_stm32_data *)dev->data;
652 const struct adc_stm32_cfg *config =
653 (const struct adc_stm32_cfg *)dev->config;
654 ADC_TypeDef *adc = config->base;
655
656 *data->buffer++ = LL_ADC_REG_ReadConversionData32(adc);
657
658 adc_context_on_sampling_done(&data->ctx, dev);
659
660 LOG_DBG("ISR triggered.");
661 }
662
adc_stm32_read(const struct device * dev,const struct adc_sequence * sequence)663 static int adc_stm32_read(const struct device *dev,
664 const struct adc_sequence *sequence)
665 {
666 struct adc_stm32_data *data = dev->data;
667 int error;
668
669 adc_context_lock(&data->ctx, false, NULL);
670 error = start_read(dev, sequence);
671 adc_context_release(&data->ctx, error);
672
673 return error;
674 }
675
676 #ifdef CONFIG_ADC_ASYNC
adc_stm32_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)677 static int adc_stm32_read_async(const struct device *dev,
678 const struct adc_sequence *sequence,
679 struct k_poll_signal *async)
680 {
681 struct adc_stm32_data *data = dev->data;
682 int error;
683
684 adc_context_lock(&data->ctx, true, async);
685 error = start_read(dev, sequence);
686 adc_context_release(&data->ctx, error);
687
688 return error;
689 }
690 #endif
691
adc_stm32_check_acq_time(uint16_t acq_time)692 static int adc_stm32_check_acq_time(uint16_t acq_time)
693 {
694 if (acq_time == ADC_ACQ_TIME_MAX) {
695 return ARRAY_SIZE(acq_time_tbl) - 1;
696 }
697
698 for (int i = 0; i < 8; i++) {
699 if (acq_time == ADC_ACQ_TIME(ADC_ACQ_TIME_TICKS,
700 acq_time_tbl[i])) {
701 return i;
702 }
703 }
704
705 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
706 return 0;
707 }
708
709 LOG_ERR("Conversion time not supportted.");
710 return -EINVAL;
711 }
712
713 /*
714 * Enable internal channel source
715 */
adc_stm32_set_common_path(const struct device * dev,uint32_t PathInternal)716 static void adc_stm32_set_common_path(const struct device *dev, uint32_t PathInternal)
717 {
718 const struct adc_stm32_cfg *config =
719 (const struct adc_stm32_cfg *)dev->config;
720 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
721 (void) adc; /* Avoid 'unused variable' warning for some families */
722
723 /* Do not remove existing paths */
724 PathInternal |= LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc));
725 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc), PathInternal);
726 }
727
adc_stm32_setup_speed(const struct device * dev,uint8_t id,uint8_t acq_time_index)728 static void adc_stm32_setup_speed(const struct device *dev, uint8_t id,
729 uint8_t acq_time_index)
730 {
731 const struct adc_stm32_cfg *config =
732 (const struct adc_stm32_cfg *)dev->config;
733 ADC_TypeDef *adc = config->base;
734
735 #if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
736 LL_ADC_SetSamplingTimeCommonChannels(adc,
737 table_samp_time[acq_time_index]);
738 #elif defined(CONFIG_SOC_SERIES_STM32G0X)
739 LL_ADC_SetSamplingTimeCommonChannels(adc, LL_ADC_SAMPLINGTIME_COMMON_1,
740 table_samp_time[acq_time_index]);
741 #else
742 LL_ADC_SetChannelSamplingTime(adc,
743 __LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
744 table_samp_time[acq_time_index]);
745 #endif
746 }
747
adc_stm32_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)748 static int adc_stm32_channel_setup(const struct device *dev,
749 const struct adc_channel_cfg *channel_cfg)
750 {
751 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
752 defined(CONFIG_SOC_SERIES_STM32G0X) || \
753 defined(CONFIG_SOC_SERIES_STM32L0X)
754 struct adc_stm32_data *data = dev->data;
755 #endif
756 int acq_time_index;
757
758 if (channel_cfg->channel_id >= STM32_CHANNEL_COUNT) {
759 LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
760 return -EINVAL;
761 }
762
763 acq_time_index = adc_stm32_check_acq_time(
764 channel_cfg->acquisition_time);
765 if (acq_time_index < 0) {
766 return acq_time_index;
767 }
768 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
769 defined(CONFIG_SOC_SERIES_STM32G0X) || \
770 defined(CONFIG_SOC_SERIES_STM32L0X)
771 if (data->acq_time_index == -1) {
772 data->acq_time_index = acq_time_index;
773 } else {
774 /* All channels of F0/L0 must have identical acquisition time.*/
775 if (acq_time_index != data->acq_time_index) {
776 return -EINVAL;
777 }
778 }
779 #endif
780
781 if (channel_cfg->differential) {
782 LOG_ERR("Differential channels are not supported");
783 return -EINVAL;
784 }
785
786 if (channel_cfg->gain != ADC_GAIN_1) {
787 LOG_ERR("Invalid channel gain");
788 return -EINVAL;
789 }
790
791 if (channel_cfg->reference != ADC_REF_INTERNAL) {
792 LOG_ERR("Invalid channel reference");
793 return -EINVAL;
794 }
795
796 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_TEMPSENSOR) == channel_cfg->channel_id) {
797 adc_stm32_set_common_path(dev, LL_ADC_PATH_INTERNAL_TEMPSENSOR);
798 } else if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_VREFINT) == channel_cfg->channel_id) {
799 adc_stm32_set_common_path(dev, LL_ADC_PATH_INTERNAL_VREFINT);
800 }
801
802 adc_stm32_setup_speed(dev, channel_cfg->channel_id,
803 acq_time_index);
804
805 LOG_DBG("Channel setup succeeded!");
806
807 return 0;
808 }
809
adc_stm32_init(const struct device * dev)810 static int adc_stm32_init(const struct device *dev)
811 {
812 struct adc_stm32_data *data = dev->data;
813 const struct adc_stm32_cfg *config = dev->config;
814 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
815 ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
816 int err;
817
818 LOG_DBG("Initializing....");
819
820 data->dev = dev;
821 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
822 defined(CONFIG_SOC_SERIES_STM32G0X) || \
823 defined(CONFIG_SOC_SERIES_STM32L0X)
824 /*
825 * All conversion time for all channels on one ADC instance for F0 and
826 * L0 series chips has to be the same. For STM32G0 currently only one
827 * of the two available common channel conversion times is used.
828 * This additional variable is for checking if the conversion time
829 * selection of all channels on one ADC instance is the same.
830 */
831 data->acq_time_index = -1;
832 #endif
833
834 if (clock_control_on(clk,
835 (clock_control_subsys_t *) &config->pclken) != 0) {
836 return -EIO;
837 }
838
839 /* Configure dt provided device signals when available */
840 err = stm32_dt_pinctrl_configure(config->pinctrl,
841 config->pinctrl_len,
842 (uint32_t)config->base);
843 if (err < 0) {
844 LOG_ERR("ADC pinctrl setup failed (%d)", err);
845 return err;
846 }
847
848 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
849 defined(CONFIG_SOC_SERIES_STM32L5X) || \
850 defined(CONFIG_SOC_SERIES_STM32WBX) || \
851 defined(CONFIG_SOC_SERIES_STM32G4X) || \
852 defined(CONFIG_SOC_SERIES_STM32H7X)
853 /*
854 * L4, WB, G4 and H7 series STM32 needs to be awaken from deep sleep
855 * mode, and restore its calibration parameters if there are some
856 * previously stored calibration parameters.
857 */
858
859 LL_ADC_DisableDeepPowerDown(adc);
860 #endif
861 /*
862 * F3, L4, WB, G0 and G4 ADC modules need some time
863 * to be stabilized before performing any enable or calibration actions.
864 */
865 #if defined(STM32F3X_ADC_V1_1) || \
866 defined(CONFIG_SOC_SERIES_STM32L4X) || \
867 defined(CONFIG_SOC_SERIES_STM32L5X) || \
868 defined(CONFIG_SOC_SERIES_STM32WBX) || \
869 defined(CONFIG_SOC_SERIES_STM32G0X) || \
870 defined(CONFIG_SOC_SERIES_STM32G4X) || \
871 defined(CONFIG_SOC_SERIES_STM32H7X) || \
872 defined(CONFIG_SOC_SERIES_STM32WLX)
873 LL_ADC_EnableInternalRegulator(adc);
874 k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);
875 #endif
876
877 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
878 defined(CONFIG_SOC_SERIES_STM32L0X) || \
879 defined(CONFIG_SOC_SERIES_STM32WLX)
880 LL_ADC_SetClock(adc, LL_ADC_CLOCK_SYNC_PCLK_DIV4);
881 #elif defined(STM32F3X_ADC_V1_1) || \
882 defined(CONFIG_SOC_SERIES_STM32L4X) || \
883 defined(CONFIG_SOC_SERIES_STM32L5X) || \
884 defined(CONFIG_SOC_SERIES_STM32WBX) || \
885 defined(CONFIG_SOC_SERIES_STM32G0X) || \
886 defined(CONFIG_SOC_SERIES_STM32G4X) || \
887 defined(CONFIG_SOC_SERIES_STM32H7X)
888 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
889 LL_ADC_CLOCK_SYNC_PCLK_DIV4);
890 #elif defined(CONFIG_SOC_SERIES_STM32L1X)
891 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
892 LL_ADC_CLOCK_ASYNC_DIV4);
893 #endif
894
895 #if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
896 !defined(CONFIG_SOC_SERIES_STM32F4X) && \
897 !defined(CONFIG_SOC_SERIES_STM32F7X) && \
898 !defined(CONFIG_SOC_SERIES_STM32F1X) && \
899 !defined(STM32F3X_ADC_V2_5) && \
900 !defined(CONFIG_SOC_SERIES_STM32L1X)
901 /*
902 * Calibration of F1 and F3 (ADC1_V2_5) series has to be started
903 * after ADC Module is enabled.
904 */
905 adc_stm32_calib(dev);
906 #endif
907
908 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
909 defined(CONFIG_SOC_SERIES_STM32L0X) || \
910 defined(CONFIG_SOC_SERIES_STM32L4X) || \
911 defined(CONFIG_SOC_SERIES_STM32L5X) || \
912 defined(CONFIG_SOC_SERIES_STM32WBX) || \
913 defined(CONFIG_SOC_SERIES_STM32G0X) || \
914 defined(CONFIG_SOC_SERIES_STM32G4X) || \
915 defined(CONFIG_SOC_SERIES_STM32H7X) || \
916 defined(CONFIG_SOC_SERIES_STM32WLX)
917 if (LL_ADC_IsActiveFlag_ADRDY(adc)) {
918 LL_ADC_ClearFlag_ADRDY(adc);
919 }
920
921 /*
922 * These STM32 series has one internal voltage reference source
923 * to be enabled.
924 */
925 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc),
926 LL_ADC_PATH_INTERNAL_VREFINT);
927 #endif
928
929 #if defined(CONFIG_SOC_SERIES_STM32F0X) || \
930 defined(STM32F3X_ADC_V1_1) || \
931 defined(CONFIG_SOC_SERIES_STM32L0X) || \
932 defined(CONFIG_SOC_SERIES_STM32L4X) || \
933 defined(CONFIG_SOC_SERIES_STM32L5X) || \
934 defined(CONFIG_SOC_SERIES_STM32WBX) || \
935 defined(CONFIG_SOC_SERIES_STM32G0X) || \
936 defined(CONFIG_SOC_SERIES_STM32G4X) || \
937 defined(CONFIG_SOC_SERIES_STM32H7X) || \
938 defined(CONFIG_SOC_SERIES_STM32WLX)
939 /*
940 * ADC modules on these series have to wait for some cycles to be
941 * enabled.
942 */
943 uint32_t adc_rate, wait_cycles;
944
945 if (clock_control_get_rate(clk,
946 (clock_control_subsys_t *) &config->pclken, &adc_rate) < 0) {
947 LOG_ERR("ADC clock rate get error.");
948 }
949
950 wait_cycles = SystemCoreClock / adc_rate *
951 LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES;
952
953 for (int i = wait_cycles; i >= 0; i--) {
954 }
955 #endif
956
957 err = adc_stm32_enable(adc);
958 if (err < 0) {
959 return err;
960 }
961
962 config->irq_cfg_func();
963
964 #if defined(CONFIG_SOC_SERIES_STM32F1X) || \
965 defined(STM32F3X_ADC_V2_5)
966 /*
967 * Calibration of F1 and F3 (ADC1_V2_5) must starts after two cycles
968 * after ADON is set.
969 */
970 LL_ADC_StartCalibration(adc);
971 LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);
972 #endif
973
974 #ifdef CONFIG_SOC_SERIES_STM32H7X
975 /*
976 * To ensure linearity the factory calibration values
977 * should be loaded on initialization.
978 */
979 uint32_t channel_offset = 0U;
980 uint32_t linear_calib_buffer = 0U;
981
982 if (adc == ADC1) {
983 channel_offset = 0UL;
984 } else if (adc == ADC2) {
985 channel_offset = 8UL;
986 } else /*Case ADC3*/ {
987 channel_offset = 16UL;
988 }
989 /* Read factory calibration factors */
990 for (uint32_t count = 0UL; count < ADC_LINEAR_CALIB_REG_COUNT; count++) {
991 linear_calib_buffer = *(uint32_t *)(
992 ADC_LINEAR_CALIB_REG_1_ADDR + channel_offset + count
993 );
994 LL_ADC_SetCalibrationLinearFactor(
995 adc, LL_ADC_CALIB_LINEARITY_WORD1 << count,
996 linear_calib_buffer
997 );
998 }
999 #endif
1000 adc_context_unlock_unconditionally(&data->ctx);
1001
1002 return 0;
1003 }
1004
1005 static const struct adc_driver_api api_stm32_driver_api = {
1006 .channel_setup = adc_stm32_channel_setup,
1007 .read = adc_stm32_read,
1008 #ifdef CONFIG_ADC_ASYNC
1009 .read_async = adc_stm32_read_async,
1010 #endif
1011 };
1012
1013 #define STM32_ADC_INIT(index) \
1014 \
1015 static void adc_stm32_cfg_func_##index(void); \
1016 \
1017 static const struct soc_gpio_pinctrl adc_pins_##index[] = \
1018 ST_STM32_DT_INST_PINCTRL(index, 0); \
1019 \
1020 static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \
1021 .base = (ADC_TypeDef *)DT_INST_REG_ADDR(index), \
1022 .irq_cfg_func = adc_stm32_cfg_func_##index, \
1023 .pclken = { \
1024 .enr = DT_INST_CLOCKS_CELL(index, bits), \
1025 .bus = DT_INST_CLOCKS_CELL(index, bus), \
1026 }, \
1027 .pinctrl = adc_pins_##index, \
1028 .pinctrl_len = ARRAY_SIZE(adc_pins_##index), \
1029 }; \
1030 static struct adc_stm32_data adc_stm32_data_##index = { \
1031 ADC_CONTEXT_INIT_TIMER(adc_stm32_data_##index, ctx), \
1032 ADC_CONTEXT_INIT_LOCK(adc_stm32_data_##index, ctx), \
1033 ADC_CONTEXT_INIT_SYNC(adc_stm32_data_##index, ctx), \
1034 }; \
1035 \
1036 DEVICE_DT_INST_DEFINE(index, \
1037 &adc_stm32_init, NULL, \
1038 &adc_stm32_data_##index, &adc_stm32_cfg_##index, \
1039 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
1040 &api_stm32_driver_api); \
1041 \
1042 static void adc_stm32_cfg_func_##index(void) \
1043 { \
1044 IRQ_CONNECT(DT_INST_IRQN(index), \
1045 DT_INST_IRQ(index, priority), \
1046 adc_stm32_isr, DEVICE_DT_INST_GET(index), 0); \
1047 irq_enable(DT_INST_IRQN(index)); \
1048 }
1049
1050 DT_INST_FOREACH_STATUS_OKAY(STM32_ADC_INIT)
1051
