1 /* TI ADS1X1X ADC
2 *
3 * Copyright (c) 2021 Facebook, Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <stdbool.h>
9 #include <zephyr/device.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/adc.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/drivers/i2c.h>
14 #include <zephyr/kernel.h>
15 #include <zephyr/sys/byteorder.h>
16 #include <zephyr/sys/util.h>
17
18 #define ADC_CONTEXT_USES_KERNEL_TIMER
19 #include "adc_context.h"
20
21 LOG_MODULE_REGISTER(ADS1X1X, CONFIG_ADC_LOG_LEVEL);
22
23 #define ADS1X1X_CONFIG_OS BIT(15)
24 #define ADS1X1X_CONFIG_MUX(x) ((x) << 12)
25 #define ADS1X1X_CONFIG_PGA(x) ((x) << 9)
26 #define ADS1X1X_CONFIG_MODE BIT(8)
27 #define ADS1X1X_CONFIG_DR(x) ((x) << 5)
28 #define ADS1X1X_CONFIG_COMP_MODE BIT(4)
29 #define ADS1X1X_CONFIG_COMP_POL BIT(3)
30 #define ADS1X1X_CONFIG_COMP_LAT BIT(2)
31 #define ADS1X1X_CONFIG_COMP_QUE(x) (x)
32
33 enum ads1x1x_reg {
34 ADS1X1X_REG_CONV = 0x00,
35 ADS1X1X_REG_CONFIG = 0x01,
36 ADS1X1X_REG_LO_THRESH = 0x02,
37 ADS1X1X_REG_HI_THRESH = 0x03,
38 };
39
40 enum {
41 ADS1X15_CONFIG_MUX_DIFF_0_1 = 0,
42 ADS1X15_CONFIG_MUX_DIFF_0_3 = 1,
43 ADS1X15_CONFIG_MUX_DIFF_1_3 = 2,
44 ADS1X15_CONFIG_MUX_DIFF_2_3 = 3,
45 ADS1X15_CONFIG_MUX_SINGLE_0 = 4,
46 ADS1X15_CONFIG_MUX_SINGLE_1 = 5,
47 ADS1X15_CONFIG_MUX_SINGLE_2 = 6,
48 ADS1X15_CONFIG_MUX_SINGLE_3 = 7,
49 };
50
51 enum {
52 /* ADS111X, ADS101X samples per second */
53 /* 8, 128 samples per second */
54 ADS1X1X_CONFIG_DR_8_128 = 0,
55 /* 16, 250 samples per second */
56 ADS1X1X_CONFIG_DR_16_250 = 1,
57 /* 32, 490 samples per second */
58 ADS1X1X_CONFIG_DR_32_490 = 2,
59 /* 64, 920 samples per second */
60 ADS1X1X_CONFIG_DR_64_920 = 3,
61 /* 128, 1600 samples per second (default) */
62 ADS1X1X_CONFIG_DR_128_1600 = 4,
63 /* 250, 2400 samples per second */
64 ADS1X1X_CONFIG_DR_250_2400 = 5,
65 /* 475, 3300 samples per second */
66 ADS1X1X_CONFIG_DR_475_3300 = 6,
67 /* 860, 3300 samples per second */
68 ADS1X1X_CONFIG_DR_860_3300 = 7,
69 /* Default data rate */
70 ADS1X1X_CONFIG_DR_DEFAULT = ADS1X1X_CONFIG_DR_128_1600
71 };
72
73 enum {
74 /* +/-6.144V range = Gain 1/3 */
75 ADS1X1X_CONFIG_PGA_6144 = 0,
76 /* +/-4.096V range = Gain 1/2 */
77 ADS1X1X_CONFIG_PGA_4096 = 1,
78 /* +/-2.048V range = Gain 1 (default) */
79 ADS1X1X_CONFIG_PGA_2048 = 2,
80 /* +/-1.024V range = Gain 2 */
81 ADS1X1X_CONFIG_PGA_1024 = 3,
82 /* +/-0.512V range = Gain 4 */
83 ADS1X1X_CONFIG_PGA_512 = 4,
84 /* +/-0.256V range = Gain 8 */
85 ADS1X1X_CONFIG_PGA_256 = 5
86 };
87
88 enum {
89 ADS1X1X_CONFIG_MODE_CONTINUOUS = 0,
90 ADS1X1X_CONFIG_MODE_SINGLE_SHOT = 1,
91 };
92
93 enum {
94 /* Traditional comparator with hysteresis (default) */
95 ADS1X1X_CONFIG_COMP_MODE_TRADITIONAL = 0,
96 /* Window comparator */
97 ADS1X1X_CONFIG_COMP_MODE_WINDOW = 1
98 };
99
100 enum {
101 /* ALERT/RDY pin is low when active (default) */
102 ADS1X1X_CONFIG_COMP_POLARITY_ACTIVE_LO = 0,
103 /* ALERT/RDY pin is high when active */
104 ADS1X1X_CONFIG_COMP_POLARITY_ACTIVE_HI = 1
105 };
106
107 enum {
108 /* Non-latching comparator (default) */
109 ADS1X1X_CONFIG_COMP_NON_LATCHING = 0,
110 /* Latching comparator */
111 ADS1X1X_CONFIG_COMP_LATCHING = 1
112 };
113
114 enum {
115 /* Assert ALERT/RDY after one conversions */
116 ADS1X1X_CONFIG_COMP_QUEUE_1 = 0,
117 /* Assert ALERT/RDY after two conversions */
118 ADS1X1X_CONFIG_COMP_QUEUE_2 = 1,
119 /* Assert ALERT/RDY after four conversions */
120 ADS1X1X_CONFIG_COMP_QUEUE_4 = 2,
121 /* Disable the comparator and put ALERT/RDY in high state (default) */
122 ADS1X1X_CONFIG_COMP_QUEUE_NONE = 3
123 };
124
125 struct ads1x1x_config {
126 struct i2c_dt_spec bus;
127 const uint32_t odr_delay[8];
128 uint8_t resolution;
129 bool multiplexer;
130 bool pga;
131 };
132
133 struct ads1x1x_data {
134 const struct device *dev;
135 struct adc_context ctx;
136 k_timeout_t ready_time;
137 struct k_sem acq_sem;
138 int16_t *buffer;
139 int16_t *repeat_buffer;
140 struct k_thread thread;
141 bool differential;
142
143 K_KERNEL_STACK_MEMBER(stack, CONFIG_ADC_ADS1X1X_ACQUISITION_THREAD_STACK_SIZE);
144 };
145
ads1x1x_read_reg(const struct device * dev,enum ads1x1x_reg reg_addr,uint16_t * buf)146 static int ads1x1x_read_reg(const struct device *dev, enum ads1x1x_reg reg_addr, uint16_t *buf)
147 {
148 const struct ads1x1x_config *config = dev->config;
149 uint16_t reg_val;
150 int ret;
151
152 ret = i2c_burst_read_dt(&config->bus, reg_addr, (uint8_t *)®_val, sizeof(reg_val));
153 if (ret != 0) {
154 LOG_ERR("ADS1X1X[0x%X]: error reading register 0x%X (%d)", config->bus.addr,
155 reg_addr, ret);
156 return ret;
157 }
158
159 *buf = sys_be16_to_cpu(reg_val);
160
161 return 0;
162 }
163
ads1x1x_write_reg(const struct device * dev,enum ads1x1x_reg reg_addr,uint16_t reg_val)164 static int ads1x1x_write_reg(const struct device *dev, enum ads1x1x_reg reg_addr, uint16_t reg_val)
165 {
166 const struct ads1x1x_config *config = dev->config;
167 uint8_t buf[3];
168 int ret;
169
170 buf[0] = reg_addr;
171 sys_put_be16(reg_val, &buf[1]);
172
173 ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
174
175 if (ret != 0) {
176 LOG_ERR("ADS1X1X[0x%X]: error writing register 0x%X (%d)", config->bus.addr,
177 reg_addr, ret);
178 return ret;
179 }
180
181 return 0;
182 }
183
ads1x1x_start_conversion(const struct device * dev)184 static int ads1x1x_start_conversion(const struct device *dev)
185 {
186 /* send start sampling command */
187 uint16_t config;
188 int ret;
189
190 ret = ads1x1x_read_reg(dev, ADS1X1X_REG_CONFIG, &config);
191 if (ret != 0) {
192 return ret;
193 }
194 config |= ADS1X1X_CONFIG_OS;
195 ret = ads1x1x_write_reg(dev, ADS1X1X_REG_CONFIG, config);
196
197 return ret;
198 }
199
ads1x1x_acq_time_to_dr(const struct device * dev,uint16_t acq_time)200 static inline int ads1x1x_acq_time_to_dr(const struct device *dev, uint16_t acq_time)
201 {
202 struct ads1x1x_data *data = dev->data;
203 const struct ads1x1x_config *ads_config = dev->config;
204 const uint32_t *odr_delay = ads_config->odr_delay;
205 uint32_t odr_delay_us = 0;
206 int odr = -EINVAL;
207 uint16_t acq_value = ADC_ACQ_TIME_VALUE(acq_time);
208
209 /* The ADS1x1x uses samples per seconds units with the lowest being 8SPS
210 * and with acquisition_time only having 14b for time, this will not fit
211 * within here for microsecond units. Use Tick units and allow the user to
212 * specify the ODR directly.
213 */
214 if (acq_time != ADC_ACQ_TIME_DEFAULT && ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
215 return -EINVAL;
216 }
217
218 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
219 odr = ADS1X1X_CONFIG_DR_DEFAULT;
220 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_DEFAULT];
221 } else {
222 switch (acq_value) {
223 case ADS1X1X_CONFIG_DR_8_128:
224 odr = ADS1X1X_CONFIG_DR_8_128;
225 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_8_128];
226 break;
227 case ADS1X1X_CONFIG_DR_16_250:
228 odr = ADS1X1X_CONFIG_DR_16_250;
229 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_16_250];
230 break;
231 case ADS1X1X_CONFIG_DR_32_490:
232 odr = ADS1X1X_CONFIG_DR_32_490;
233 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_32_490];
234 break;
235 case ADS1X1X_CONFIG_DR_64_920:
236 odr = ADS1X1X_CONFIG_DR_64_920;
237 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_64_920];
238 break;
239 case ADS1X1X_CONFIG_DR_128_1600:
240 odr = ADS1X1X_CONFIG_DR_128_1600;
241 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_128_1600];
242 break;
243 case ADS1X1X_CONFIG_DR_250_2400:
244 odr = ADS1X1X_CONFIG_DR_250_2400;
245 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_250_2400];
246 break;
247 case ADS1X1X_CONFIG_DR_475_3300:
248 odr = ADS1X1X_CONFIG_DR_475_3300;
249 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_475_3300];
250 break;
251 case ADS1X1X_CONFIG_DR_860_3300:
252 odr = ADS1X1X_CONFIG_DR_860_3300;
253 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_860_3300];
254 break;
255 default:
256 break;
257 }
258 }
259
260 /* As per the datasheet, 25us is needed to wake-up from power down mode
261 */
262 odr_delay_us += 25;
263 data->ready_time = K_USEC(odr_delay_us);
264
265 return odr;
266 }
267
ads1x1x_wait_data_ready(const struct device * dev)268 static int ads1x1x_wait_data_ready(const struct device *dev)
269 {
270 int rc;
271 struct ads1x1x_data *data = dev->data;
272
273 k_sleep(data->ready_time);
274 uint16_t status = 0;
275
276 rc = ads1x1x_read_reg(dev, ADS1X1X_REG_CONFIG, &status);
277 if (rc != 0) {
278 return rc;
279 }
280
281 while (!(status & ADS1X1X_CONFIG_OS)) {
282 k_sleep(K_USEC(100));
283 rc = ads1x1x_read_reg(dev, ADS1X1X_REG_CONFIG, &status);
284 if (rc != 0) {
285 return rc;
286 }
287 }
288
289 return rc;
290 }
291
ads1x1x_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)292 static int ads1x1x_channel_setup(const struct device *dev,
293 const struct adc_channel_cfg *channel_cfg)
294 {
295 const struct ads1x1x_config *ads_config = dev->config;
296 struct ads1x1x_data *data = dev->data;
297 uint16_t config = 0;
298 int dr = 0;
299
300 if (channel_cfg->channel_id != 0) {
301 LOG_ERR("unsupported channel id '%d'", channel_cfg->channel_id);
302 return -ENOTSUP;
303 }
304
305 if (channel_cfg->reference != ADC_REF_INTERNAL) {
306 LOG_ERR("unsupported channel reference type '%d'", channel_cfg->reference);
307 return -ENOTSUP;
308 }
309
310 if (ads_config->multiplexer) {
311 /* the device has an input multiplexer */
312 if (channel_cfg->differential) {
313 if (channel_cfg->input_positive == 0 && channel_cfg->input_negative == 1) {
314 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_DIFF_0_1);
315 } else if (channel_cfg->input_positive == 0 &&
316 channel_cfg->input_negative == 3) {
317 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_DIFF_0_3);
318 } else if (channel_cfg->input_positive == 1 &&
319 channel_cfg->input_negative == 3) {
320 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_DIFF_1_3);
321 } else if (channel_cfg->input_positive == 2 &&
322 channel_cfg->input_negative == 3) {
323 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_DIFF_2_3);
324 } else {
325 LOG_ERR("unsupported input positive '%d' and input negative '%d'",
326 channel_cfg->input_positive, channel_cfg->input_negative);
327 return -ENOTSUP;
328 }
329 } else {
330 if (channel_cfg->input_positive == 0) {
331 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_SINGLE_0);
332 } else if (channel_cfg->input_positive == 1) {
333 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_SINGLE_1);
334 } else if (channel_cfg->input_positive == 2) {
335 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_SINGLE_2);
336 } else if (channel_cfg->input_positive == 3) {
337 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_SINGLE_3);
338 } else {
339 LOG_ERR("unsupported input positive '%d'",
340 channel_cfg->input_positive);
341 return -ENOTSUP;
342 }
343 }
344 } else {
345 /* only differential supported without multiplexer */
346 if (!((channel_cfg->differential) &&
347 (channel_cfg->input_positive == 0 && channel_cfg->input_negative == 1))) {
348 LOG_ERR("unsupported input positive '%d' and input negative '%d'",
349 channel_cfg->input_positive, channel_cfg->input_negative);
350 return -ENOTSUP;
351 }
352 }
353 /* store differential mode to determine supported resolution */
354 data->differential = channel_cfg->differential;
355
356 dr = ads1x1x_acq_time_to_dr(dev, channel_cfg->acquisition_time);
357 if (dr < 0) {
358 LOG_ERR("unsupported channel acquisition time 0x%02x",
359 channel_cfg->acquisition_time);
360 return -ENOTSUP;
361 }
362
363 config |= ADS1X1X_CONFIG_DR(dr);
364
365 if (ads_config->pga) {
366 /* programmable gain amplifier support */
367 switch (channel_cfg->gain) {
368 case ADC_GAIN_1_3:
369 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_6144);
370 break;
371 case ADC_GAIN_1_2:
372 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_4096);
373 break;
374 case ADC_GAIN_1:
375 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_2048);
376 break;
377 case ADC_GAIN_2:
378 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_1024);
379 break;
380 case ADC_GAIN_4:
381 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_512);
382 break;
383 case ADC_GAIN_8:
384 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_256);
385 break;
386 default:
387 LOG_ERR("unsupported channel gain '%d'", channel_cfg->gain);
388 return -ENOTSUP;
389 }
390 } else {
391 /* no programmable gain amplifier, so only allow ADC_GAIN_1 */
392 if (channel_cfg->gain != ADC_GAIN_1) {
393 LOG_ERR("unsupported channel gain '%d'", channel_cfg->gain);
394 return -ENOTSUP;
395 }
396 }
397
398 /* Only single shot supported */
399 config |= ADS1X1X_CONFIG_MODE;
400
401 /* disable comparator */
402 config |= ADS1X1X_CONFIG_COMP_MODE;
403
404 return ads1x1x_write_reg(dev, ADS1X1X_REG_CONFIG, config);
405 }
406
ads1x1x_validate_buffer_size(const struct adc_sequence * sequence)407 static int ads1x1x_validate_buffer_size(const struct adc_sequence *sequence)
408 {
409 size_t needed = sizeof(int16_t);
410
411 if (sequence->options) {
412 needed *= (1 + sequence->options->extra_samplings);
413 }
414
415 if (sequence->buffer_size < needed) {
416 return -ENOMEM;
417 }
418
419 return 0;
420 }
421
ads1x1x_validate_sequence(const struct device * dev,const struct adc_sequence * sequence)422 static int ads1x1x_validate_sequence(const struct device *dev, const struct adc_sequence *sequence)
423 {
424 const struct ads1x1x_config *config = dev->config;
425 struct ads1x1x_data *data = dev->data;
426 uint8_t resolution = data->differential ? config->resolution : config->resolution - 1;
427 int err;
428
429 if (sequence->resolution != resolution) {
430 LOG_ERR("unsupported resolution %d", sequence->resolution);
431 return -ENOTSUP;
432 }
433
434 if (sequence->channels != BIT(0)) {
435 LOG_ERR("only channel 0 supported");
436 return -ENOTSUP;
437 }
438
439 if (sequence->oversampling) {
440 LOG_ERR("oversampling not supported");
441 return -ENOTSUP;
442 }
443
444 err = ads1x1x_validate_buffer_size(sequence);
445 if (err) {
446 LOG_ERR("buffer size too small");
447 return -ENOTSUP;
448 }
449
450 return 0;
451 }
452
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)453 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
454 {
455 struct ads1x1x_data *data = CONTAINER_OF(ctx, struct ads1x1x_data, ctx);
456
457 if (repeat_sampling) {
458 data->buffer = data->repeat_buffer;
459 }
460 }
461
adc_context_start_sampling(struct adc_context * ctx)462 static void adc_context_start_sampling(struct adc_context *ctx)
463 {
464 struct ads1x1x_data *data = CONTAINER_OF(ctx, struct ads1x1x_data, ctx);
465 int ret;
466
467 data->repeat_buffer = data->buffer;
468
469 ret = ads1x1x_start_conversion(data->dev);
470 if (ret != 0) {
471 /* if we fail to complete the I2C operations to start
472 * sampling, return an immediate error (likely -EIO) rather
473 * than handing it off to the acquisition thread.
474 */
475 adc_context_complete(ctx, ret);
476 return;
477 }
478 k_sem_give(&data->acq_sem);
479 }
480
ads1x1x_adc_start_read(const struct device * dev,const struct adc_sequence * sequence)481 static int ads1x1x_adc_start_read(const struct device *dev, const struct adc_sequence *sequence)
482 {
483 int rc;
484 struct ads1x1x_data *data = dev->data;
485
486 rc = ads1x1x_validate_sequence(dev, sequence);
487 if (rc != 0) {
488 return rc;
489 }
490
491 data->buffer = sequence->buffer;
492
493 adc_context_start_read(&data->ctx, sequence);
494
495 return adc_context_wait_for_completion(&data->ctx);
496 }
497
ads1x1x_adc_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)498 static int ads1x1x_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
499 struct k_poll_signal *async)
500 {
501 int rc;
502 struct ads1x1x_data *data = dev->data;
503
504 adc_context_lock(&data->ctx, async ? true : false, async);
505 rc = ads1x1x_adc_start_read(dev, sequence);
506 adc_context_release(&data->ctx, rc);
507
508 return rc;
509 }
510
ads1x1x_adc_perform_read(const struct device * dev)511 static int ads1x1x_adc_perform_read(const struct device *dev)
512 {
513 int rc;
514 struct ads1x1x_data *data = dev->data;
515 const struct ads1x1x_config *config = dev->config;
516 int16_t buf;
517
518 rc = ads1x1x_read_reg(dev, ADS1X1X_REG_CONV, &buf);
519 if (rc != 0) {
520 adc_context_complete(&data->ctx, rc);
521 return rc;
522 }
523 /* The ads101x stores it's 12b data in the upper part
524 * while the ads111x uses all 16b in the register, so
525 * shift down. Data is also signed, so perform
526 * division rather than shifting
527 */
528 *data->buffer++ = buf / (1 << (16 - config->resolution));
529
530 adc_context_on_sampling_done(&data->ctx, dev);
531
532 return rc;
533 }
534
ads1x1x_read(const struct device * dev,const struct adc_sequence * sequence)535 static int ads1x1x_read(const struct device *dev, const struct adc_sequence *sequence)
536 {
537 return ads1x1x_adc_read_async(dev, sequence, NULL);
538 }
539
ads1x1x_acquisition_thread(void * p1,void * p2,void * p3)540 static void ads1x1x_acquisition_thread(void *p1, void *p2, void *p3)
541 {
542 ARG_UNUSED(p2);
543 ARG_UNUSED(p3);
544
545 const struct device *dev = p1;
546 struct ads1x1x_data *data = dev->data;
547 int rc;
548
549 while (true) {
550 k_sem_take(&data->acq_sem, K_FOREVER);
551
552 rc = ads1x1x_wait_data_ready(dev);
553 if (rc != 0) {
554 LOG_ERR("failed to get ready status (err %d)", rc);
555 adc_context_complete(&data->ctx, rc);
556 continue;
557 }
558
559 ads1x1x_adc_perform_read(dev);
560 }
561 }
562
ads1x1x_init(const struct device * dev)563 static int ads1x1x_init(const struct device *dev)
564 {
565 const struct ads1x1x_config *config = dev->config;
566 struct ads1x1x_data *data = dev->data;
567
568 data->dev = dev;
569
570 k_sem_init(&data->acq_sem, 0, 1);
571
572 if (!device_is_ready(config->bus.bus)) {
573 LOG_ERR("I2C bus %s not ready", config->bus.bus->name);
574 return -ENODEV;
575 }
576
577 k_tid_t tid =
578 k_thread_create(&data->thread, data->stack, K_THREAD_STACK_SIZEOF(data->stack),
579 ads1x1x_acquisition_thread, (void *)dev, NULL,
580 NULL, CONFIG_ADC_ADS1X1X_ACQUISITION_THREAD_PRIO, 0, K_NO_WAIT);
581 k_thread_name_set(tid, "adc_ads1x1x");
582
583 adc_context_unlock_unconditionally(&data->ctx);
584
585 return 0;
586 }
587
588 static const struct adc_driver_api ads1x1x_api = {
589 .channel_setup = ads1x1x_channel_setup,
590 .read = ads1x1x_read,
591 .ref_internal = 2048,
592 #ifdef CONFIG_ADC_ASYNC
593 .read_async = ads1x1x_adc_read_async,
594 #endif
595 };
596
597 #define DT_INST_ADS1X1X(inst, t) DT_INST(inst, ti_ads##t)
598
599 #define ADS1X1X_INIT(t, n, odr_delay_us, res, mux, pgab) \
600 static const struct ads1x1x_config ads##t##_config_##n = { \
601 .bus = I2C_DT_SPEC_GET(DT_INST_ADS1X1X(n, t)), \
602 .odr_delay = odr_delay_us, \
603 .resolution = res, \
604 .multiplexer = mux, \
605 .pga = pgab, \
606 }; \
607 static struct ads1x1x_data ads##t##_data_##n = { \
608 ADC_CONTEXT_INIT_LOCK(ads##t##_data_##n, ctx), \
609 ADC_CONTEXT_INIT_TIMER(ads##t##_data_##n, ctx), \
610 ADC_CONTEXT_INIT_SYNC(ads##t##_data_##n, ctx), \
611 }; \
612 DEVICE_DT_DEFINE(DT_INST_ADS1X1X(n, t), ads1x1x_init, NULL, &ads##t##_data_##n, \
613 &ads##t##_config_##n, POST_KERNEL, CONFIG_ADC_ADS1X1X_INIT_PRIORITY, \
614 &ads1x1x_api);
615
616 /* The ADS111X provides 16 bits of data in binary two's complement format
617 * A positive full-scale (+FS) input produces an output code of 7FFFh and a
618 * negative full-scale (–FS) input produces an output code of 8000h. Single
619 * ended signal measurements only only use the positive code range from
620 * 0000h to 7FFFh
621 */
622 #define ADS111X_RESOLUTION 16
623
624 /*
625 * Approximated ADS111x acquisition times in microseconds. These are
626 * used for the initial delay when polling for data ready.
627 * {8 SPS, 16 SPS, 32 SPS, 64 SPS, 128 SPS (default), 250 SPS, 475 SPS, 860 SPS}
628 */
629 #define ADS111X_ODR_DELAY_US \
630 { \
631 125000, 62500, 31250, 15625, 7813, 4000, 2105, 1163 \
632 }
633
634 /*
635 * ADS1115: 16 bit, multiplexer, programmable gain amplifier
636 */
637 #define ADS1115_INIT(n) ADS1X1X_INIT(1115, n, ADS111X_ODR_DELAY_US, ADS111X_RESOLUTION, true, true)
638 #undef DT_DRV_COMPAT
639 #define DT_DRV_COMPAT ti_ads1115
640 DT_INST_FOREACH_STATUS_OKAY(ADS1115_INIT)
641
642 /*
643 * ADS1114: 16 bit, no multiplexer, programmable gain amplifier
644 */
645 #define ADS1114_INIT(n) ADS1X1X_INIT(1114, n, ADS111X_ODR_DELAY_US, ADS111X_RESOLUTION, false, true)
646 #undef DT_DRV_COMPAT
647 #define DT_DRV_COMPAT ti_ads1114
648 DT_INST_FOREACH_STATUS_OKAY(ADS1114_INIT)
649
650 /*
651 * ADS1113: 16 bit, no multiplexer, no programmable gain amplifier
652 */
653 #define ADS1113_INIT(n) \
654 ADS1X1X_INIT(1113, n, ADS111X_ODR_DELAY_US, ADS111X_RESOLUTION, false, false)
655 #undef DT_DRV_COMPAT
656 #define DT_DRV_COMPAT ti_ads1113
657 DT_INST_FOREACH_STATUS_OKAY(ADS1113_INIT)
658
659 /* The ADS101X provides 12 bits of data in binary two's complement format
660 * A positive full-scale (+FS) input produces an output code of 7FFh and a
661 * negative full-scale (–FS) input produces an output code of 800h. Single
662 * ended signal measurements only only use the positive code range from
663 * 000h to 7FFh
664 */
665 #define ADS101X_RESOLUTION 12
666
667 /*
668 * Approximated ADS101x acquisition times in microseconds. These are
669 * used for the initial delay when polling for data ready.
670 * {128 SPS, 250 SPS, 490 SPS, 920 SPS, 1600 SPS (default), 2400 SPS, 3300 SPS, 3300 SPS}
671 */
672 #define ADS101X_ODR_DELAY_US \
673 { \
674 7813, 4000, 2041, 1087, 625, 417, 303, 303 \
675 }
676
677 /*
678 * ADS1015: 12 bit, multiplexer, programmable gain amplifier
679 */
680 #define ADS1015_INIT(n) ADS1X1X_INIT(1015, n, ADS101X_ODR_DELAY_US, ADS101X_RESOLUTION, true, true)
681 #undef DT_DRV_COMPAT
682 #define DT_DRV_COMPAT ti_ads1015
683 DT_INST_FOREACH_STATUS_OKAY(ADS1015_INIT)
684
685 /*
686 * ADS1014: 12 bit, no multiplexer, programmable gain amplifier
687 */
688 #define ADS1014_INIT(n) ADS1X1X_INIT(1014, n, ADS101X_ODR_DELAY_US, ADS101X_RESOLUTION, false, true)
689 #undef DT_DRV_COMPAT
690 #define DT_DRV_COMPAT ti_ads1014
691 DT_INST_FOREACH_STATUS_OKAY(ADS1014_INIT)
692
693 /*
694 * ADS1013: 12 bit, no multiplexer, no programmable gain amplifier
695 */
696 #define ADS1013_INIT(n) \
697 ADS1X1X_INIT(1013, n, ADS101X_ODR_DELAY_US, ADS101X_RESOLUTION, false, false)
698 #undef DT_DRV_COMPAT
699 #define DT_DRV_COMPAT ti_ads1013
700 DT_INST_FOREACH_STATUS_OKAY(ADS1013_INIT)
701
