1 /*
2 * Copyright (c) 2022-2024 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c
21 * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c
22 */
23
24 #include "tfm_hal_device_header.h"
25
26 /*----------------------------------------------------------------------------
27 External References
28 *----------------------------------------------------------------------------*/
29 extern uint32_t __INITIAL_SP;
30 extern uint32_t __STACK_LIMIT;
31
32 extern __NO_RETURN void __PROGRAM_START(void);
33
34 /*----------------------------------------------------------------------------
35 Internal References
36 *----------------------------------------------------------------------------*/
37 __NO_RETURN void Reset_Handler(void);
38
39 /*----------------------------------------------------------------------------
40 Exception / Interrupt Handler
41 *----------------------------------------------------------------------------*/
42 /* Exception handler that blocks execution. */
exception_handler(void)43 __NO_RETURN void exception_handler(void)
44 {
45 while (1);
46 }
47
48 /* No IRQs are enabled at boot, so this handler should be unreachable. In case
49 * it is ever reached, disable the IRQ that was triggered and return. In debug
50 * builds, block execution to catch the bug.
51 */
invalid_irq_handler(void)52 void invalid_irq_handler(void)
53 {
54 #ifndef NDEBUG
55 while (1);
56 #else
57 NVIC_DisableIRQ((IRQn_Type)((int32_t)__get_IPSR() - 16));
58 #endif
59 }
60
61 /*----------------------------------------------------------------------------
62 Exception / Interrupt Vector table
63 *----------------------------------------------------------------------------*/
64
65 #if defined ( __GNUC__ )
66 #pragma GCC diagnostic push
67 #pragma GCC diagnostic ignored "-Wpedantic"
68 #endif
69
70 extern const VECTOR_TABLE_Type __VECTOR_TABLE[];
71 const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
72 (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
73 Reset_Handler, /* Reset Handler */
74 exception_handler, /* -14: NMI Handler */
75 exception_handler, /* -13: Hard Fault Handler */
76 exception_handler, /* -12: MPU Fault Handler */
77 exception_handler, /* -11: Bus Fault Handler */
78 exception_handler, /* -10: Usage Fault Handler */
79 exception_handler, /* -9: Secure Fault Handler */
80 0, /* Reserved */
81 0, /* Reserved */
82 0, /* Reserved */
83 exception_handler, /* -5: SVCall Handler */
84 exception_handler, /* -4: Debug Monitor Handler */
85 0, /* Reserved */
86 exception_handler, /* -2: PendSV Handler */
87 exception_handler, /* -1: SysTick Handler */
88
89 invalid_irq_handler, /* 0: Non-Secure Watchdog Reset Request Handler */
90 invalid_irq_handler, /* 1: Non-Secure Watchdog Handler */
91 invalid_irq_handler, /* 2: SLOWCLK Timer Handler */
92 invalid_irq_handler, /* 3: TIMER 0 Handler */
93 invalid_irq_handler, /* 4: TIMER 1 Handler */
94 invalid_irq_handler, /* 5: TIMER 2 Handler */
95 0, /* 6: Reserved */
96 0, /* 7: Reserved */
97 0, /* 8: Reserved */
98 invalid_irq_handler, /* 9: MPC Combined (Secure) Handler */
99 invalid_irq_handler, /* 10: PPC Combined (Secure) Handler */
100 invalid_irq_handler, /* 11: MSC Combined (Secure) Handler */
101 invalid_irq_handler, /* 12: Bridge Error (Secure) Handler */
102 0, /* 13: Reserved */
103 invalid_irq_handler, /* 14: PPU Combined (Secure) Handler */
104 0, /* 15: Reserved */
105 invalid_irq_handler, /* 16: NPU0 Handler */
106 invalid_irq_handler, /* 17: NPU1 Handler */
107 invalid_irq_handler, /* 18: NPU2 Handler */
108 invalid_irq_handler, /* 19: NPU3 Handler */
109 invalid_irq_handler, /* 20: KMU (Secure) Handler */
110 0, /* 21: Reserved */
111 0, /* 22: Reserved */
112 0, /* 23: Reserved */
113 invalid_irq_handler, /* 24: DMA350 Combined (Secure) Handler */
114 invalid_irq_handler, /* 25: DMA350 Combined (Non-Secure) Handler */
115 invalid_irq_handler, /* 26: DMA350 Security Violation Handler */
116 invalid_irq_handler, /* 27: TIMER 3 AON Handler */
117 invalid_irq_handler, /* 28: CPU0 CTI IRQ 0 Handler */
118 invalid_irq_handler, /* 29: CPU0 CTI IRQ 1 Handler */
119 0, /* 30: Reserved */
120 0, /* 31: Reserved */
121
122 /* External interrupts */
123 invalid_irq_handler, /* 32: SAM Critical Security Fault (Secure) Handler */
124 invalid_irq_handler, /* 33: SAM Security Fault (Secure) Handler */
125 invalid_irq_handler, /* 34: GPIO Combined (Secure) Handler */
126 invalid_irq_handler, /* 35: Secure Debug Channel Handler */
127 invalid_irq_handler, /* 36: FPU Exception Handler */
128 invalid_irq_handler, /* 37: SRAM or TRAM Corrected ECC Error (Secure) Handler */
129 invalid_irq_handler, /* 38: Secure I-Cache (Secure) Handler */
130 invalid_irq_handler, /* 39: ATU (Secure) Handler */
131 invalid_irq_handler, /* 40: CMU MHU 0 Sender Handler */
132 invalid_irq_handler, /* 41: CMU MHU 0 Receiver Handler */
133 invalid_irq_handler, /* 42: CMU MHU 1 Sender Handler */
134 invalid_irq_handler, /* 43: CMU MHU 1 Receiver Handler */
135 invalid_irq_handler, /* 44: CMU MHU 2 Sender Handler */
136 invalid_irq_handler, /* 45: CMU MHU 2 Receiver Handler */
137 invalid_irq_handler, /* 46: CMU MHU 3 Sender Handler */
138 invalid_irq_handler, /* 47: CMU MHU 3 Receiver Handler */
139 invalid_irq_handler, /* 48: CMU MHU 4 Sender Handler */
140 invalid_irq_handler, /* 49: CMU MHU 4 Receiver Handler */
141 invalid_irq_handler, /* 50: CMU MHU 5 Sender Handler */
142 invalid_irq_handler, /* 51: CMU MHU 5 Receiver Handler */
143 invalid_irq_handler, /* 52: CMU MHU 6 Sender Handler */
144 invalid_irq_handler, /* 53: CMU MHU 6 Receiver Handler */
145 invalid_irq_handler, /* 54: CMU MHU 7 Sender Handler */
146 invalid_irq_handler, /* 55: CMU MHU 7 Receiver Handler */
147 invalid_irq_handler, /* 56: CMU MHU 8 Sender Handler */
148 invalid_irq_handler, /* 57: CMU MHU 8 Receiver Handler */
149 invalid_irq_handler, /* 58: Crypto Engine (Secure) Handler */
150 invalid_irq_handler, /* 59: SoC System Timer 0 AON Handler */
151 invalid_irq_handler, /* 60: SoC System Timer 1 AON Handler */
152 invalid_irq_handler, /* 61: SRAM ECC Detected Partial Write (Secure) Handler */
153 invalid_irq_handler, /* 62: Integrity Checker Handler */
154 0, /* 63: Reserved */
155 0, /* 64: Reserved */
156 0, /* 65: Reserved */
157 0, /* 66: Reserved */
158 0, /* 67: Reserved */
159 0, /* 68: Reserved */
160 0, /* 69: Reserved */
161 0, /* 70: Reserved */
162 0, /* 71: Reserved */
163 0, /* 72: Reserved */
164 0, /* 73: Reserved */
165 0, /* 74: Reserved */
166 0, /* 75: Reserved */
167 0, /* 76: Reserved */
168 0, /* 77: Reserved */
169 0, /* 78: Reserved */
170 0, /* 79: Reserved */
171 0, /* 80: Reserved */
172 0, /* 81: Reserved */
173 0, /* 82: Reserved */
174 0, /* 83: Reserved */
175 0, /* 84: Reserved */
176 0, /* 85: Reserved */
177 0, /* 86: Reserved */
178 0, /* 87: Reserved */
179 0, /* 88: Reserved */
180 0, /* 89: Reserved */
181 0, /* 90: Reserved */
182 0, /* 91: Reserved */
183 0, /* 92: Reserved */
184 0, /* 93: Reserved */
185 0, /* 94: Reserved */
186 0, /* 95: Reserved */
187 };
188
189 #if defined ( __GNUC__ )
190 #pragma GCC diagnostic pop
191 #endif
192
193 /*----------------------------------------------------------------------------
194 Reset Handler called on controller reset
195 *----------------------------------------------------------------------------*/
Reset_Handler(void)196 void Reset_Handler(void)
197 {
198 __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
199
200 SystemInit(); /* CMSIS System Initialization */
201 __PROGRAM_START(); /* Enter PreMain (C library entry point) */
202 }
203
