1;/*
2; * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
3; *
4; * Licensed under the Apache License, Version 2.0 (the "License");
5; * you may not use this file except in compliance with the License.
6; * You may obtain a copy of the License at
7; *
8; *     http://www.apache.org/licenses/LICENSE-2.0
9; *
10; * Unless required by applicable law or agreed to in writing, software
11; * distributed under the License is distributed on an "AS IS" BASIS,
12; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13; * See the License for the specific language governing permissions and
14; * limitations under the License.
15; *
16; *
17; * This file is derivative of CMSIS V5.00 gcc_arm.ld
18; */
19
20/* Linker script to configure memory regions. */
21/* This file will be run trough the pre-processor. */
22
23#include "region_defs.h"
24
25MEMORY
26{
27    FLASH (rx)  : ORIGIN = BL1_2_CODE_START, LENGTH = BL1_2_CODE_SIZE
28    RAM   (rwx) : ORIGIN = BL1_2_DATA_START, LENGTH = BL1_2_DATA_SIZE
29}
30
31__heap_size__  = BL1_2_HEAP_SIZE;
32__msp_stack_size__ = BL1_2_MSP_STACK_SIZE;
33
34/* Library configurations */
35GROUP(libgcc.a libc.a libm.a libnosys.a)
36
37ENTRY(Reset_Handler)
38
39SECTIONS
40{
41    .text :
42    {
43        KEEP(*(.vectors))
44        __Vectors_End = .;
45        __Vectors_Size = __Vectors_End - __Vectors;
46        __end__ = .;
47
48        *(.text*)
49
50        KEEP(*(.init))
51        KEEP(*(.fini))
52
53
54        /* .ctors */
55        *crtbegin.o(.ctors)
56        *crtbegin?.o(.ctors)
57        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
58        *(SORT(.ctors.*))
59        *(.ctors)
60
61        /* .dtors */
62         *crtbegin.o(.dtors)
63         *crtbegin?.o(.dtors)
64         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
65         *(SORT(.dtors.*))
66         *(.dtors)
67
68        *(.rodata*)
69
70        KEEP(*(.eh_frame*))
71    } > FLASH
72
73    .ARM.extab :
74    {
75        *(.ARM.extab* .gnu.linkonce.armextab.*)
76    } > FLASH
77
78    __exidx_start = .;
79    .ARM.exidx :
80    {
81        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
82    } > FLASH
83    __exidx_end = .;
84
85    /* To copy multiple ROM to RAM sections,
86     * define etext2/data2_start/data2_end and
87     * define __STARTUP_COPY_MULTIPLE in startup file */
88    .copy.table :
89    {
90        . = ALIGN(4);
91        __copy_table_start__ = .;
92        LONG (__etext)
93        LONG (__data_start__)
94        LONG ((__data_end__ - __data_start__) / 4)
95        LONG (DEFINED(__etext2) ? __etext2 : 0)
96        LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
97        LONG (DEFINED(__data2_start__) ? ((__data2_end__ - __data2_start__) / 4) : 0)
98        __copy_table_end__ = .;
99    } > FLASH
100
101    /* To clear multiple BSS sections,
102     * uncomment .zero.table section and,
103     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup file */
104    .zero.table :
105    {
106        . = ALIGN(4);
107        __zero_table_start__ = .;
108        LONG (__bss_start__)
109        LONG ((__bss_end__ - __bss_start__) / 4)
110        LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
111        LONG (DEFINED(__bss2_start__) ? ((__bss2_end__ - __bss2_start__) / 4) : 0)
112        __zero_table_end__ = .;
113    } > FLASH
114
115    __etext = ALIGN(4);
116
117    .tfm_bl2_shared_data : ALIGN(32)
118    {
119        . += BOOT_TFM_SHARED_DATA_SIZE;
120    } > RAM
121    Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data);
122    Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data);
123
124    .data : AT (__etext)
125    {
126        __data_start__ = .;
127        *(vtable)
128        *(.data*)
129
130        . = ALIGN(4);
131        /* preinit data */
132        PROVIDE_HIDDEN (__preinit_array_start = .);
133        KEEP(*(.preinit_array))
134        PROVIDE_HIDDEN (__preinit_array_end = .);
135
136        . = ALIGN(4);
137        /* init data */
138        PROVIDE_HIDDEN (__init_array_start = .);
139        KEEP(*(SORT(.init_array.*)))
140        KEEP(*(.init_array))
141        PROVIDE_HIDDEN (__init_array_end = .);
142
143
144        . = ALIGN(4);
145        /* finit data */
146        PROVIDE_HIDDEN (__fini_array_start = .);
147        KEEP(*(SORT(.fini_array.*)))
148        KEEP(*(.fini_array))
149        PROVIDE_HIDDEN (__fini_array_end = .);
150
151        KEEP(*(.jcr*))
152        . = ALIGN(4);
153        /* All data end */
154        __data_end__ = .;
155
156    } > RAM
157    Image$$ER_DATA$$Base = ADDR(.data);
158
159    .bss :
160    {
161        . = ALIGN(4);
162        __bss_start__ = .;
163        *(.bss*)
164        *(COMMON)
165        . = ALIGN(4);
166        __bss_end__ = .;
167    } > RAM
168
169    bss_size = __bss_end__ - __bss_start__;
170
171    .msp_stack : ALIGN(32)
172    {
173        . += __msp_stack_size__;
174    } > RAM
175    Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack);
176    Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
177
178    .heap : ALIGN(8)
179    {
180        . = ALIGN(8);
181        __end__ = .;
182        PROVIDE(end = .);
183        __HeapBase = .;
184        . += __heap_size__;
185        __HeapLimit = .;
186        __heap_limit = .; /* Add for _sbrk */
187    } > RAM
188    Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
189
190    PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
191}
192