1;/*
2; * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
3; *
4; * Licensed under the Apache License, Version 2.0 (the "License");
5; * you may not use this file except in compliance with the License.
6; * You may obtain a copy of the License at
7; *
8; *     http://www.apache.org/licenses/LICENSE-2.0
9; *
10; * Unless required by applicable law or agreed to in writing, software
11; * distributed under the License is distributed on an "AS IS" BASIS,
12; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13; * See the License for the specific language governing permissions and
14; * limitations under the License.
15; *
16; *
17; * This file is derivative of CMSIS V5.00 gcc_arm.ld
18; */
19
20/* Linker script to configure memory regions. */
21/* This file will be run trough the pre-processor. */
22
23#include "region_defs.h"
24
25MEMORY
26{
27    FLASH (rx)  : ORIGIN = BL1_1_CODE_START, LENGTH = BL1_1_CODE_SIZE
28    RAM   (rwx) : ORIGIN = BL1_1_DATA_START, LENGTH = BL1_1_DATA_SIZE
29}
30
31__heap_size__  = BL1_1_HEAP_SIZE;
32__msp_stack_size__ = BL1_1_MSP_STACK_SIZE;
33
34/* Library configurations */
35GROUP(libgcc.a libc.a libm.a libnosys.a)
36
37ENTRY(Reset_Handler)
38
39SECTIONS
40{
41    .text :
42    {
43        KEEP(*(.vectors))
44        __Vectors_End = .;
45        __Vectors_Size = __Vectors_End - __Vectors;
46        __end__ = .;
47
48        *(.text*)
49
50        KEEP(*shared_lib*:*(.text*))
51        KEEP(*bl1_tests_shared*:*(.text*))
52        KEEP(*bl1_crypto_hw*:*(.text*))
53        KEEP(*boot_hal_bl1*(.text*))
54        KEEP(*(.init))
55        KEEP(*(.fini))
56
57
58        /* .ctors */
59        *crtbegin.o(.ctors)
60        *crtbegin?.o(.ctors)
61        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
62        *(SORT(.ctors.*))
63        *(.ctors)
64
65        /* .dtors */
66         *crtbegin.o(.dtors)
67         *crtbegin?.o(.dtors)
68         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
69         *(SORT(.dtors.*))
70         *(.dtors)
71
72        *(.rodata*)
73
74        KEEP(*(.eh_frame*))
75    } > FLASH
76
77    .ARM.extab :
78    {
79        *(.ARM.extab* .gnu.linkonce.armextab.*)
80    } > FLASH
81
82    __exidx_start = .;
83    .ARM.exidx :
84    {
85        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
86    } > FLASH
87    __exidx_end = .;
88
89    /* To copy multiple ROM to RAM sections,
90     * define etext2/data2_start/data2_end and
91     * define __STARTUP_COPY_MULTIPLE in startup file */
92    .copy.table :
93    {
94        . = ALIGN(4);
95        __copy_table_start__ = .;
96        LONG (__etext)
97        LONG (__data_start__)
98        LONG ((__data_end__ - __data_start__) / 4)
99        LONG (DEFINED(__etext2) ? __etext2 : 0)
100        LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
101        LONG (DEFINED(__data2_start__) ? ((__data2_end__ - __data2_start__) / 4) : 0)
102        __copy_table_end__ = .;
103    } > FLASH
104
105    /* To clear multiple BSS sections,
106     * uncomment .zero.table section and,
107     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup file */
108    .zero.table :
109    {
110        . = ALIGN(4);
111        __zero_table_start__ = .;
112        LONG (__bss_start__)
113        LONG ((__bss_end__ - __bss_start__) / 4)
114        LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
115        LONG (DEFINED(__bss2_start__) ? ((__bss2_end__ - __bss2_start__) / 4) : 0)
116        __zero_table_end__ = .;
117    } > FLASH
118
119    __etext = ALIGN(4);
120
121    .tfm_bl2_shared_data : ALIGN(32)
122    {
123        . += BOOT_TFM_SHARED_DATA_SIZE;
124    } > RAM
125    Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data);
126    Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data);
127
128    Image$$BL1_1_ER_DATA_START$$Base = .;
129    .data : AT (__etext)
130    {
131        __data_start__ = .;
132        *(vtable)
133        *(.data*)
134
135        . = ALIGN(4);
136        /* preinit data */
137        PROVIDE_HIDDEN (__preinit_array_start = .);
138        KEEP(*(.preinit_array))
139        PROVIDE_HIDDEN (__preinit_array_end = .);
140
141        . = ALIGN(4);
142        /* init data */
143        PROVIDE_HIDDEN (__init_array_start = .);
144        KEEP(*(SORT(.init_array.*)))
145        KEEP(*(.init_array))
146        PROVIDE_HIDDEN (__init_array_end = .);
147
148
149        . = ALIGN(4);
150        /* finit data */
151        PROVIDE_HIDDEN (__fini_array_start = .);
152        KEEP(*(SORT(.fini_array.*)))
153        KEEP(*(.fini_array))
154        PROVIDE_HIDDEN (__fini_array_end = .);
155
156        KEEP(*(.jcr*))
157        . = ALIGN(4);
158        /* All data end */
159        __data_end__ = .;
160
161    } > RAM
162    Image$$ER_DATA$$Base = ADDR(.data);
163
164    .bss :
165    {
166        . = ALIGN(4);
167        __bss_start__ = .;
168        *(.bss*)
169        *(COMMON)
170        . = ALIGN(4);
171        __bss_end__ = .;
172    } > RAM
173
174    bss_size = __bss_end__ - __bss_start__;
175
176    .msp_stack : ALIGN(32)
177    {
178        . += __msp_stack_size__;
179    } > RAM
180    Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack);
181    Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
182
183    .heap : ALIGN(8)
184    {
185        . = ALIGN(8);
186        __end__ = .;
187        PROVIDE(end = .);
188        __HeapBase = .;
189        . += __heap_size__;
190        __HeapLimit = .;
191        __heap_limit = .; /* Add for _sbrk */
192    } > RAM
193    Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap);
194
195    PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
196    Image$$BL1_1_ER_DATA_LIMIT$$Base = .;
197
198    Image$$BL1_2_ER_DATA_START$$Base = BL1_2_DATA_START;
199    Image$$BL1_2_ER_DATA_LIMIT$$Base = BL1_2_DATA_START + BL1_2_DATA_SIZE;
200}
201