1/*
2 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *     http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "region_defs.h"
18
19LR_CODE BL1_2_CODE_START {
20    ER_CODE BL1_2_CODE_START BL1_2_CODE_SIZE {
21        *.o (RESET +First)
22        * (+RO)
23    }
24
25    TFM_SHARED_DATA BOOT_TFM_SHARED_DATA_BASE ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE {
26    }
27
28    ER_DATA BL1_2_DATA_START {
29        * (+ZI +RW)
30    }
31
32    /* MSP */
33    ARM_LIB_STACK +0 ALIGN 32 EMPTY BL1_2_MSP_STACK_SIZE {
34    }
35
36    ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL1_2_HEAP_SIZE {
37    }
38
39    /* This empty, zero long execution region is here to mark the limit address
40     * of the last execution region that is allocated in SRAM.
41     */
42    SRAM_WATERMARK +0 EMPTY 0x0 {
43    }
44
45    /* Make sure that the sections allocated in the SRAM does not exceed the
46     * size of the SRAM available.
47     */
48    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= BL1_2_DATA_START + BL1_2_DATA_SIZE)
49}
50