1/*
2 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *     http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "region_defs.h"
18
19LR_CODE BL1_1_CODE_START {
20    ER_CODE BL1_1_CODE_START BL1_1_CODE_SIZE {
21        *.o (RESET +First)
22        * (+RO)
23    }
24
25    TFM_SHARED_DATA BOOT_TFM_SHARED_DATA_BASE ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE {
26    }
27
28    BL1_1_ER_DATA_START +0 EMPTY 0x0 {
29    }
30
31    ER_DATA +0 {
32        * (+ZI +RW)
33    }
34
35    /* MSP */
36    ARM_LIB_STACK +0 ALIGN 32 EMPTY BL1_1_MSP_STACK_SIZE {
37    }
38
39    ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL1_1_HEAP_SIZE {
40    }
41
42    /* This empty, zero long execution region is here to mark the limit address
43     * of the last execution region that is allocated in SRAM.
44     */
45    SRAM_WATERMARK +0 EMPTY 0x0 {
46    }
47
48    /* Make sure that the sections allocated in the SRAM does not exceed the
49     * size of the SRAM available.
50     */
51    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= BL1_1_DATA_START + BL1_1_DATA_SIZE)
52
53    BL1_1_ER_DATA_LIMIT +0 EMPTY 0x0 {
54    }
55
56    BL1_2_ER_DATA_START BL1_2_DATA_START EMPTY 0x0 {
57    }
58
59    BL1_2_ER_DATA_LIMIT BL1_2_DATA_START + BL1_2_DATA_SIZE EMPTY 0x0 {
60    }
61}
62