1 /* 2 * Copyright 2021-2024 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _WIFI_BT_MODULE_CONFIG_H_ 9 #define _WIFI_BT_MODULE_CONFIG_H_ 10 11 /* Wi-Fi boards configuration list */ 12 13 /* AzureWave AW-NM191-uSD */ 14 #if defined(WIFI_88W8801_BOARD_AW_NM191_USD) 15 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 16 #define SD8801 17 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 18 #define WIFI_BT_USE_USD_INTERFACE 19 #define WLAN_ED_MAC_CTRL \ 20 { \ 21 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x1B \ 22 } 23 24 /* AzureWave AW-NM191MA */ 25 #elif defined(WIFI_88W8801_BOARD_AW_NM191MA) 26 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 27 #define SD8801 28 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 29 #define WIFI_BT_USE_M2_INTERFACE 30 #define WLAN_ED_MAC_CTRL \ 31 { \ 32 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x1B \ 33 } 34 35 /* AzureWave AW-AM457-uSD */ 36 #elif defined(WIFI_IW416_BOARD_AW_AM457_USD) 37 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 38 #define SD8978 39 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 40 #define WIFI_BT_USE_USD_INTERFACE 41 #define OVERRIDE_CALIBRATION_DATA "WIFI_IW416_BOARD_AW_AM457_CAL_DATA_EXT.h" 42 #define WLAN_ED_MAC_CTRL \ 43 { \ 44 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ 45 } 46 47 /* AzureWave AW-AM457MA */ 48 #elif defined(WIFI_IW416_BOARD_AW_AM457MA) 49 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 50 #define SD8978 51 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 52 #define WIFI_BT_USE_M2_INTERFACE 53 #define OVERRIDE_CALIBRATION_DATA "WIFI_IW416_BOARD_AW_AM457_CAL_DATA_EXT.h" 54 #define WLAN_ED_MAC_CTRL \ 55 { \ 56 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ 57 } 58 59 /* AzureWave AW-AM510-uSD */ 60 #elif defined(WIFI_IW416_BOARD_AW_AM510_USD) 61 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 62 #define SD8978 63 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 64 #define CONFIG_BR_SCO_PCM_DIRECTION 1 65 #define WIFI_BT_USE_USD_INTERFACE 66 #define WLAN_ED_MAC_CTRL \ 67 { \ 68 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ 69 } 70 71 /* AzureWave AW-AM510MA */ 72 #elif defined(WIFI_IW416_BOARD_AW_AM510MA) 73 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 74 #define SD8978 75 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 76 #define CONFIG_BR_SCO_PCM_DIRECTION 1 77 #define WIFI_BT_USE_M2_INTERFACE 78 #define WLAN_ED_MAC_CTRL \ 79 { \ 80 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ 81 } 82 83 /* AzureWave AW-CM358-uSD */ 84 #elif defined(WIFI_88W8987_BOARD_AW_CM358_USD) 85 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 86 #define SD8987 87 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 88 #define SD_TIMING_MAX kSD_TimingDDR50Mode 89 #define WIFI_BT_USE_USD_INTERFACE 90 #define WLAN_ED_MAC_CTRL \ 91 { \ 92 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ 93 } 94 95 /* AzureWave AW-CM358MA */ 96 #elif defined(WIFI_88W8987_BOARD_AW_CM358MA) 97 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 98 #define SD8987 99 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 100 #define SD_TIMING_MAX kSD_TimingDDR50Mode 101 #define WIFI_BT_USE_M2_INTERFACE 102 #define WLAN_ED_MAC_CTRL \ 103 { \ 104 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ 105 } 106 107 /* Murata 2DS + Murata uSD-M.2 adapter */ 108 #elif defined(WIFI_88W8801_BOARD_MURATA_2DS_USD) 109 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_CA.h" 110 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_EU.h" 111 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_JP.h" 112 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_US.h" 113 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_WW.h" 114 #define SD8801 115 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 116 #define SD_TIMING_MAX kSD_TimingSDR25HighSpeedMode 117 #define WIFI_BT_USE_USD_INTERFACE 118 #define WLAN_ED_MAC_CTRL \ 119 { \ 120 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0E \ 121 } 122 123 /* Murata 2DS */ 124 #elif defined(WIFI_88W8801_BOARD_MURATA_2DS_M2) 125 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_CA.h" 126 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_EU.h" 127 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_JP.h" 128 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_US.h" 129 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_WW.h" 130 #define SD8801 131 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 132 #define SD_TIMING_MAX kSD_TimingSDR25HighSpeedMode 133 #define WIFI_BT_USE_M2_INTERFACE 134 #define WLAN_ED_MAC_CTRL \ 135 { \ 136 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0E \ 137 } 138 139 /* Murata 1XK + Murata uSD-M.2 adapter */ 140 #elif defined(WIFI_IW416_BOARD_MURATA_1XK_USD) 141 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_CA.h" 142 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_EU.h" 143 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_JP.h" 144 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_US.h" 145 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_WW.h" 146 #define SD8978 147 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 148 #define SD_TIMING_MAX kSD_TimingDDR50Mode 149 #define WIFI_BT_USE_USD_INTERFACE 150 #define WLAN_ED_MAC_CTRL \ 151 { \ 152 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \ 153 } 154 155 /* Murata 1XK */ 156 #elif defined(WIFI_IW416_BOARD_MURATA_1XK_M2) 157 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_CA.h" 158 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_EU.h" 159 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_JP.h" 160 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_US.h" 161 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_WW.h" 162 #define SD8978 163 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 164 #define SD_TIMING_MAX kSD_TimingDDR50Mode 165 #define WIFI_BT_USE_M2_INTERFACE 166 #define WLAN_ED_MAC_CTRL \ 167 { \ 168 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \ 169 } 170 171 /* Murata 1ZM + Murata uSD-M.2 adapter */ 172 #elif defined(WIFI_88W8987_BOARD_MURATA_1ZM_USD) 173 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_CA.h" 174 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_EU.h" 175 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_JP.h" 176 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_US.h" 177 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_WW.h" 178 #define SD8987 179 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 180 #define SD_TIMING_MAX kSD_TimingDDR50Mode 181 #define WIFI_BT_USE_USD_INTERFACE 182 #define WLAN_ED_MAC_CTRL \ 183 { \ 184 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x6, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \ 185 } 186 187 /* Murata 1ZM */ 188 #elif defined(WIFI_88W8987_BOARD_MURATA_1ZM_M2) 189 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_CA.h" 190 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_EU.h" 191 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_JP.h" 192 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_US.h" 193 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_WW.h" 194 #define SD8987 195 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 196 #define SD_TIMING_MAX kSD_TimingDDR50Mode 197 #define WIFI_BT_USE_M2_INTERFACE 198 #define WLAN_ED_MAC_CTRL \ 199 { \ 200 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x6, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \ 201 } 202 203 /* USD Firecrest module */ 204 #elif defined(WIFI_IW612_BOARD_RD_USD) 205 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 206 #define SD9177 207 #define SDMMCHOST_OPERATION_VOLTAGE_3V3 208 #define SD_TIMING_MAX kSD_TimingDDR50Mode 209 #define WIFI_BT_USE_USD_INTERFACE 210 #define WLAN_ED_MAC_CTRL \ 211 { \ 212 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ 213 } 214 215 /* 2EL Firecrest module with uSD adapter */ 216 #elif defined(WIFI_IW612_BOARD_MURATA_2EL_USD) 217 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h" 218 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h" 219 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h" 220 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h" 221 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" 222 #define SD9177 223 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 224 #define SD_TIMING_MAX kSD_TimingDDR50Mode 225 #define WIFI_BT_USE_USD_INTERFACE 226 #define WLAN_ED_MAC_CTRL \ 227 { \ 228 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ 229 } 230 231 /* 2EL Firecrest module with M2 interface */ 232 #elif defined(WIFI_IW612_BOARD_MURATA_2EL_M2) 233 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_CA_RU_Tx_power.h" 234 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_EU_RU_Tx_power.h" 235 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_JP_RU_Tx_power.h" 236 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_US_RU_Tx_power.h" 237 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" 238 #define SD9177 239 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 240 #define SD_TIMING_MAX kSD_TimingDDR50Mode 241 #define WIFI_BT_USE_M2_INTERFACE 242 #define WLAN_ED_MAC_CTRL \ 243 { \ 244 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ 245 } 246 247 /* u-blox EVK-LILY-W131/-W132 */ 248 #elif defined(WIFI_88W8801_BOARD_UBX_LILY_W1_USD) 249 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 250 #define SD8801 251 #define SDMMCHOST_OPERATION_VOLTAGE_3V3 252 #define WIFI_BT_USE_USD_INTERFACE 253 #define WLAN_ED_MAC_CTRL \ 254 { \ 255 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x1B \ 256 } 257 258 /* u-blox EVK-JODY-W263 */ 259 #elif defined(WIFI_88W8987_BOARD_UBX_JODY_W2_USD) 260 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 261 #define SD8987 262 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 263 #define WIFI_BT_USE_USD_INTERFACE 264 #define WLAN_ED_MAC_CTRL \ 265 { \ 266 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ 267 } 268 /* Murata 2DL + Murata uSD-M.2 adapter */ 269 #elif defined(WIFI_IW611_BOARD_MURATA_2DL_USD) 270 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" 271 #define SD9177 272 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 273 #define SD_TIMING_MAX kSD_TimingDDR50Mode 274 #define WIFI_BT_USE_USD_INTERFACE 275 #define WLAN_ED_MAC_CTRL \ 276 { \ 277 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ 278 } 279 280 /* Murata 2DL */ 281 #elif defined(WIFI_IW611_BOARD_MURATA_2DL_M2) 282 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2EL_WW.h" 283 #define SD9177 284 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 285 #define SD_TIMING_MAX kSD_TimingDDR50Mode 286 #define WIFI_BT_USE_M2_INTERFACE 287 #define WLAN_ED_MAC_CTRL \ 288 { \ 289 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ 290 } 291 292 /* u-blox JODY W5 uSD */ 293 #elif defined(WIFI_AW611_BOARD_UBX_JODY_W5_USD) 294 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_jody_w5_WW.h" 295 #define SD9177 296 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 297 #define SD_TIMING_MAX kSD_TimingDDR50Mode 298 #define WIFI_BT_USE_USD_INTERFACE 299 #define WLAN_ED_MAC_CTRL \ 300 { \ 301 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ 302 } 303 304 /* u-blox JODY W5 M2 */ 305 #elif defined(WIFI_AW611_BOARD_UBX_JODY_W5_M2) 306 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_jody_w5_WW.h" 307 #define SD9177 308 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 309 #define SD_TIMING_MAX kSD_TimingDDR50Mode 310 #define WIFI_BT_USE_M2_INTERFACE 311 #define WLAN_ED_MAC_CTRL \ 312 { \ 313 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0xA, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xA \ 314 } 315 316 /* u-blox EVK-MAYA-W161/-W166 */ 317 #elif defined(WIFI_IW416_BOARD_UBX_MAYA_W1_USD) 318 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h" 319 #define SD8978 320 #define SDMMCHOST_OPERATION_VOLTAGE_1V8 321 #define WIFI_BT_USE_USD_INTERFACE 322 #define WLAN_ED_MAC_CTRL \ 323 { \ 324 .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \ 325 } 326 327 /* Redfinch */ 328 #elif defined(WIFI_BOARD_RW610) 329 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW_rw610.h" 330 #define RW610 331 332 /* K32W061 transceiver */ 333 #elif defined(K32W061_TRANSCEIVER) 334 /* 335 * Wifi functions are not used with K32W061 but wifi files require to 336 * be built, so stub macro are defined. Wifi functions won't be used at 337 * link stage for k32w061 transceiver 338 * 339 */ 340 #define SD8987 341 342 #else 343 #error "Please define macro related to wifi board" 344 #endif 345 346 #endif /* _WIFI_BT_MODULE_CONFIG_H_ */ 347
