1 /*
2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdlib.h>
8 #include <string.h>
9 #include "sdkconfig.h"
10 #include "esp_attr.h"
11 #include "esp_err.h"
12 #include "esp_types.h"
13 #include "esp_log.h"
14 #include "soc/spi_mem_reg.h"
15 #include "soc/io_mux_reg.h"
16 #include "esp_private/spi_flash_os.h"
17 #include "soc/soc.h"
18 #if CONFIG_IDF_TARGET_ESP32S3
19 #include "esp32s3/spi_timing_config.h"
20 #include "esp32s3/rom/cache.h"
21 #endif
22
23 #ifndef __ZEPHYR__
24 #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(*(arr)))
25 #endif
26
27 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
28 const static char *TAG = "MSPI Timing";
29 static spi_timing_tuning_param_t s_flash_best_timing_tuning_config;
30 static spi_timing_tuning_param_t s_psram_best_timing_tuning_config;
31 #endif
32
33 /*------------------------------------------------------------------------------
34 * Common settings
35 *----------------------------------------------------------------------------*/
spi_timing_set_pin_drive_strength(void)36 void spi_timing_set_pin_drive_strength(void)
37 {
38 //For now, set them all to 3. Need to check after QVL test results are out. TODO: IDF-3663
39 //Set default clk
40 SET_PERI_REG_MASK(SPI_MEM_DATE_REG(0), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
41 REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3);
42 REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, 3);
43 //Set default mspi d0 ~ d7, dqs pin drive strength
44 uint32_t regs[] = {IO_MUX_GPIO27_REG, IO_MUX_GPIO28_REG,
45 IO_MUX_GPIO31_REG, IO_MUX_GPIO32_REG,
46 IO_MUX_GPIO33_REG, IO_MUX_GPIO34_REG,
47 IO_MUX_GPIO35_REG, IO_MUX_GPIO36_REG,
48 IO_MUX_GPIO37_REG};
49 for (int i = 0; i < ARRAY_SIZE(regs); i++) {
50 PIN_SET_DRV(regs[i], 3);
51 }
52 }
53
54 /*------------------------------------------------------------------------------
55 * Static functions to get clock configs
56 *----------------------------------------------------------------------------*/
get_mspi_core_clock(void)57 static spi_timing_config_core_clock_t get_mspi_core_clock(void)
58 {
59 return spi_timing_config_get_core_clock();
60 }
61
get_flash_clock_divider(void)62 static uint32_t get_flash_clock_divider(void)
63 {
64 #if CONFIG_ESPTOOLPY_FLASHFREQ_20M
65 return SPI_TIMING_CORE_CLOCK_MHZ / 20;
66 #elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
67 return SPI_TIMING_CORE_CLOCK_MHZ / 40;
68 #elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
69 return SPI_TIMING_CORE_CLOCK_MHZ / 80;
70 #elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
71 return SPI_TIMING_CORE_CLOCK_MHZ / 120;
72 #else
73 abort();
74 #endif
75 }
76
get_psram_clock_divider(void)77 static uint32_t get_psram_clock_divider(void)
78 {
79 #if CONFIG_SPIRAM_SPEED_40M
80 return SPI_TIMING_CORE_CLOCK_MHZ / 40;
81 #elif CONFIG_SPIRAM_SPEED_80M
82 return SPI_TIMING_CORE_CLOCK_MHZ / 80;
83 #elif CONFIG_SPIRAM_SPEED_120M
84 return SPI_TIMING_CORE_CLOCK_MHZ / 120;
85 #else
86 //Will enter this branch only if PSRAM is not enable
87 return 0;
88 #endif
89 }
90
91 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
92 /*------------------------------------------------------------------------------
93 * Static functions to do timing tuning
94 *----------------------------------------------------------------------------*/
95 /**
96 * Set timing tuning regs, in order to get successful sample points
97 */
init_spi1_for_tuning(bool is_flash)98 static void init_spi1_for_tuning(bool is_flash)
99 {
100 //Get required core clock and module clock settings
101 spi_timing_config_core_clock_t core_clock = get_mspi_core_clock();
102 //Set SPI1 core clock. SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
103 spi_timing_config_set_core_clock(0, core_clock);
104 //Set SPI1 module clock as required
105 if (is_flash) {
106 uint32_t flash_div = get_flash_clock_divider();
107 spi_timing_config_set_flash_clock(1, flash_div);
108 //Power on HCLK
109 REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(0), SPI_MEM_TIMING_CLK_ENA);
110 } else {
111 //We use SPI1 Flash to tune PSRAM, PSRAM timing related regs do nothing on SPI1
112 uint32_t psram_div = get_psram_clock_divider();
113 spi_timing_config_set_flash_clock(1, psram_div);
114 //Power on HCLK
115 REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(0), SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
116 }
117 }
118
119 /**
120 * We use different SPI1 timing tuning config to read data to see if current MSPI sampling is successful.
121 * The sampling result will be stored in an array. In this array, successful item will be 1, failed item will be 0.
122 */
sweep_for_success_sample_points(uint8_t * reference_data,const spi_timing_config_t * config,bool is_flash,uint8_t * out_array)123 static void sweep_for_success_sample_points(uint8_t *reference_data, const spi_timing_config_t *config, bool is_flash, uint8_t *out_array)
124 {
125 uint32_t config_idx = 0;
126 uint8_t read_data[SPI_TIMING_TEST_DATA_LEN] = {0};
127
128 for (config_idx = 0; config_idx < config->available_config_num; config_idx++) {
129 memset(read_data, 0, SPI_TIMING_TEST_DATA_LEN);
130 #if SPI_TIMING_FLASH_NEEDS_TUNING
131 if (is_flash) {
132 spi_timing_config_flash_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num);
133 spi_timing_config_flash_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len);
134 spi_timing_config_flash_read_data(1, read_data, SPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(read_data));
135 }
136 #endif
137 #if SPI_TIMING_PSRAM_NEEDS_TUNING
138 if (!is_flash) {
139 spi_timing_config_psram_tune_din_num_mode(config->tuning_config_table[config_idx].spi_din_mode, config->tuning_config_table[config_idx].spi_din_num);
140 spi_timing_config_psram_tune_dummy(config->tuning_config_table[config_idx].extra_dummy_len);
141 spi_timing_config_psram_read_data(1, read_data, SPI_TIMING_PSRAM_TEST_DATA_ADDR, SPI_TIMING_TEST_DATA_LEN);
142 }
143 #endif
144 if (memcmp(reference_data, read_data, sizeof(read_data)) == 0) {
145 out_array[config_idx] = 1;
146 }
147 }
148 }
149
150 /**
151 * Find consecutive successful sampling points.
152 * e.g. array: {1, 1, 0, 0, 1, 1, 1, 0}
153 * out_length: 3
154 * outout_end_index: 6
155 */
find_max_consecutive_success_points(uint8_t * array,uint32_t size,uint32_t * out_length,uint32_t * out_end_index)156 static void find_max_consecutive_success_points(uint8_t *array, uint32_t size, uint32_t *out_length, uint32_t *out_end_index)
157 {
158 uint32_t max = 0;
159 uint32_t match_num = 0;
160 uint32_t i = 0;
161 uint32_t end = 0;
162
163 while (i < size) {
164 if (array[i]) {
165 match_num++;
166 } else {
167 if (match_num > max) {
168 max = match_num;
169 end = i - 1;
170 }
171 match_num = 0;
172 }
173 i++;
174 }
175
176 *out_length = match_num > max ? match_num : max;
177 *out_end_index = match_num == size ? size : end;
178 }
179
180 #if SPI_TIMING_FLASH_DTR_MODE || SPI_TIMING_PSRAM_DTR_MODE
select_best_tuning_config_dtr(spi_timing_config_t * config,uint32_t consecutive_length,uint32_t end)181 static uint32_t select_best_tuning_config_dtr(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end)
182 {
183 #if (SPI_TIMING_CORE_CLOCK_MHZ == 160)
184 //Core clock 160M DTR best point scheme
185 uint32_t best_point;
186
187 //Define these magic number in macros in `spi_timing_config.h`. TODO: IDF-3663
188 if (consecutive_length <= 2 || consecutive_length >= 6) {
189 //tuning is FAIL, select default point, and generate a warning
190 best_point = config->default_config_id;
191 ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point);
192 } else if (consecutive_length <= 4) {
193 //consecutive length : 3 or 4
194 best_point = end - 1;
195 ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
196 } else {
197 //consecutive point list length equals 5
198 best_point = end - 2;
199 ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
200 }
201
202 return best_point;
203 #else
204 //won't reach here
205 abort();
206 #endif
207 }
208 #endif
209
210 #if SPI_TIMING_FLASH_STR_MODE || SPI_TIMING_PSRAM_STR_MODE
select_best_tuning_config_str(spi_timing_config_t * config,uint32_t consecutive_length,uint32_t end)211 static uint32_t select_best_tuning_config_str(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end)
212 {
213 #if (SPI_TIMING_CORE_CLOCK_MHZ == 120 || SPI_TIMING_CORE_CLOCK_MHZ == 240)
214 //STR best point scheme
215 uint32_t best_point;
216
217 if (consecutive_length <= 2|| consecutive_length >= 5) {
218 //tuning is FAIL, select default point, and generate a warning
219 best_point = config->default_config_id;
220 ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point);
221 } else {
222 //consecutive length : 3 or 4
223 best_point = end - consecutive_length / 2;
224 ESP_EARLY_LOGD(TAG,"tuning success, best point is index %d", best_point);
225 }
226
227 return best_point;
228 #else
229 //won't reach here
230 abort();
231 #endif
232 }
233 #endif
234
select_best_tuning_config(spi_timing_config_t * config,uint32_t consecutive_length,uint32_t end,bool is_flash)235 static void select_best_tuning_config(spi_timing_config_t *config, uint32_t consecutive_length, uint32_t end, bool is_flash)
236 {
237 uint32_t best_point = 0;
238 if (is_flash) {
239 #if SPI_TIMING_FLASH_DTR_MODE
240 best_point = select_best_tuning_config_dtr(config, consecutive_length, end);
241 #elif SPI_TIMING_FLASH_STR_MODE
242 best_point = select_best_tuning_config_str(config, consecutive_length, end);
243 #endif
244 s_flash_best_timing_tuning_config = config->tuning_config_table[best_point];
245 } else {
246 #if SPI_TIMING_PSRAM_DTR_MODE
247 best_point = select_best_tuning_config_dtr(config, consecutive_length, end);
248 #elif SPI_TIMING_PSRAM_STR_MODE
249 best_point = select_best_tuning_config_str(config, consecutive_length, end);
250 #endif
251 s_psram_best_timing_tuning_config = config->tuning_config_table[best_point];
252 }
253 }
254
do_tuning(uint8_t * reference_data,spi_timing_config_t * timing_config,bool is_flash)255 static void do_tuning(uint8_t *reference_data, spi_timing_config_t *timing_config, bool is_flash)
256 {
257 /**
258 * We use SPI1 to tune the timing:
259 * 1. Get all SPI1 sampling results.
260 * 2. Find the longest consecutive successful sampling points from the result above.
261 * 3. The middle one will be the best sampling point.
262 */
263 uint32_t consecutive_length = 0;
264 uint32_t last_success_point = 0;
265 uint8_t sample_result[SPI_TIMING_CONFIG_NUM_DEFAULT] = {0};
266
267 init_spi1_for_tuning(is_flash);
268 sweep_for_success_sample_points(reference_data, timing_config, is_flash, sample_result);
269 find_max_consecutive_success_points(sample_result, SPI_TIMING_CONFIG_NUM_DEFAULT, &consecutive_length, &last_success_point);
270 select_best_tuning_config(timing_config, consecutive_length, last_success_point, is_flash);
271 }
272 #endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
273
274
275 /*------------------------------------------------------------------------------
276 * FLASH Timing Tuning
277 *----------------------------------------------------------------------------*/
278 #if SPI_TIMING_FLASH_NEEDS_TUNING
get_flash_tuning_configs(spi_timing_config_t * config)279 static void get_flash_tuning_configs(spi_timing_config_t *config)
280 {
281 #if SPI_TIMING_FLASH_DTR_MODE
282 #define FLASH_MODE DTR_MODE
283 #else //SPI_TIMING_FLASH_STR_MODE
284 #define FLASH_MODE STR_MODE
285 #endif
286
287 #if CONFIG_ESPTOOLPY_FLASHFREQ_20M
288 *config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 20, FLASH_MODE);
289 #elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
290 *config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 40, FLASH_MODE);
291 #elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
292 *config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 80, FLASH_MODE);
293 #elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
294 *config = SPI_TIMING_FLASH_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 120, FLASH_MODE);
295 #endif
296
297 #undef FLASH_MODE
298 }
299
spi_timing_flash_tuning(void)300 void spi_timing_flash_tuning(void)
301 {
302 ESP_EARLY_LOGW("FLASH", "DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version.");
303 /**
304 * set SPI01 related regs to 20mhz configuration, to get reference data from FLASH
305 * see detailed comments in this function (`spi_timing_enter_mspi_low_speed_mode`)
306 */
307 spi_timing_enter_mspi_low_speed_mode(true);
308
309 //Disable the variable dummy mode when doing timing tuning
310 CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY); //GD flash will read error in variable mode with 20MHz
311
312 uint8_t reference_data[SPI_TIMING_TEST_DATA_LEN] = {0};
313 spi_timing_config_flash_read_data(1, reference_data, SPI_TIMING_FLASH_TEST_DATA_ADDR, sizeof(reference_data));
314 spi_timing_config_t timing_configs = {0};
315 get_flash_tuning_configs(&timing_configs);
316
317 do_tuning(reference_data, &timing_configs, true);
318 spi_timing_enter_mspi_high_speed_mode(true);
319 }
320 #else
spi_timing_flash_tuning(void)321 void spi_timing_flash_tuning(void)
322 {
323 //Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned
324 }
325 #endif //SPI_TIMING_FLASH_NEEDS_TUNING
326
327
328 /*------------------------------------------------------------------------------
329 * PSRAM Timing Tuning
330 *----------------------------------------------------------------------------*/
331 #if SPI_TIMING_PSRAM_NEEDS_TUNING
get_psram_tuning_configs(spi_timing_config_t * config)332 static void get_psram_tuning_configs(spi_timing_config_t *config)
333 {
334 #if SPI_TIMING_PSRAM_DTR_MODE
335 #define PSRAM_MODE DTR_MODE
336 #else //SPI_TIMING_PSRAM_STR_MODE
337 #define PSRAM_MODE STR_MODE
338 #endif
339
340 #if CONFIG_SPIRAM_SPEED_40M
341 *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 40, PSRAM_MODE);
342 #elif CONFIG_SPIRAM_SPEED_80M
343 *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 80, PSRAM_MODE);
344 #elif CONFIG_SPIRAM_SPEED_120M
345 *config = SPI_TIMING_PSRAM_GET_TUNING_CONFIG(SPI_TIMING_CORE_CLOCK_MHZ, 120, PSRAM_MODE);
346 #endif
347
348 #undef PSRAM_MODE
349 }
350
spi_timing_psram_tuning(void)351 void spi_timing_psram_tuning(void)
352 {
353 ESP_EARLY_LOGW("PSRAM", "DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version.");
354 /**
355 * set SPI01 related regs to 20mhz configuration, to write reference data to PSRAM
356 * see detailed comments in this function (`spi_timing_enter_mspi_low_speed_mode`)
357 */
358 spi_timing_enter_mspi_low_speed_mode(true);
359
360 // write data into psram, used to do timing tuning test.
361 uint8_t reference_data[SPI_TIMING_TEST_DATA_LEN];
362 for (int i=0; i < SPI_TIMING_TEST_DATA_LEN/4; i++) {
363 ((uint32_t *)reference_data)[i] = 0xa5ff005a;
364 }
365 spi_timing_config_psram_write_data(1, reference_data, SPI_TIMING_PSRAM_TEST_DATA_ADDR, SPI_TIMING_TEST_DATA_LEN);
366 spi_timing_config_t timing_configs = {0};
367 get_psram_tuning_configs(&timing_configs);
368
369 //Disable the variable dummy mode when doing timing tuning
370 CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
371 //Get required config, and set them to PSRAM related registers
372 do_tuning(reference_data, &timing_configs, false);
373 spi_timing_enter_mspi_high_speed_mode(true);
374 }
375
376 #else
spi_timing_psram_tuning(void)377 void spi_timing_psram_tuning(void)
378 {
379 //Empty function for compatibility, therefore upper layer won't need to know that FLASH in which operation mode and frequency config needs to be tuned
380 }
381 #endif //SPI_TIMING_PSRAM_NEEDS_TUNING
382
383
384 /*------------------------------------------------------------------------------
385 * APIs to make SPI0 (and SPI1) FLASH work for high/low freq
386 *----------------------------------------------------------------------------*/
387 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
clear_timing_tuning_regs(bool control_spi1)388 static void clear_timing_tuning_regs(bool control_spi1)
389 {
390 spi_timing_config_flash_set_din_mode_num(0, 0, 0); //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
391 spi_timing_config_flash_set_extra_dummy(0, 0);
392 if (control_spi1) {
393 spi_timing_config_flash_set_extra_dummy(1, 0);
394 } else {
395 //Won't touch SPI1 registers
396 }
397 }
398 #endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
399
spi_timing_enter_mspi_low_speed_mode(bool control_spi1)400 void spi_timing_enter_mspi_low_speed_mode(bool control_spi1)
401 {
402 /**
403 * Here we are going to slow the SPI1 frequency to 20Mhz, so we need to set SPI1 din_num and din_mode regs.
404 *
405 * Because SPI0 and SPI1 share the din_num and din_mode regs, so if we clear SPI1 din_num and din_mode to
406 * 0, if the SPI0 flash module clock is still in high freq, it may not work correctly.
407 *
408 * Therefore, here we need to slow both the SPI0 and SPI1 and related timing tuning regs to 20Mhz configuration.
409 */
410
411 //Switch SPI1 and SPI0 clock as 20MHz, set its SPIMEM core clock as 80M and set clock division as 4
412 spi_timing_config_set_core_clock(0, SPI_TIMING_CONFIG_CORE_CLOCK_80M); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
413 spi_timing_config_set_flash_clock(0, 4);
414 if (control_spi1) {
415 //After tuning, won't touch SPI1 again
416 spi_timing_config_set_flash_clock(1, 4);
417 }
418
419 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
420 clear_timing_tuning_regs(control_spi1);
421 #endif
422 }
423
424 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
set_timing_tuning_regs_as_required(bool control_spi1)425 static void set_timing_tuning_regs_as_required(bool control_spi1)
426 {
427 //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
428 spi_timing_config_flash_set_din_mode_num(0, s_flash_best_timing_tuning_config.spi_din_mode, s_flash_best_timing_tuning_config.spi_din_num);
429 spi_timing_config_flash_set_extra_dummy(0, s_flash_best_timing_tuning_config.extra_dummy_len);
430 if (control_spi1) {
431 spi_timing_config_flash_set_extra_dummy(1, s_flash_best_timing_tuning_config.extra_dummy_len);
432 }
433
434 spi_timing_config_psram_set_din_mode_num(0, s_psram_best_timing_tuning_config.spi_din_mode, s_psram_best_timing_tuning_config.spi_din_num);
435 spi_timing_config_psram_set_extra_dummy(0, s_psram_best_timing_tuning_config.extra_dummy_len);
436 }
437 #endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
438
439 /**
440 * Set SPI0 FLASH and PSRAM module clock, din_num, din_mode and extra dummy,
441 * according to the configuration got from timing tuning function (`calculate_best_flash_tuning_config`).
442 * iF control_spi1 == 1, will also update SPI1 timing registers. Should only be set to 1 when do tuning.
443 *
444 * This function should always be called after `spi_timing_flash_tuning` or `calculate_best_flash_tuning_config`
445 */
spi_timing_enter_mspi_high_speed_mode(bool control_spi1)446 void spi_timing_enter_mspi_high_speed_mode(bool control_spi1)
447 {
448 spi_timing_config_core_clock_t core_clock = get_mspi_core_clock();
449 uint32_t flash_div = get_flash_clock_divider();
450 uint32_t psram_div = get_psram_clock_divider();
451
452 //Set SPI01 core clock
453 spi_timing_config_set_core_clock(0, core_clock); //SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
454 //Set FLASH module clock
455 spi_timing_config_set_flash_clock(0, flash_div);
456 if (control_spi1) {
457 spi_timing_config_set_flash_clock(1, flash_div);
458 }
459 //Set PSRAM module clock
460 spi_timing_config_set_psram_clock(0, psram_div);
461
462 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
463 set_timing_tuning_regs_as_required(true);
464 #endif
465 }
466
spi_timing_change_speed_mode_cache_safe(bool switch_down)467 void spi_timing_change_speed_mode_cache_safe(bool switch_down)
468 {
469 Cache_Freeze_ICache_Enable(1);
470 Cache_Freeze_DCache_Enable(1);
471 if (switch_down) {
472 //enter MSPI low speed mode, extra delays should be removed
473 spi_timing_enter_mspi_low_speed_mode(false);
474 } else {
475 //enter MSPI high speed mode, extra delays should be considered
476 spi_timing_enter_mspi_high_speed_mode(false);
477 }
478 Cache_Freeze_DCache_Disable();
479 Cache_Freeze_ICache_Disable();
480 }
481
482 /*------------------------------------------------------------------------------
483 * APIs to inform SPI1 Flash driver of necessary timing configurations
484 *----------------------------------------------------------------------------*/
spi_timing_is_tuned(void)485 bool spi_timing_is_tuned(void)
486 {
487 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
488 return true;
489 #else
490 return false;
491 #endif
492 }
493
494 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t * out_timing_config)495 void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config)
496 {
497 // Get clock configuration directly from system.
498 out_timing_config->clock_config.spimem.val = spi_timing_config_get_flash_clock_reg();
499
500 // Get extra dummy length here. Therefore, no matter what freq, or mode.
501 // If it needs tuning, it will return correct extra dummy len. If no tuning, it will return 0.
502
503 out_timing_config->extra_dummy = s_flash_best_timing_tuning_config.extra_dummy_len;
504
505 // Get CS setup/hold value here.
506 spi_timing_config_get_cs_timing(&out_timing_config->cs_setup, &out_timing_config->cs_hold);
507 }
508 #else
spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t * out_timing_config)509 void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config)
510 {
511 // This function shouldn't be called if timing tuning is not used.
512 abort();
513 }
514 #endif // SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
515
