1 /*
2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdlib.h>
8 #include <sys/param.h>
9 #include "sdkconfig.h"
10 #include "string.h"
11 #include "esp_attr.h"
12 #include "esp_err.h"
13 #include "esp_types.h"
14 #include "esp_log.h"
15 #include "soc/spi_mem_reg.h"
16 #include "spi_timing_config.h"
17
18 #define OPI_PSRAM_SYNC_READ 0x0000
19 #define OPI_PSRAM_SYNC_WRITE 0x8080
20 #define OCT_PSRAM_RD_DUMMY_NUM (2*(10-1))
21 #define OCT_PSRAM_WR_DUMMY_NUM (2*(5-1))
22
23 #define QPI_PSRAM_FAST_READ 0XEB
24 #define QPI_PSRAM_WRITE 0X38
25 #define QPI_PSRAM_FAST_READ_DUMMY 6
26
27 #define MULTI_LINE_MASK_OCT_FLASH (SPI_MEM_FCMD_OCT | SPI_MEM_FADDR_OCT | SPI_MEM_FDIN_OCT | SPI_MEM_FDOUT_OCT)
28 #define MULTI_LINE_MASK_QUAD_FLASH (SPI_MEM_FASTRD_MODE | SPI_MEM_FREAD_DUAL | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_QIO)
29 #define SPI_FLASH_QIO_MODE (SPI_MEM_FREAD_QIO | SPI_MEM_FASTRD_MODE)
30 #define SPI_FLASH_QUAD_MODE (SPI_MEM_FREAD_QUAD | SPI_MEM_FASTRD_MODE)
31 #define SPI_FLASH_DIO_MODE (SPI_MEM_FREAD_DIO | SPI_MEM_FASTRD_MODE)
32 #define SPI_FLASH_DUAL_MODE (SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE)
33 #define SPI_FLASH_FAST_MODE (SPI_MEM_FASTRD_MODE)
34 #define SPI_FLASH_SLOW_MODE 0
35
36 #define NOT_INIT_INT 127
37
38 //-------------------------------------MSPI Clock Setting-------------------------------------//
spi_timing_config_get_core_clock(void)39 spi_timing_config_core_clock_t spi_timing_config_get_core_clock(void)
40 {
41 switch (SPI_TIMING_CORE_CLOCK_MHZ) {
42 case 80:
43 return SPI_TIMING_CONFIG_CORE_CLOCK_80M;
44 case 120:
45 return SPI_TIMING_CONFIG_CORE_CLOCK_120M;
46 case 160:
47 return SPI_TIMING_CONFIG_CORE_CLOCK_160M;
48 case 240:
49 return SPI_TIMING_CONFIG_CORE_CLOCK_240M;
50 default:
51 abort();
52 }
53 }
54
spi_timing_config_set_core_clock(uint8_t spi_num,spi_timing_config_core_clock_t core_clock)55 void spi_timing_config_set_core_clock(uint8_t spi_num, spi_timing_config_core_clock_t core_clock)
56 {
57 uint32_t reg_val = 0;
58
59 switch (core_clock) {
60 case SPI_TIMING_CONFIG_CORE_CLOCK_80M:
61 reg_val = 0;
62 break;
63 case SPI_TIMING_CONFIG_CORE_CLOCK_120M:
64 reg_val = 1;
65 break;
66 case SPI_TIMING_CONFIG_CORE_CLOCK_160M:
67 reg_val = 2;
68 break;
69 case SPI_TIMING_CONFIG_CORE_CLOCK_240M:
70 reg_val = 3;
71 break;
72 default:
73 abort();
74 }
75
76 REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, reg_val);
77 }
78
spi_timing_config_set_flash_clock(uint8_t spi_num,uint32_t freqdiv)79 void spi_timing_config_set_flash_clock(uint8_t spi_num, uint32_t freqdiv)
80 {
81 assert(freqdiv > 0);
82 if (freqdiv == 1) {
83 WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), SPI_MEM_CLK_EQU_SYSCLK);
84 } else {
85 uint32_t freqbits = (((freqdiv - 1) << SPI_MEM_CLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_CLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_CLKCNT_L_S);
86 WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), freqbits);
87 }
88 }
89
spi_timing_config_set_psram_clock(uint8_t spi_num,uint32_t freqdiv)90 void spi_timing_config_set_psram_clock(uint8_t spi_num, uint32_t freqdiv)
91 {
92 if (freqdiv == 1) {
93 WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
94 } else {
95 uint32_t freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
96 WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
97 }
98 }
99
100 /////////////////////////////////////////TIMING TUNING IS NEEDED//////////////////////////////////////////////
101 //////////////////////////////////////////////////////////////////////////////////////////////////////////////
102 #if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
103 //If one of the FLASH / PSRAM or both of them need timing tuning, we should build following code
104 typedef enum {
105 PSRAM_CMD_QPI,
106 PSRAM_CMD_SPI,
107 } psram_cmd_mode_t;
108
109 #if !CONFIG_ESPTOOLPY_OCT_FLASH
110 static uint8_t s_rom_flash_extra_dummy[2] = {NOT_INIT_INT, NOT_INIT_INT};
111 #endif
112
113 #if CONFIG_SPIRAM_MODE_QUAD
114 static uint8_t s_psram_extra_dummy;
115 extern void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
116 uint32_t cmd, int cmd_bit_len,
117 uint32_t addr, int addr_bit_len,
118 int dummy_bits,
119 uint8_t* mosi_data, int mosi_bit_len,
120 uint8_t* miso_data, int miso_bit_len,
121 uint32_t cs_mask,
122 bool is_write_erase_operation);
123 #endif
124
125 //-------------------------------------FLASH timing tuning register config-------------------------------------//
spi_timing_config_flash_set_din_mode_num(uint8_t spi_num,uint8_t din_mode,uint8_t din_num)126 void spi_timing_config_flash_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
127 {
128 uint32_t reg_val = 0;
129 reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
130 | (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
131 | (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
132 REG_WRITE(SPI_MEM_DIN_MODE_REG(spi_num), reg_val);
133
134 reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
135 | (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
136 | (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
137 REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val);
138 }
139
spi_timing_config_flash_set_extra_dummy(uint8_t spi_num,uint8_t extra_dummy)140 void spi_timing_config_flash_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
141 {
142 #if CONFIG_ESPTOOLPY_OCT_FLASH
143 if (extra_dummy > 0) {
144 SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
145 SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
146 SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
147 } else {
148 CLEAR_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
149 SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0,
150 SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
151 }
152 #else
153 /**
154 * The `SPI_MEM_TIMING_CALI_REG` register is only used for OPI on 728
155 * Here we only need to update this global variable for extra dummy. Since we use the ROM Flash API, which will set the dummy based on this.
156 * We only initialise the SPI0. And leave the SPI1 for flash driver to configure.
157 */
158 if (s_rom_flash_extra_dummy[spi_num] == NOT_INIT_INT) {
159 s_rom_flash_extra_dummy[spi_num] = g_rom_spiflash_dummy_len_plus[spi_num];
160 }
161 g_rom_spiflash_dummy_len_plus[spi_num] = s_rom_flash_extra_dummy[spi_num] + extra_dummy;
162
163 uint32_t dummy;
164 uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
165 if (ctrl_reg & MULTI_LINE_MASK_OCT_FLASH) {
166 abort();
167 }
168 switch (ctrl_reg & MULTI_LINE_MASK_QUAD_FLASH) {
169 case SPI_FLASH_QIO_MODE:
170 dummy = SPI1_R_QIO_DUMMY_CYCLELEN;
171 break;
172 case SPI_FLASH_QUAD_MODE:
173 dummy = SPI1_R_FAST_DUMMY_CYCLELEN;
174 break;
175 case SPI_FLASH_DIO_MODE:
176 dummy = SPI1_R_DIO_DUMMY_CYCLELEN;
177 break;
178 case SPI_FLASH_DUAL_MODE:
179 dummy = SPI1_R_FAST_DUMMY_CYCLELEN;
180 break;
181 case SPI_FLASH_FAST_MODE:
182 dummy = SPI1_R_FAST_DUMMY_CYCLELEN;
183 break;
184 case SPI_FLASH_SLOW_MODE:
185 dummy = 0;
186 break;
187 default:
188 abort();
189 }
190 SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, dummy + g_rom_spiflash_dummy_len_plus[spi_num], SPI_MEM_USR_DUMMY_CYCLELEN_S);
191 #endif
192 }
193
194 //-------------------------------------PSRAM timing tuning register config-------------------------------------//
spi_timing_config_psram_set_din_mode_num(uint8_t spi_num,uint8_t din_mode,uint8_t din_num)195 void spi_timing_config_psram_set_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
196 {
197 uint32_t reg_val = 0;
198 reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_MODE_M | SPI_MEM_SPI_SMEM_DIN1_MODE_M | SPI_MEM_SPI_SMEM_DIN2_MODE_M | SPI_MEM_SPI_SMEM_DIN3_MODE_M | SPI_MEM_SPI_SMEM_DIN4_MODE_M | SPI_MEM_SPI_SMEM_DIN5_MODE_M | SPI_MEM_SPI_SMEM_DIN6_MODE_M | SPI_MEM_SPI_SMEM_DIN7_MODE_M | SPI_MEM_SPI_SMEM_DINS_MODE_M)))
199 | (din_mode << SPI_MEM_SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN3_MODE_S)
200 | (din_mode << SPI_MEM_SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DINS_MODE_S);
201 REG_WRITE(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num), reg_val);
202
203 reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_NUM_M | SPI_MEM_SPI_SMEM_DIN1_NUM_M | SPI_MEM_SPI_SMEM_DIN2_NUM_M | SPI_MEM_SPI_SMEM_DIN3_NUM_M | SPI_MEM_SPI_SMEM_DIN4_NUM_M | SPI_MEM_SPI_SMEM_DIN5_NUM_M | SPI_MEM_SPI_SMEM_DIN6_NUM_M | SPI_MEM_SPI_SMEM_DIN7_NUM_M | SPI_MEM_SPI_SMEM_DINS_NUM_M)))
204 | (din_num << SPI_MEM_SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN3_NUM_S)
205 | (din_num << SPI_MEM_SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DINS_NUM_S);
206 REG_WRITE(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num), reg_val);
207 }
208
spi_timing_config_psram_set_extra_dummy(uint8_t spi_num,uint8_t extra_dummy)209 void spi_timing_config_psram_set_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
210 {
211 #if CONFIG_SPIRAM_MODE_OCT
212 if (extra_dummy > 0) {
213 SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
214 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
215 SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
216 } else {
217 CLEAR_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
218 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
219 SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
220 }
221 #elif CONFIG_SPIRAM_MODE_QUAD
222 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_USR_RD_SRAM_DUMMY_M);
223 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(spi_num), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (QPI_PSRAM_FAST_READ_DUMMY + extra_dummy - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S);
224 #endif
225 }
226
227 //-------------------------------------------FLASH/PSRAM Read/Write------------------------------------------//
spi_timing_config_flash_read_data(uint8_t spi_num,uint8_t * buf,uint32_t addr,uint32_t len)228 void spi_timing_config_flash_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
229 {
230 #if CONFIG_ESPTOOLPY_OCT_FLASH
231 // note that in spi_flash_read API, there is a wait-idle stage, since flash can only be read in idle state.
232 // but after we change the timing settings, we might not read correct idle status via RDSR.
233 // so, here we should use a read API that won't check idle status.
234 for (int i = 0; i < 16; i++) {
235 REG_WRITE(SPI_MEM_W0_REG(1) + i*4, 0);
236 }
237 esp_rom_opiflash_read_raw(addr, buf, len);
238 #else
239 esp_rom_spiflash_read(addr, (uint32_t *)buf, len);
240 #endif
241 }
242
s_psram_write_data(uint8_t spi_num,uint8_t * buf,uint32_t addr,uint32_t len)243 static void s_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
244 {
245 #if CONFIG_SPIRAM_MODE_OCT
246 esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
247 OPI_PSRAM_SYNC_WRITE, 16,
248 addr, 32,
249 OCT_PSRAM_WR_DUMMY_NUM,
250 buf, len * 8,
251 NULL, 0,
252 BIT(1),
253 false);
254 #elif CONFIG_SPIRAM_MODE_QUAD
255 psram_exec_cmd(spi_num, 0,
256 QPI_PSRAM_WRITE, 8,
257 addr, 24,
258 0,
259 buf, len * 8,
260 NULL, 0,
261 SPI_MEM_CS1_DIS_M,
262 false);
263 #endif
264 }
265
s_psram_read_data(uint8_t spi_num,uint8_t * buf,uint32_t addr,uint32_t len)266 static void s_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
267 {
268 #if CONFIG_SPIRAM_MODE_OCT
269 for (int i = 0; i < 16; i++) {
270 REG_WRITE(SPI_MEM_W0_REG(1) + i*4, 0);
271 }
272 esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
273 OPI_PSRAM_SYNC_READ, 16,
274 addr, 32,
275 OCT_PSRAM_RD_DUMMY_NUM,
276 NULL, 0,
277 buf, len * 8,
278 BIT(1),
279 false);
280 #elif CONFIG_SPIRAM_MODE_QUAD
281 psram_exec_cmd(spi_num, 0,
282 QPI_PSRAM_FAST_READ, 8,
283 addr, 24,
284 QPI_PSRAM_FAST_READ_DUMMY + s_psram_extra_dummy,
285 NULL, 0,
286 buf, len * 8,
287 SPI_MEM_CS1_DIS_M,
288 false);
289 #endif
290 }
291
s_psram_execution(uint8_t spi_num,uint8_t * buf,uint32_t addr,uint32_t len,bool is_read)292 static void s_psram_execution(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len, bool is_read)
293 {
294 while (len) {
295 uint32_t length = MIN(len, 32);
296 if (is_read) {
297 s_psram_read_data(1, buf, addr, length);
298 } else {
299 s_psram_write_data(1, buf, addr, length);
300 }
301 addr += length;
302 buf += length;
303 len -= length;
304 }
305 }
306
spi_timing_config_psram_write_data(uint8_t spi_num,uint8_t * buf,uint32_t addr,uint32_t len)307 void spi_timing_config_psram_write_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
308 {
309 s_psram_execution(spi_num, buf, addr, len, false);
310 }
311
spi_timing_config_psram_read_data(uint8_t spi_num,uint8_t * buf,uint32_t addr,uint32_t len)312 void spi_timing_config_psram_read_data(uint8_t spi_num, uint8_t *buf, uint32_t addr, uint32_t len)
313 {
314 s_psram_execution(spi_num, buf, addr, len, true);
315 }
316
317
318 /*-------------------------------------------------------------------------------------------------
319 * SPI1 Timing Tuning APIs
320 * These APIs are only used in `spi_flash_timing_tuning.c/sweep_for_success_sample_points()` for
321 * configuring SPI1 timing tuning related registers to find best tuning parameter
322 *-------------------------------------------------------------------------------------------------*/
spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode,uint8_t din_num)323 void spi_timing_config_flash_tune_din_num_mode(uint8_t din_mode, uint8_t din_num)
324 {
325 /**
326 * 1. SPI_MEM_DINx_MODE(1), SPI_MEM_DINx_NUM(1) are meaningless
327 * SPI0 and SPI1 share the SPI_MEM_DINx_MODE(0), SPI_MEM_DINx_NUM(0) for FLASH timing tuning
328 * 2. We use SPI1 to get the best Flash timing tuning (mode and num) config
329 */
330 spi_timing_config_flash_set_din_mode_num(0, din_mode, din_num);
331 }
332
spi_timing_config_flash_tune_dummy(uint8_t extra_dummy)333 void spi_timing_config_flash_tune_dummy(uint8_t extra_dummy)
334 {
335 spi_timing_config_flash_set_extra_dummy(1, extra_dummy);
336 }
337
spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode,uint8_t din_num)338 void spi_timing_config_psram_tune_din_num_mode(uint8_t din_mode, uint8_t din_num)
339 {
340 /**
341 * 1. SPI_MEM_SPI_SMEM_DINx_MODE(1), SPI_MEM_SPI_SMEM_DINx_NUM(1) are meaningless
342 * SPI0 and SPI1 share the SPI_MEM_SPI_SMEM_DINx_MODE(0), SPI_MEM_SPI_SMEM_DINx_NUM(0) for PSRAM timing tuning
343 * 2. We use SPI1 to get the best PSRAM timing tuning (mode and num) config
344 */
345 spi_timing_config_psram_set_din_mode_num(0, din_mode, din_num);
346 }
347
spi_timing_config_psram_tune_dummy(uint8_t extra_dummy)348 void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy)
349 {
350 #if CONFIG_SPIRAM_MODE_OCT
351 //On 728, for SPI1, flash and psram share the extra dummy register
352 spi_timing_config_flash_set_extra_dummy(1, extra_dummy);
353 #elif CONFIG_SPIRAM_MODE_QUAD
354 //Update this `s_psram_extra_dummy`, the `s_psram_read_data` will set dummy according to this `s_psram_extra_dummy`
355 s_psram_extra_dummy = extra_dummy;
356 SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_USR_DUMMY); // dummy en
357 SET_PERI_REG_BITS(SPI_MEM_USER1_REG(1), SPI_MEM_USR_DUMMY_CYCLELEN_V, extra_dummy - 1, SPI_MEM_USR_DUMMY_CYCLELEN_S);
358 #endif
359 }
360
361 #endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
362
363
364 /*-------------------------------------------------------------------------------------------------
365 * To let upper lay (spi_flash_timing_tuning.c) to know the necessary timing registers
366 *-------------------------------------------------------------------------------------------------*/
s_get_cs_setup_enable(void)367 static bool s_get_cs_setup_enable(void)
368 {
369 return REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_SETUP);
370 }
371
s_get_cs_hold_enable(void)372 static bool s_get_cs_hold_enable(void)
373 {
374 return REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD);
375 }
376
377 /**
378 * Get the SPI1 Flash CS timing setting. The setup time and hold time are both realistic cycles.
379 * @note On ESP32-S3, SPI0/1 share the Flash CS timing registers. Therefore, we should not change these values.
380 * @note This function inform `spi_flash_timing_tuning.c` (driver layer) of the cycle,
381 * and other component (esp_flash driver) should get these cycle and configure the registers accordingly.
382 */
spi_timing_config_get_cs_timing(uint8_t * setup_time,uint32_t * hold_time)383 void spi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time)
384 {
385 *setup_time = REG_GET_FIELD(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME);
386 *hold_time = REG_GET_FIELD(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME);
387 /**
388 * The logic here is, if setup_en / hold_en is false, then we return the realistic cycle number,
389 * which is 0. If true, then the realistic cycle number is (reg_value + 1)
390 */
391 if (s_get_cs_setup_enable()) {
392 *setup_time += 1;
393 } else {
394 *setup_time = 0;
395 }
396 if (s_get_cs_hold_enable()) {
397 *hold_time += 1;
398 } else {
399 *hold_time = 0;
400 }
401 }
402
403 /**
404 * Get the SPI1 Flash clock setting.
405 * @note Similarly, this function inform `spi_flash_timing_tuning.c` (driver layer) of the clock setting,
406 * and other component (esp_flash driver) should get these and configure the registers accordingly.
407 */
spi_timing_config_get_flash_clock_reg(void)408 uint32_t spi_timing_config_get_flash_clock_reg(void)
409 {
410 return READ_PERI_REG(SPI_MEM_CLOCK_REG(1));
411 }
412
