1 // Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #include "soc/rtc_io_periph.h" 16 17 const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { 18 RTCIO_GPIO0_CHANNEL, //GPIO0 19 RTCIO_GPIO1_CHANNEL, //GPIO1 20 RTCIO_GPIO2_CHANNEL, //GPIO2 21 RTCIO_GPIO3_CHANNEL, //GPIO3 22 RTCIO_GPIO4_CHANNEL, //GPIO4 23 RTCIO_GPIO5_CHANNEL, //GPIO5 24 RTCIO_GPIO6_CHANNEL, //GPIO6 25 RTCIO_GPIO7_CHANNEL, //GPIO7 26 RTCIO_GPIO8_CHANNEL, //GPIO8 27 RTCIO_GPIO9_CHANNEL, //GPIO9 28 RTCIO_GPIO10_CHANNEL, //GPIO10 29 RTCIO_GPIO11_CHANNEL, //GPIO11 30 RTCIO_GPIO12_CHANNEL, //GPIO12 31 RTCIO_GPIO13_CHANNEL, //GPIO13 32 RTCIO_GPIO14_CHANNEL, //GPIO14 33 RTCIO_GPIO15_CHANNEL, //GPIO15 34 RTCIO_GPIO16_CHANNEL, //GPIO16 35 RTCIO_GPIO17_CHANNEL, //GPIO17 36 RTCIO_GPIO18_CHANNEL, //GPIO18 37 RTCIO_GPIO19_CHANNEL, //GPIO19 38 RTCIO_GPIO20_CHANNEL, //GPIO20 39 RTCIO_GPIO21_CHANNEL, //GPIO21 40 -1,//GPIO22 41 -1,//GPIO23 42 -1,//GPIO24 43 -1,//GPIO25 44 -1,//GPIO26 45 -1,//GPIO27 46 -1,//GPIO28 47 -1,//GPIO29 48 -1,//GPIO30 49 -1,//GPIO31 50 -1,//GPIO32 51 -1,//GPIO33 52 -1,//GPIO34 53 -1,//GPIO35 54 -1,//GPIO36 55 -1,//GPIO37 56 -1,//GPIO38 57 -1,//GPIO39 58 -1,//GPIO40 59 -1,//GPIO41 60 -1,//GPIO42 61 -1,//GPIO43 62 -1,//GPIO44 63 -1,//GPIO45 64 -1,//GPIO46 65 }; 66 67 //Reg,Mux,Fun,IE,Up,Down,Rtc_number 68 const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = { 69 /*REG MUX select function select Input enable Pullup Pulldown Sleep select Sleep input enable Sleep output enable PAD hold Pad force hold Mask of drive capability Offset gpio number */ 70 {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD0_HOLD_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_CHANNEL_0_GPIO_NUM}, //0 71 {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD1_HOLD_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_CHANNEL_1_GPIO_NUM}, //1 72 {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD2_HOLD_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_CHANNEL_2_GPIO_NUM}, //2 73 {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD3_HOLD_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_CHANNEL_3_GPIO_NUM}, //3 74 {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD4_HOLD_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_CHANNEL_4_GPIO_NUM}, //4 75 {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD5_HOLD_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_CHANNEL_5_GPIO_NUM}, //5 76 {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD6_HOLD_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_CHANNEL_6_GPIO_NUM}, //6 77 {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD7_HOLD_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_CHANNEL_7_GPIO_NUM}, //7 78 {RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_MUX_SEL_M, RTC_IO_TOUCH_PAD8_FUN_SEL_S, RTC_IO_TOUCH_PAD8_FUN_IE_M, RTC_IO_TOUCH_PAD8_RUE_M, RTC_IO_TOUCH_PAD8_RDE_M, RTC_IO_TOUCH_PAD8_SLP_SEL_M, RTC_IO_TOUCH_PAD8_SLP_IE_M, RTC_IO_TOUCH_PAD8_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD8_HOLD_M, RTC_IO_TOUCH_PAD8_DRV_V, RTC_IO_TOUCH_PAD8_DRV_S, RTCIO_CHANNEL_8_GPIO_NUM}, //8 79 {RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_MUX_SEL_M, RTC_IO_TOUCH_PAD9_FUN_SEL_S, RTC_IO_TOUCH_PAD9_FUN_IE_M, RTC_IO_TOUCH_PAD9_RUE_M, RTC_IO_TOUCH_PAD9_RDE_M, RTC_IO_TOUCH_PAD9_SLP_SEL_M, RTC_IO_TOUCH_PAD9_SLP_IE_M, RTC_IO_TOUCH_PAD9_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD9_HOLD_M, RTC_IO_TOUCH_PAD9_DRV_V, RTC_IO_TOUCH_PAD9_DRV_S, RTCIO_CHANNEL_9_GPIO_NUM}, //9 80 {RTC_IO_TOUCH_PAD10_REG, RTC_IO_TOUCH_PAD10_MUX_SEL_M, RTC_IO_TOUCH_PAD10_FUN_SEL_S, RTC_IO_TOUCH_PAD10_FUN_IE_M, RTC_IO_TOUCH_PAD10_RUE_M, RTC_IO_TOUCH_PAD10_RDE_M, RTC_IO_TOUCH_PAD10_SLP_SEL_M, RTC_IO_TOUCH_PAD10_SLP_IE_M, RTC_IO_TOUCH_PAD10_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD10_HOLD_M, RTC_IO_TOUCH_PAD10_DRV_V, RTC_IO_TOUCH_PAD10_DRV_S, RTCIO_CHANNEL_10_GPIO_NUM}, //10 81 {RTC_IO_TOUCH_PAD11_REG, RTC_IO_TOUCH_PAD11_MUX_SEL_M, RTC_IO_TOUCH_PAD11_FUN_SEL_S, RTC_IO_TOUCH_PAD11_FUN_IE_M, RTC_IO_TOUCH_PAD11_RUE_M, RTC_IO_TOUCH_PAD11_RDE_M, RTC_IO_TOUCH_PAD11_SLP_SEL_M, RTC_IO_TOUCH_PAD11_SLP_IE_M, RTC_IO_TOUCH_PAD11_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD11_HOLD_M, RTC_IO_TOUCH_PAD11_DRV_V, RTC_IO_TOUCH_PAD11_DRV_S, RTCIO_CHANNEL_11_GPIO_NUM}, //11 82 {RTC_IO_TOUCH_PAD12_REG, RTC_IO_TOUCH_PAD12_MUX_SEL_M, RTC_IO_TOUCH_PAD12_FUN_SEL_S, RTC_IO_TOUCH_PAD12_FUN_IE_M, RTC_IO_TOUCH_PAD12_RUE_M, RTC_IO_TOUCH_PAD12_RDE_M, RTC_IO_TOUCH_PAD12_SLP_SEL_M, RTC_IO_TOUCH_PAD12_SLP_IE_M, RTC_IO_TOUCH_PAD12_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD12_HOLD_M, RTC_IO_TOUCH_PAD12_DRV_V, RTC_IO_TOUCH_PAD12_DRV_S, RTCIO_CHANNEL_12_GPIO_NUM}, //12 83 {RTC_IO_TOUCH_PAD13_REG, RTC_IO_TOUCH_PAD13_MUX_SEL_M, RTC_IO_TOUCH_PAD13_FUN_SEL_S, RTC_IO_TOUCH_PAD13_FUN_IE_M, RTC_IO_TOUCH_PAD13_RUE_M, RTC_IO_TOUCH_PAD13_RDE_M, RTC_IO_TOUCH_PAD13_SLP_SEL_M, RTC_IO_TOUCH_PAD13_SLP_IE_M, RTC_IO_TOUCH_PAD13_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD13_HOLD_M, RTC_IO_TOUCH_PAD13_DRV_V, RTC_IO_TOUCH_PAD13_DRV_S, RTCIO_CHANNEL_13_GPIO_NUM}, //13 84 {RTC_IO_TOUCH_PAD14_REG, RTC_IO_TOUCH_PAD14_MUX_SEL_M, RTC_IO_TOUCH_PAD14_FUN_SEL_S, RTC_IO_TOUCH_PAD14_FUN_IE_M, RTC_IO_TOUCH_PAD14_RUE_M, RTC_IO_TOUCH_PAD14_RDE_M, RTC_IO_TOUCH_PAD14_SLP_SEL_M, RTC_IO_TOUCH_PAD14_SLP_IE_M, RTC_IO_TOUCH_PAD14_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD14_HOLD_M, RTC_IO_TOUCH_PAD14_DRV_V, RTC_IO_TOUCH_PAD14_DRV_S, RTCIO_CHANNEL_14_GPIO_NUM}, //14 85 {RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_SLP_OE_M, 0, RTC_CNTL_X32P_HOLD_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_CHANNEL_15_GPIO_NUM}, //15 86 {RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_SLP_OE_M, 0, RTC_CNTL_X32N_HOLD_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_CHANNEL_16_GPIO_NUM}, //16 87 {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_SLP_OE_M, 0, RTC_CNTL_PDAC1_HOLD_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_CHANNEL_17_GPIO_NUM}, //17 88 {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_SLP_OE_M, 0, RTC_CNTL_PDAC2_HOLD_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_CHANNEL_18_GPIO_NUM}, //18 89 {RTC_IO_RTC_PAD19_REG, RTC_IO_PAD19_MUX_SEL_M, RTC_IO_PAD19_FUN_SEL_S, RTC_IO_PAD19_FUN_IE_M, RTC_IO_PAD19_RUE_M, RTC_IO_PAD19_RDE_M, RTC_IO_PAD19_SLP_SEL_M, RTC_IO_PAD19_SLP_IE_M, RTC_IO_PAD19_SLP_OE_M, 0, RTC_CNTL_PAD19_HOLD_M, RTC_IO_PAD19_DRV_V, RTC_IO_PAD19_DRV_S, RTCIO_CHANNEL_19_GPIO_NUM}, //19 90 {RTC_IO_RTC_PAD20_REG, RTC_IO_PAD20_MUX_SEL_M, RTC_IO_PAD20_FUN_SEL_S, RTC_IO_PAD20_FUN_IE_M, RTC_IO_PAD20_RUE_M, RTC_IO_PAD20_RDE_M, RTC_IO_PAD20_SLP_SEL_M, RTC_IO_PAD20_SLP_IE_M, RTC_IO_PAD20_SLP_OE_M, 0, RTC_CNTL_PAD20_HOLD_M, RTC_IO_PAD20_DRV_V, RTC_IO_PAD20_DRV_S, RTCIO_CHANNEL_20_GPIO_NUM}, //20 91 {RTC_IO_RTC_PAD21_REG, RTC_IO_PAD21_MUX_SEL_M, RTC_IO_PAD21_FUN_SEL_S, RTC_IO_PAD21_FUN_IE_M, RTC_IO_PAD21_RUE_M, RTC_IO_PAD21_RDE_M, RTC_IO_PAD21_SLP_SEL_M, RTC_IO_PAD21_SLP_IE_M, RTC_IO_PAD21_SLP_OE_M, 0, RTC_CNTL_PAD21_HOLD_M, RTC_IO_PAD21_DRV_V, RTC_IO_PAD21_DRV_S, RTCIO_CHANNEL_21_GPIO_NUM}, //21 92 }; 93
