1 /********************************************************************* 2 * SEGGER Microcontroller GmbH * 3 * The Embedded Experts * 4 ********************************************************************** 5 * * 6 * (c) 1995 - 2021 SEGGER Microcontroller GmbH * 7 * * 8 * www.segger.com Support: support@segger.com * 9 * * 10 ********************************************************************** 11 * * 12 * SEGGER RTT * Real Time Transfer for embedded targets * 13 * * 14 ********************************************************************** 15 * * 16 * All rights reserved. * 17 * * 18 * SEGGER strongly recommends to not make any changes * 19 * to or modify the source code of this software in order to stay * 20 * compatible with the RTT protocol and J-Link. * 21 * * 22 * Redistribution and use in source and binary forms, with or * 23 * without modification, are permitted provided that the following * 24 * condition is met: * 25 * * 26 * o Redistributions of source code must retain the above copyright * 27 * notice, this condition and the following disclaimer. * 28 * * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 30 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 31 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 33 * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * 34 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 36 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 38 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 40 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 41 * DAMAGE. * 42 * * 43 ********************************************************************** 44 * * 45 * RTT version: 7.22 * 46 * * 47 ********************************************************************** 48 49 ---------------------------END-OF-HEADER------------------------------ 50 File : SEGGER_RTT_Conf.h 51 Purpose : Implementation of SEGGER real-time transfer (RTT) which 52 allows real-time communication on targets which support 53 debugger memory accesses while the CPU is running. 54 Revision: $Rev: 21386 $ 55 56 */ 57 58 #ifndef SEGGER_RTT_CONF_H 59 #define SEGGER_RTT_CONF_H 60 61 #ifdef __IAR_SYSTEMS_ICC__ 62 #include <intrinsics.h> 63 #endif 64 65 /********************************************************************* 66 * 67 * Defines, configurable 68 * 69 ********************************************************************** 70 */ 71 72 // 73 // Take in and set to correct values for Cortex-A systems with CPU cache 74 // 75 // #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current 76 // system #define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can 77 // be accessed uncached 78 // 79 // Most common case: 80 // Up-channel 0: RTT 81 // Up-channel 1: SystemView 82 // 83 #ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS 84 #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) 85 #endif 86 // 87 // Most common case: 88 // Down-channel 0: RTT 89 // Down-channel 1: SystemView 90 // 91 #ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 92 #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) 93 #endif 94 95 #ifndef BUFFER_SIZE_UP 96 #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) 97 #endif 98 99 #ifndef BUFFER_SIZE_DOWN 100 #define BUFFER_SIZE_DOWN \ 101 (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) 102 #endif 103 104 #ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE 105 #define SEGGER_RTT_PRINTF_BUFFER_SIZE \ 106 (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) 107 #endif 108 109 #ifndef SEGGER_RTT_MODE_DEFAULT 110 #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) 111 #endif 112 113 /********************************************************************* 114 * 115 * RTT memcpy configuration 116 * 117 * memcpy() is good for large amounts of data, 118 * but the overhead is big for small amounts, which are usually stored via RTT. 119 * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. 120 * 121 * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. 122 * This is may be required with memory access restrictions, 123 * such as on Cortex-A devices with MMU. 124 */ 125 #ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP 126 #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop 127 #endif 128 // 129 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets 130 // 131 // #if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) 132 // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) 133 // #endif 134 135 // 136 // Target is not allowed to perform other RTT operations while string still has not been stored completely. 137 // Otherwise we would probably end up with a mixed string in the buffer. 138 // If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and 139 // SEGGER_RTT_UNLOCK() function here. 140 // 141 // SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. 142 // Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. 143 // When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to 144 // be adjusted accordingly. (Higher priority = lower priority number) Default value for embOS: 128u Default 145 // configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 146 // - configPRIO_BITS) ) In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are 147 // implemented in NVIC or define SEGGER_RTT_LOCK() to completely disable interrupts. 148 // 149 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 150 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY \ 151 (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) 152 #endif 153 154 /********************************************************************* 155 * 156 * RTT lock configuration for SEGGER Embedded Studio, 157 * Rowley CrossStudio and GCC 158 */ 159 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || \ 160 defined(__clang__)) && \ 161 !defined(__CC_ARM) && !defined(WIN32)) 162 #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) 163 #define SEGGER_RTT_LOCK() \ 164 { \ 165 unsigned int _SEGGER_RTT__LockState; \ 166 __asm volatile( \ 167 "mrs %0, primask \n\t" \ 168 "movs r1, #1 \n\t" \ 169 "msr primask, r1 \n\t" \ 170 : "=r"(_SEGGER_RTT__LockState) \ 171 : \ 172 : "r1", "cc"); 173 174 #define SEGGER_RTT_UNLOCK() \ 175 __asm volatile("msr primask, %0 \n\t" : : "r"(_SEGGER_RTT__LockState) :); \ 176 } 177 #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) 178 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 179 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 180 #endif 181 #define SEGGER_RTT_LOCK() \ 182 { \ 183 unsigned int _SEGGER_RTT__LockState; \ 184 __asm volatile( \ 185 "mrs %0, basepri \n\t" \ 186 "mov r1, %1 \n\t" \ 187 "msr basepri, r1 \n\t" \ 188 : "=r"(_SEGGER_RTT__LockState) \ 189 : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ 190 : "r1", "cc"); 191 192 #define SEGGER_RTT_UNLOCK() \ 193 __asm volatile("msr basepri, %0 \n\t" : : "r"(_SEGGER_RTT__LockState) :); \ 194 } 195 196 #elif defined(__ARM_ARCH_7A__) 197 #define SEGGER_RTT_LOCK() \ 198 { \ 199 unsigned int _SEGGER_RTT__LockState; \ 200 __asm volatile( \ 201 "mrs r1, CPSR \n\t" \ 202 "mov %0, r1 \n\t" \ 203 "orr r1, r1, #0xC0 \n\t" \ 204 "msr CPSR_c, r1 \n\t" \ 205 : "=r"(_SEGGER_RTT__LockState) \ 206 : \ 207 : "r1", "cc"); 208 209 #define SEGGER_RTT_UNLOCK() \ 210 __asm volatile( \ 211 "mov r0, %0 \n\t" \ 212 "mrs r1, CPSR \n\t" \ 213 "bic r1, r1, #0xC0 \n\t" \ 214 "and r0, r0, #0xC0 \n\t" \ 215 "orr r1, r1, r0 \n\t" \ 216 "msr CPSR_c, r1 \n\t" \ 217 : \ 218 : "r"(_SEGGER_RTT__LockState) \ 219 : "r0", "r1", "cc"); \ 220 } 221 #elif defined(__riscv) || defined(__riscv_xlen) 222 #define SEGGER_RTT_LOCK() \ 223 { \ 224 unsigned int _SEGGER_RTT__LockState; \ 225 __asm volatile( \ 226 "csrr %0, mstatus \n\t" \ 227 "csrci mstatus, 8 \n\t" \ 228 "andi %0, %0, 8 \n\t" \ 229 : "=r"(_SEGGER_RTT__LockState) \ 230 : \ 231 :); 232 233 #define SEGGER_RTT_UNLOCK() \ 234 __asm volatile( \ 235 "csrr a1, mstatus \n\t" \ 236 "or %0, %0, a1 \n\t" \ 237 "csrs mstatus, %0 \n\t" \ 238 : \ 239 : "r"(_SEGGER_RTT__LockState) \ 240 : "a1"); \ 241 } 242 #else 243 #define SEGGER_RTT_LOCK() 244 #define SEGGER_RTT_UNLOCK() 245 #endif 246 #endif 247 248 /********************************************************************* 249 * 250 * RTT lock configuration for IAR EWARM 251 */ 252 #ifdef __ICCARM__ 253 #if (defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || (defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) 254 #define SEGGER_RTT_LOCK() \ 255 { \ 256 unsigned int _SEGGER_RTT__LockState; \ 257 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 258 __set_PRIMASK(1); 259 260 #define SEGGER_RTT_UNLOCK() \ 261 __set_PRIMASK(_SEGGER_RTT__LockState); \ 262 } 263 #elif (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)) || (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ 264 (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ 265 (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) 266 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 267 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 268 #endif 269 #define SEGGER_RTT_LOCK() \ 270 { \ 271 unsigned int _SEGGER_RTT__LockState; \ 272 _SEGGER_RTT__LockState = __get_BASEPRI(); \ 273 __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 274 275 #define SEGGER_RTT_UNLOCK() \ 276 __set_BASEPRI(_SEGGER_RTT__LockState); \ 277 } 278 #elif (defined(__ARM7A__) && (__CORE__ == __ARM7A__)) || (defined(__ARM7R__) && (__CORE__ == __ARM7R__)) 279 #define SEGGER_RTT_LOCK() \ 280 { \ 281 unsigned int _SEGGER_RTT__LockState; \ 282 __asm volatile( \ 283 "mrs r1, CPSR \n\t" \ 284 "mov %0, r1 \n\t" \ 285 "orr r1, r1, #0xC0 \n\t" \ 286 "msr CPSR_c, r1 \n\t" \ 287 : "=r"(_SEGGER_RTT__LockState) \ 288 : \ 289 : "r1", "cc"); 290 291 #define SEGGER_RTT_UNLOCK() \ 292 __asm volatile( \ 293 "mov r0, %0 \n\t" \ 294 "mrs r1, CPSR \n\t" \ 295 "bic r1, r1, #0xC0 \n\t" \ 296 "and r0, r0, #0xC0 \n\t" \ 297 "orr r1, r1, r0 \n\t" \ 298 "msr CPSR_c, r1 \n\t" \ 299 : \ 300 : "r"(_SEGGER_RTT__LockState) \ 301 : "r0", "r1", "cc"); \ 302 } 303 #endif 304 #endif 305 306 /********************************************************************* 307 * 308 * RTT lock configuration for IAR RX 309 */ 310 #ifdef __ICCRX__ 311 #define SEGGER_RTT_LOCK() \ 312 { \ 313 unsigned long _SEGGER_RTT__LockState; \ 314 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 315 __disable_interrupt(); 316 317 #define SEGGER_RTT_UNLOCK() \ 318 __set_interrupt_state(_SEGGER_RTT__LockState); \ 319 } 320 #endif 321 322 /********************************************************************* 323 * 324 * RTT lock configuration for IAR RL78 325 */ 326 #ifdef __ICCRL78__ 327 #define SEGGER_RTT_LOCK() \ 328 { \ 329 __istate_t _SEGGER_RTT__LockState; \ 330 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 331 __disable_interrupt(); 332 333 #define SEGGER_RTT_UNLOCK() \ 334 __set_interrupt_state(_SEGGER_RTT__LockState); \ 335 } 336 #endif 337 338 /********************************************************************* 339 * 340 * RTT lock configuration for KEIL ARM 341 */ 342 #ifdef __CC_ARM 343 #if (defined __TARGET_ARCH_6S_M) 344 #define SEGGER_RTT_LOCK() \ 345 { \ 346 unsigned int _SEGGER_RTT__LockState; \ 347 register unsigned char _SEGGER_RTT__PRIMASK __asm("primask"); \ 348 _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ 349 _SEGGER_RTT__PRIMASK = 1u; \ 350 __schedule_barrier(); 351 352 #define SEGGER_RTT_UNLOCK() \ 353 _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ 354 __schedule_barrier(); \ 355 } 356 #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) 357 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 358 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 359 #endif 360 #define SEGGER_RTT_LOCK() \ 361 { \ 362 unsigned int _SEGGER_RTT__LockState; \ 363 register unsigned char BASEPRI __asm("basepri"); \ 364 _SEGGER_RTT__LockState = BASEPRI; \ 365 BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ 366 __schedule_barrier(); 367 368 #define SEGGER_RTT_UNLOCK() \ 369 BASEPRI = _SEGGER_RTT__LockState; \ 370 __schedule_barrier(); \ 371 } 372 #endif 373 #endif 374 375 /********************************************************************* 376 * 377 * RTT lock configuration for TI ARM 378 */ 379 #ifdef __TI_ARM__ 380 #if defined(__TI_ARM_V6M0__) 381 #define SEGGER_RTT_LOCK() \ 382 { \ 383 unsigned int _SEGGER_RTT__LockState; \ 384 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 385 __set_PRIMASK(1); 386 387 #define SEGGER_RTT_UNLOCK() \ 388 __set_PRIMASK(_SEGGER_RTT__LockState); \ 389 } 390 #elif (defined(__TI_ARM_V7M3__) || defined(__TI_ARM_V7M4__)) 391 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 392 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 393 #endif 394 #define SEGGER_RTT_LOCK() \ 395 { \ 396 unsigned int _SEGGER_RTT__LockState; \ 397 _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 398 399 #define SEGGER_RTT_UNLOCK() \ 400 _set_interrupt_priority(_SEGGER_RTT__LockState); \ 401 } 402 #endif 403 #endif 404 405 /********************************************************************* 406 * 407 * RTT lock configuration for CCRX 408 */ 409 #ifdef __RX 410 #include <machine.h> 411 #define SEGGER_RTT_LOCK() \ 412 { \ 413 unsigned long _SEGGER_RTT__LockState; \ 414 _SEGGER_RTT__LockState = get_psw() & 0x010000; \ 415 clrpsw_i(); 416 417 #define SEGGER_RTT_UNLOCK() \ 418 set_psw(get_psw() | _SEGGER_RTT__LockState); \ 419 } 420 #endif 421 422 /********************************************************************* 423 * 424 * RTT lock configuration for embOS Simulation on Windows 425 * (Can also be used for generic RTT locking with embOS) 426 */ 427 #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) 428 429 void OS_SIM_EnterCriticalSection(void); 430 void OS_SIM_LeaveCriticalSection(void); 431 432 #define SEGGER_RTT_LOCK() \ 433 { \ 434 OS_SIM_EnterCriticalSection(); 435 436 #define SEGGER_RTT_UNLOCK() \ 437 OS_SIM_LeaveCriticalSection(); \ 438 } 439 #endif 440 441 /********************************************************************* 442 * 443 * RTT lock configuration fallback 444 */ 445 #ifndef SEGGER_RTT_LOCK 446 #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) 447 #endif 448 449 #ifndef SEGGER_RTT_UNLOCK 450 #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) 451 #endif 452 453 #endif 454 /*************************** End of file ****************************/ 455
