1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #include "hal/interrupt_controller_hal.h" 16 #include "soc/soc_caps.h" 17 18 #if __riscv 19 #include "riscv/instruction_decode.h" 20 is_interrupt_number_reserved(int interrupt_number)21static bool is_interrupt_number_reserved(int interrupt_number) 22 { 23 // Workaround to reserve interrupt number 1 for Wi-Fi, 5,8 for Bluetooth, 6 for "permanently disabled interrupt" 24 // [TODO: IDF-2465] 25 const uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8); 26 if (reserved & BIT(interrupt_number)) { 27 return true; 28 } 29 30 extern int _vector_table; 31 extern int _interrupt_handler; 32 const intptr_t pc = (intptr_t)(&_vector_table + interrupt_number); 33 34 /* JAL instructions are relative to the PC there are executed from. */ 35 const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc); 36 37 return destination != (intptr_t)&_interrupt_handler; 38 } 39 #endif 40 interrupt_controller_hal_desc_type(int interrupt_number)41int_type_t interrupt_controller_hal_desc_type(int interrupt_number) 42 { 43 #ifndef SOC_CPU_HAS_FLEXIBLE_INTC 44 const int_desc_t *int_desc = interrupt_controller_hal_desc_table(); 45 return (int_desc[interrupt_number].type); 46 #else 47 return (INTTP_NA); 48 #endif 49 } 50 interrupt_controller_hal_desc_level(int interrupt_number)51int interrupt_controller_hal_desc_level(int interrupt_number) 52 { 53 #ifndef SOC_CPU_HAS_FLEXIBLE_INTC 54 const int_desc_t *int_desc = interrupt_controller_hal_desc_table(); 55 return (int_desc[interrupt_number].level); 56 #else 57 return 1; 58 #endif 59 } 60 interrupt_controller_hal_desc_flags(int interrupt_number,int cpu_number)61int_desc_flag_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number) 62 { 63 #ifndef SOC_CPU_HAS_FLEXIBLE_INTC 64 const int_desc_t *int_desc = interrupt_controller_hal_desc_table(); 65 return (int_desc[interrupt_number].cpuflags[cpu_number]); 66 #else 67 #if __riscv 68 return is_interrupt_number_reserved(interrupt_number) ? INTDESC_RESVD : INTDESC_NORMAL; 69 #else 70 return INTDESC_NORMAL; 71 #endif 72 #endif 73 } 74
