1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "sdkconfig.h"
16 #include "hal/interrupt_controller_hal.h"
17 #include "hal/interrupt_controller_ll.h"
18 #include "soc/soc_caps.h"
19 #include "soc/soc.h"
20
21 //We should mark the interrupt for the timer used by FreeRTOS as reserved. The specific timer
22 //is selectable using menuconfig; we use these cpp bits to convert that into something we can use in
23 //the table below.
24 #if CONFIG_FREERTOS_CORETIMER_0
25 #define INT6RES INTDESC_RESVD
26 #else
27 #define INT6RES INTDESC_SPECIAL
28 #endif
29
30 #if CONFIG_FREERTOS_CORETIMER_1
31 #define INT15RES INTDESC_RESVD
32 #else
33 #define INT15RES INTDESC_SPECIAL
34 #endif
35
36 //This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
37 const static int_desc_t interrupt_descriptor_table [32]={
38 { 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //0
39 { 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //1
40 { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //2
41 { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //3
42 { 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_NORMAL} }, //4
43 { 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //5
44 { 1, INTTP_NA, {INT6RES, INT6RES } }, //6
45 { 1, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //7
46 { 1, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //8
47 { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //9
48 { 1, INTTP_EDGE , {INTDESC_NORMAL, INTDESC_NORMAL} }, //10
49 { 3, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //11
50 { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //12
51 { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //13
52 { 7, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //14, NMI
53 { 3, INTTP_NA, {INT15RES, INT15RES } }, //15
54 { 5, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL} }, //16
55 { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //17
56 { 1, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //18
57 { 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //19
58 { 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //20
59 { 2, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //21
60 { 3, INTTP_EDGE, {INTDESC_RESVD, INTDESC_NORMAL} }, //22
61 { 3, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_NORMAL} }, //23
62 { 4, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_NORMAL} }, //24
63 { 4, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //25
64 { 5, INTTP_LEVEL, {INTDESC_NORMAL, INTDESC_RESVD } }, //26
65 { 3, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //27
66 { 4, INTTP_EDGE, {INTDESC_NORMAL, INTDESC_NORMAL} }, //28
67 { 3, INTTP_NA, {INTDESC_SPECIAL,INTDESC_SPECIAL}}, //29
68 { 4, INTTP_EDGE, {INTDESC_RESVD, INTDESC_RESVD } }, //30
69 { 5, INTTP_LEVEL, {INTDESC_RESVD, INTDESC_RESVD } }, //31
70 };
71
interrupt_controller_hal_desc_table(void)72 const int_desc_t *interrupt_controller_hal_desc_table(void)
73 {
74 return interrupt_descriptor_table;
75 }
76
