1 /*
2 * Copyright 2024 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_xspi_nor_flash.h"
10 #include "fsl_nor_flash.h"
11
12 /*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15 #define XSPI_INSTR_CMD_IDX (0U)
16 #define XSPI_INSTR_RADDR_IDX (1U)
17 #define XSPI_INSTR_CADDR_IDX (2U)
18 #define XSPI_INSTR_READ_IDX (3U)
19 #define XSPI_INSTR_WRITE_IDX (4U)
20 #define XSPI_INSTR_MODE_IDX (5U)
21 #define XSPI_INSTR_MODE2_IDX (6U)
22 #define XSPI_INSTR_MODE4_IDX (7U)
23
24 const xspi_lut_instr_t g_xspiCommonInstr[2][8] = {
25 {kXSPI_Command_SDR, kXSPI_Command_RADDR_SDR, kXSPI_Command_CADDR_SDR, kXSPI_Command_READ_SDR,
26 kXSPI_Command_WRITE_SDR, kXSPI_Command_MODE_SDR, kXSPI_Command_MODE2_SDR, kXSPI_Command_MODE4_SDR},
27 {kXSPI_Command_DDR, kXSPI_Command_RADDR_DDR, kXSPI_Command_CADDR_DDR, kXSPI_Command_READ_DDR,
28 kXSPI_Command_WRITE_DDR, kXSPI_Command_MODE_DDR, kXSPI_Command_MODE2_DDR, kXSPI_Command_MODE4_DDR}};
29
30 /*******************************************************************************
31 * Prototypes
32 ******************************************************************************/
33 typedef struct _lut_seq_entry
34 {
35 uint32_t insrOperandPair1;
36 uint32_t insrOperandPair2;
37 uint32_t insrOperandPair3;
38 uint32_t insrOperandPair4;
39 uint32_t insrOperandPair5;
40 } lut_seq_entry_t;
41
42 typedef struct _lut_seq_instr_operand
43 {
44 uint16_t operand : 8U;
45 uint16_t padNum : 2U;
46 uint16_t instr : 6U;
47 } lut_seq_instr_operand_t;
48 /*******************************************************************************
49 * Variables
50 ******************************************************************************/
51
52 XSPI_Type *curXSPIBase = NULL;
53 xspi_mem_nor_handle_t xspiMemNorHandle;
54
55 static uint32_t s_socXspiAmbaBase[] = XSPI_AMBA_BASES;
56
57 lut_seq_entry_t g_xspiLut[16] = {0UL};
58 /*******************************************************************************
59 * Code
60 ******************************************************************************/
61
XSPI_NOR_ReadSFDP(uint32_t address,uint32_t * buffer,uint32_t bytes)62 static status_t XSPI_NOR_ReadSFDP(uint32_t address, uint32_t *buffer, uint32_t bytes)
63 {
64 xspi_transfer_t flashXfer;
65 status_t status = kStatus_InvalidArgument;
66
67 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
68
69 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId] + address;
70 flashXfer.cmdType = kXSPI_Read;
71 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ_SFDP;
72 flashXfer.data = (uint32_t *)(void *)buffer;
73 flashXfer.dataSize = bytes;
74 flashXfer.targetGroup = xspiMemNorHandle.selectedTg; /* Target group selection is from application. */
75
76 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
77
78 return status;
79 }
80
XSPI_NOR_ProbeNorFlashSfdpHeader(void)81 static status_t XSPI_NOR_ProbeNorFlashSfdpHeader(void)
82 {
83 uint8_t sfdpLutIndex = 0U;
84 xspi_device_config_t tmpNorFlashConfig;
85 sfdp_protocol_type_t tmpProtocol = kSFDP_Protocol_1s1s1s;
86 /* Data strobe used for 4s-4d-4d and 8D-8D-8D. */
87 xspi_device_ddr_config_t tmpDeviceDDRConfig;
88
89 struct _probedInfo
90 {
91 sfdp_protocol_type_t protocolMode;
92 uint8_t addrWidth;
93 } probedInfo[12] = {
94 {kSFDP_Protocol_1s1s1s, 24U}, {kSFDP_Protocol_2s2s2s, 24U}, {kSFDP_Protocol_4s4s4s, 24U},
95 {kSFDP_Protocol_4s4d4d, 24U}, {kSFDP_Protocol_8d8d8d, 32U}, {kSFDP_Protocol_8d8d8d, 32U},
96 {kSFDP_Protocol_8d8d8d, 24U}, {kSFDP_Protocol_8d8d8d, 24U}, {kSFDP_Protocol_8s8s8s, 32U},
97 {kSFDP_Protocol_8s8s8s, 32U}, {kSFDP_Protocol_8s8s8s, 24U}, {kSFDP_Protocol_8s8s8s, 24U},
98 };
99 /* Read SFDP command can be used with device supported mode if (1s-1s-1s), (2s-2s-2s),
100 (4s-4s-4s), (4s-4d-4d) and (8D-8D-8D). For the (8D-8D-8D) mode, the instruction 5Ah and 50 MHz requirements
101 remain the same, while 24 or 32 address bit, and a variable number of wait states may be used. */
102 lut_seq_entry_t sfdp_lut[12] = {
103 /* Read SFDP in 1s-1s-1s mode. */
104 {
105 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_1PAD, 0x5A, kXSPI_Command_RADDR_SDR, kXSPI_1PAD, 24),
106 XSPI_LUT_SEQ(kXSPI_Command_DUMMY_SDR, kXSPI_1PAD, 8, kXSPI_Command_READ_SDR, kXSPI_1PAD, 0xFF),
107 0UL,
108 0UL,
109 0UL,
110 },
111
112 /* Read SFDP in 2s-2s-2s mode. */
113 {
114 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_2PAD, 0x5A, kXSPI_Command_RADDR_SDR, kXSPI_2PAD, 24),
115 XSPI_LUT_SEQ(kXSPI_Command_DUMMY_SDR, kXSPI_2PAD, 8, kXSPI_Command_READ_SDR, kXSPI_2PAD, 0xFF),
116 0UL,
117 0UL,
118 0UL,
119 },
120 /* Read SFDP in 4s-4s-4s mode. */
121 {
122 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_4PAD, 0x5A, kXSPI_Command_RADDR_SDR, kXSPI_4PAD, 24),
123 XSPI_LUT_SEQ(kXSPI_Command_DUMMY_SDR, kXSPI_4PAD, 8, kXSPI_Command_READ_SDR, kXSPI_4PAD, 0xFF),
124 0UL,
125 0UL,
126 0UL,
127 },
128 /* Read SFDP in 4s-4d-4d mode. */
129 {
130 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_4PAD, 0x5A, kXSPI_Command_RADDR_DDR, kXSPI_4PAD, 24),
131 XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_4PAD, 0xFF, 0U, 0U, 0U),
132 0UL,
133 0UL,
134 0UL,
135 },
136 /* Read SFDP in 8D-8D-8D mode, with extension is the inverse of the command and 32 bit address */
137 {
138 XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0x5AU, kXSPI_Command_DDR, kXSPI_8PAD, 0xA5U),
139 XSPI_LUT_SEQ(kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 32U, kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 20U),
140 XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_8PAD, 0xFFU, 0U, 0U, 0U),
141 0UL,
142 0UL,
143 },
144 /* Read SFDP in 8D-8D-8D mode, with same extension cmd and 32 bit address */
145 {
146 XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0x5A, kXSPI_Command_DDR, kXSPI_8PAD, 0x5A),
147 XSPI_LUT_SEQ(kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 32, kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 20U),
148 XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_8PAD, 0xFF, 0U, 0U, 0U),
149 0UL,
150 0UL,
151 },
152 /* Read SFDP in 8D-8D-8D mode, with same extension cmd and 24 bit address */
153 {
154 XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0x5A, kXSPI_Command_DDR, kXSPI_8PAD, 0x5A),
155 XSPI_LUT_SEQ(kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 24, kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 20U),
156 XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_8PAD, 0xFF, 0U, 0U, 0U),
157 0UL,
158 0UL,
159 },
160
161 /* Read SFDP in 8D-8D-8D mode, with extension is the inverse of the command and 24 bit address */
162 {
163 XSPI_LUT_SEQ(kXSPI_Command_DDR, kXSPI_8PAD, 0x5A, kXSPI_Command_DDR, kXSPI_8PAD, 0xA5),
164 XSPI_LUT_SEQ(kXSPI_Command_RADDR_DDR, kXSPI_8PAD, 24, kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 20U),
165 XSPI_LUT_SEQ(kXSPI_Command_READ_DDR, kXSPI_8PAD, 0xFF, 0U, 0U, 0U),
166 0UL,
167 0UL,
168 },
169 /* Read SFDP in 8S-8S-8S mode, with extension is the inverse of the command and 32 bit address */
170 {
171 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_8PAD, 0x5AU, kXSPI_Command_SDR, kXSPI_8PAD, 0xA5U),
172 XSPI_LUT_SEQ(kXSPI_Command_RADDR_SDR, kXSPI_8PAD, 32U, kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 20U),
173 XSPI_LUT_SEQ(kXSPI_Command_READ_SDR, kXSPI_8PAD, 0xFFU, 0U, 0U, 0U),
174 0UL,
175 0UL,
176 },
177 /* Read SFDP in 8S-8S-8S mode, with same extension cmd and 32 bit address */
178 {
179 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_8PAD, 0x5A, kXSPI_Command_SDR, kXSPI_8PAD, 0x5A),
180 XSPI_LUT_SEQ(kXSPI_Command_RADDR_SDR, kXSPI_8PAD, 32, kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 20U),
181 XSPI_LUT_SEQ(kXSPI_Command_READ_SDR, kXSPI_8PAD, 0xFF, 0U, 0U, 0U),
182 0UL,
183 0UL,
184 },
185 /* Read SFDP in 8S-8S-8S mode, with same extension cmd and 24 bit address */
186 {
187 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_8PAD, 0x5A, kXSPI_Command_SDR, kXSPI_8PAD, 0x5A),
188 XSPI_LUT_SEQ(kXSPI_Command_RADDR_SDR, kXSPI_8PAD, 24, kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 20U),
189 XSPI_LUT_SEQ(kXSPI_Command_READ_SDR, kXSPI_8PAD, 0xFF, 0U, 0U, 0U),
190 0UL,
191 0UL,
192 },
193
194 /* Read SFDP in 8S-8S-8S mode, with extension is the inverse of the command and 24 bit address */
195 {
196 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_8PAD, 0x5A, kXSPI_Command_SDR, kXSPI_8PAD, 0xA5),
197 XSPI_LUT_SEQ(kXSPI_Command_RADDR_SDR, kXSPI_8PAD, 24, kXSPI_Command_DUMMY_SDR, kXSPI_8PAD, 20U),
198 XSPI_LUT_SEQ(kXSPI_Command_READ_SDR, kXSPI_8PAD, 0xFF, 0U, 0U, 0U),
199 0UL,
200 0UL,
201 },
202 };
203
204 for (sfdpLutIndex = 0U; sfdpLutIndex < ARRAY_SIZE(sfdp_lut); sfdpLutIndex++)
205 {
206 tmpNorFlashConfig.addrMode = kXSPI_DeviceByteAddressable;
207 tmpNorFlashConfig.columnAddrWidth = 0U;
208 tmpNorFlashConfig.CSHoldTime = 3U;
209 tmpNorFlashConfig.CSSetupTime = 3U;
210 tmpNorFlashConfig.deviceInterface = kXSPI_StrandardExtendedSPI;
211 tmpNorFlashConfig.enableCASInterleaving = false;
212 tmpNorFlashConfig.enableCknPad = false;
213 tmpNorFlashConfig.interfaceSettings.strandardExtendedSPISettings.pageSize = 256U;
214 tmpNorFlashConfig.ptrDeviceDdrConfig = NULL;
215 tmpNorFlashConfig.ptrDeviceRegInfo = NULL;
216 tmpNorFlashConfig.sampleClkConfig.dllConfig.dllMode = kXSPI_AutoUpdateMode;
217 tmpNorFlashConfig.sampleClkConfig.dllConfig.useRefValue = true;
218 tmpNorFlashConfig.sampleClkConfig.enableDQSLatency = false;
219 tmpNorFlashConfig.sampleClkConfig.sampleClkSource = kXSPI_SampleClkFromDqsPadLoopback;
220 tmpNorFlashConfig.deviceSize[0] = 0x40;
221 tmpNorFlashConfig.deviceSize[1] = 0x40;
222 tmpNorFlashConfig.xspiRootClk = xspiMemNorHandle.clkFreq; /* Set as 50MHz to read SFDP. */
223
224 tmpProtocol = probedInfo[sfdpLutIndex].protocolMode;
225
226 if (((uint32_t)tmpProtocol & 0x100UL) != 0UL)
227 {
228 tmpDeviceDDRConfig.enableDdr = true;
229 }
230 else
231 {
232 tmpDeviceDDRConfig.enableDdr = false;
233 }
234
235 if (sfdpLutIndex >= 3U)
236 {
237 tmpDeviceDDRConfig.enableByteSwapInOctalMode = false;
238 tmpDeviceDDRConfig.ddrDataAlignedClk = kXSPI_DDRDataAlignedWith2xInternalRefClk;
239 tmpNorFlashConfig.sampleClkConfig.sampleClkSource = kXSPI_SampleClkFromExternalDQS;
240 tmpNorFlashConfig.ptrDeviceDdrConfig = &tmpDeviceDDRConfig;
241 }
242
243 XSPI_SetDeviceConfig(curXSPIBase, &tmpNorFlashConfig);
244 XSPI_EnableModule(curXSPIBase, true);
245
246 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_READ_SFDP * 5U, &(sfdp_lut[sfdpLutIndex].insrOperandPair1), 5U);
247
248 sfdp_ret_type_t ret;
249 ret = SFDP_ReadSFDPHeader(xspiMemNorHandle.ptrSfdpHandle, XSPI_NOR_ReadSFDP);
250
251 if ((ret == kSFDP_RET_Success) && (sfdpLutIndex < ARRAY_SIZE(sfdp_lut)))
252 {
253 /* successfully to read SFDP header from external device. */
254
255 /* recode current protocol type and address width. */
256 xspiMemNorHandle.curProtocolType = probedInfo[sfdpLutIndex].protocolMode;
257 xspiMemNorHandle.addrSize = probedInfo[sfdpLutIndex].addrWidth;
258 break;
259 }
260 else if ((sfdpLutIndex == (ARRAY_SIZE(sfdp_lut) - 1U)) && (ret != kSFDP_RET_Success))
261 {
262 return kStatus_Fail;
263 }
264 else
265 {
266 }
267 }
268
269 return kStatus_Success;
270 }
271
XSPI_NOR_Enter4ByteMode(void)272 static status_t XSPI_NOR_Enter4ByteMode(void)
273 {
274 status_t status = kStatus_Success;
275 sfdp_4_byte_addr_enter_method_t enterMethod = SFDP_Get4ByteAddrModeEnterMethod(xspiMemNorHandle.ptrSfdpHandle);
276 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
277 xspi_transfer_t flashXfer;
278
279 switch (enterMethod)
280 {
281 case kSFDP_4ByteAddrEnterMethod0:
282 {
283 memset((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, 0UL, sizeof(lut_seq_entry_t));
284 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1 =
285 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_1PAD, 0xB7U, kXSPI_Command_STOP, kXSPI_1PAD, 0U);
286
287 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
288 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
289
290 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
291 flashXfer.cmdType = kXSPI_Command;
292 flashXfer.data = NULL;
293 flashXfer.dataSize = 0U;
294 flashXfer.lockArbitration = false;
295 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
296 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
297
298 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
299 if (status != kStatus_Success)
300 {
301 return status;
302 }
303 break;
304 }
305 case kSFDP_4ByteAddrEnterMethod1:
306 {
307 memset((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, 0UL, sizeof(lut_seq_entry_t));
308 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1 =
309 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_1PAD, 0x06U, kXSPI_Command_SDR, kXSPI_1PAD, 0xB7U);
310
311 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
312 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
313
314 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
315 flashXfer.cmdType = kXSPI_Command;
316 flashXfer.data = NULL;
317 flashXfer.dataSize = 0U;
318 flashXfer.lockArbitration = false;
319 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
320 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
321
322 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
323 break;
324 }
325 case kSFDP_4ByteAddrEnterMethod2:
326 {
327 break;
328 }
329 case kSFDP_4ByteAddrEnterMethod3:
330 {
331 break;
332 }
333 case kSFDP_4ByteAddrEnterMethod4:
334 {
335 break;
336 }
337 case kSFDP_4ByteAddrEnterMethod5:
338 {
339 /* The flash device support dedicated 4-byte address instruction set, no actions to do. */
340 break;
341 }
342 case kSFDP_4ByteAddrEnterMethod6:
343 {
344 /* Always operats in 4-byte address mode, no action to do. */
345 break;
346 }
347 default:
348 {
349 assert(false);
350 }
351 }
352
353 return status;
354 }
355
XSPI_NOR_SetNorFlashDeviceConfig(xspi_memory_config_t * ptrUserInputMemConfig)356 static status_t XSPI_NOR_SetNorFlashDeviceConfig(xspi_memory_config_t *ptrUserInputMemConfig)
357 {
358 xspi_device_ddr_config_t externalDeviceDdrConfig;
359 xspi_device_status_reg_info_t norFlashStatusRegInfo;
360 xspi_device_config_t externNorFlashConfig;
361 status_t status;
362
363 externalDeviceDdrConfig.enableDdr = SFDP_CheckDTRSupported(xspiMemNorHandle.ptrSfdpHandle);
364 externalDeviceDdrConfig.enableByteSwapInOctalMode = SFDP_CheckByteSwapInOctalMode(xspiMemNorHandle.ptrSfdpHandle);
365 externalDeviceDdrConfig.ddrDataAlignedClk = kXSPI_DDRDataAlignedWith2xInternalRefClk;
366
367 sfdp_wip_bit_info_t wipInfo;
368 SFDP_GetBusyBitInfo(xspiMemNorHandle.ptrSfdpHandle, (sfdp_flash_pad_num_t)ptrUserInputMemConfig->numPadUsed,
369 &wipInfo);
370
371 norFlashStatusRegInfo.wipLocation = wipInfo.location;
372 norFlashStatusRegInfo.value1Expired = wipInfo.polarity;
373 norFlashStatusRegInfo.upperHalfWordSelected = wipInfo.upperHalfWordSelected;
374
375 (void)memset((void *)(uint32_t)&externNorFlashConfig, 0UL, sizeof(externNorFlashConfig));
376
377 externNorFlashConfig.ptrDeviceRegInfo = &norFlashStatusRegInfo;
378 externNorFlashConfig.deviceSize[0] = SFDP_GetFlashDensity(xspiMemNorHandle.ptrSfdpHandle);
379 externNorFlashConfig.deviceSize[1] = externNorFlashConfig.deviceSize[0];
380 externNorFlashConfig.ptrDeviceDdrConfig = &externalDeviceDdrConfig;
381 externNorFlashConfig.enableCknPad = ptrUserInputMemConfig->enableClknPad;
382 externNorFlashConfig.deviceInterface = kXSPI_StrandardExtendedSPI;
383 externNorFlashConfig.interfaceSettings.strandardExtendedSPISettings.pageSize =
384 SFDP_GetPageSize(xspiMemNorHandle.ptrSfdpHandle);
385 externNorFlashConfig.addrMode = ptrUserInputMemConfig->addrMode;
386 externNorFlashConfig.columnAddrWidth = 0U;
387 externNorFlashConfig.CSHoldTime = 3U;
388 externNorFlashConfig.CSSetupTime = 3U;
389 externNorFlashConfig.enableCASInterleaving = false;
390 externNorFlashConfig.sampleClkConfig = ptrUserInputMemConfig->sampleClkConfig;
391 externNorFlashConfig.xspiRootClk = ptrUserInputMemConfig->xspiRootClk;
392
393 status = XSPI_SetDeviceConfig(curXSPIBase, &externNorFlashConfig);
394
395 xspiMemNorHandle.memSizeInByte = externNorFlashConfig.deviceSize[0] * 1024UL;
396 xspiMemNorHandle.norFlashStatusRegInfo = norFlashStatusRegInfo;
397
398 return status;
399 }
400
XSPI_NOR_FillPageProgramLutSeq(void)401 static void XSPI_NOR_FillPageProgramLutSeq(void)
402 {
403 xspi_lut_instr_t cmdInstr;
404 xspi_lut_instr_t raddrInstr;
405 xspi_lut_instr_t writeInstr;
406
407 sfdp_flash_pad_num_t instrPad;
408 uint8_t instrDDR;
409 sfdp_flash_pad_num_t addrPad;
410 uint8_t addrDDR;
411 sfdp_flash_pad_num_t dataPad;
412 uint8_t dataDDR;
413
414 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
415
416 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
417 raddrInstr = g_xspiCommonInstr[addrDDR][XSPI_INSTR_RADDR_IDX];
418 writeInstr = g_xspiCommonInstr[dataDDR][XSPI_INSTR_WRITE_IDX];
419
420 sfdp_page_program_cmd_info_t pageProgramCmdInfo;
421
422 SFDP_GetPageProgramCmdInfo(xspiMemNorHandle.ptrSfdpHandle, xspiMemNorHandle.curProtocolType, &pageProgramCmdInfo);
423
424 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
425 {
426 uint8_t cmdInstrExtension =
427 SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, pageProgramCmdInfo.instruction);
428
429 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM].insrOperandPair1 =
430 XSPI_LUT_SEQ(cmdInstr, (xspi_pad_t)instrPad, pageProgramCmdInfo.instruction, cmdInstr, (xspi_pad_t)instrPad,
431 cmdInstrExtension);
432 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM].insrOperandPair2 = XSPI_LUT_SEQ(
433 raddrInstr, (xspi_pad_t)addrPad, xspiMemNorHandle.addrSize, writeInstr, (xspi_pad_t)dataPad, 0x8U);
434 }
435 else
436 {
437 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM].insrOperandPair1 =
438 XSPI_LUT_SEQ(cmdInstr, (xspi_pad_t)instrPad, pageProgramCmdInfo.instruction, raddrInstr,
439 (xspi_pad_t)addrPad, xspiMemNorHandle.addrSize);
440 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM].insrOperandPair2 =
441 XSPI_LUT_SEQ(writeInstr, (xspi_pad_t)dataPad, 0x8U, 0x0U, 0x0U, 0x0U);
442 }
443 }
444
XSPI_NOR_FillSectorEraseLutSeq(void)445 static void XSPI_NOR_FillSectorEraseLutSeq(void)
446 {
447 xspi_lut_instr_t cmdInstr;
448 xspi_lut_instr_t raddrInstr;
449 sfdp_flash_pad_num_t instrPad;
450 uint8_t instrDDR;
451 sfdp_flash_pad_num_t addrPad;
452 uint8_t addrDDR;
453 sfdp_flash_pad_num_t dataPad;
454 uint8_t dataDDR;
455
456 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
457
458 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
459 raddrInstr = g_xspiCommonInstr[addrDDR][XSPI_INSTR_RADDR_IDX];
460
461 sfdp_erase_cmd_info_t sectorEraseCmdInfo;
462
463 if (SFDP_GetSectorEraseCmdInfo(xspiMemNorHandle.ptrSfdpHandle, kSFDP_EraseCmdType1, §orEraseCmdInfo) ==
464 kSFDP_RET_Success)
465 {
466 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
467 {
468 uint8_t cmdInstrExtension =
469 SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, sectorEraseCmdInfo.instruction);
470
471 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ERASESECTOR].insrOperandPair1 =
472 XSPI_LUT_SEQ(cmdInstr, instrPad, sectorEraseCmdInfo.instruction, cmdInstr, instrPad, cmdInstrExtension);
473 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ERASESECTOR].insrOperandPair2 =
474 XSPI_LUT_SEQ(raddrInstr, addrPad, xspiMemNorHandle.addrSize, kXSPI_Command_STOP, instrPad, 0U);
475 }
476 else
477 {
478 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ERASESECTOR].insrOperandPair1 = XSPI_LUT_SEQ(
479 cmdInstr, instrPad, sectorEraseCmdInfo.instruction, raddrInstr, addrPad, xspiMemNorHandle.addrSize);
480 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ERASESECTOR].insrOperandPair2 =
481 XSPI_LUT_SEQ(kXSPI_Command_STOP, instrPad, 0x0U, 0x0U, 0x0U, 0x0U);
482 }
483 }
484
485 xspiMemNorHandle.sectorSizeInByte = sectorEraseCmdInfo.eraseSize;
486 (void)dataPad;
487 (void)dataDDR;
488 }
489
XSPI_NOR_FillBlockEraseLutSeq(void)490 static void XSPI_NOR_FillBlockEraseLutSeq(void)
491 {
492 xspi_lut_instr_t cmdInstr;
493 xspi_lut_instr_t raddrInstr;
494 sfdp_flash_pad_num_t instrPad;
495 uint8_t instrDDR;
496 sfdp_flash_pad_num_t addrPad;
497 uint8_t addrDDR;
498 sfdp_flash_pad_num_t dataPad;
499 uint8_t dataDDR;
500
501 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
502
503 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
504 raddrInstr = g_xspiCommonInstr[addrDDR][XSPI_INSTR_RADDR_IDX];
505
506 sfdp_erase_cmd_info_t sectorEraseCmdInfo;
507
508 if (SFDP_GetSectorEraseCmdInfo(xspiMemNorHandle.ptrSfdpHandle, kSFDP_EraseCmdType2, §orEraseCmdInfo) ==
509 kSFDP_RET_Success)
510 {
511 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
512 {
513 uint8_t cmdInstrExtension =
514 SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, sectorEraseCmdInfo.instruction);
515 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK].insrOperandPair1 =
516 XSPI_LUT_SEQ(cmdInstr, instrPad, sectorEraseCmdInfo.instruction, cmdInstr, instrPad, cmdInstrExtension);
517 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK].insrOperandPair2 =
518 XSPI_LUT_SEQ(raddrInstr, addrPad, xspiMemNorHandle.addrSize, kXSPI_Command_STOP, instrPad, 0U);
519 }
520 else
521 {
522 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK].insrOperandPair1 = XSPI_LUT_SEQ(
523 cmdInstr, instrPad, sectorEraseCmdInfo.instruction, raddrInstr, addrPad, xspiMemNorHandle.addrSize);
524
525 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK].insrOperandPair2 =
526 XSPI_LUT_SEQ(kXSPI_Command_STOP, instrPad, 0x0U, 0x0U, 0x0U, 0x0U);
527 }
528 }
529
530 (void)dataPad;
531 (void)dataDDR;
532 }
533
XSPI_NOR_FillWriteEnableLutSeq(void)534 static void XSPI_NOR_FillWriteEnableLutSeq(void)
535 {
536 xspi_lut_instr_t cmdInstr;
537 sfdp_flash_pad_num_t instrPad;
538 uint8_t instrDDR;
539 sfdp_flash_pad_num_t addrPad;
540 uint8_t addrDDR;
541 sfdp_flash_pad_num_t dataPad;
542 uint8_t dataDDR;
543
544 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
545 (void)addrPad;
546 (void)addrDDR;
547 (void)dataPad;
548 (void)dataDDR;
549
550 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
551
552 uint8_t wrenInstr = 0x06U;
553 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
554 {
555 uint8_t wrenInstrExtension = SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, wrenInstr);
556
557 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_WRITEENABLE].insrOperandPair1 =
558 XSPI_LUT_SEQ(cmdInstr, instrPad, wrenInstr, cmdInstr, instrPad, wrenInstrExtension);
559 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_WRITEENABLE].insrOperandPair2 =
560 XSPI_LUT_SEQ(kXSPI_Command_STOP, instrPad, 0x0U, 0x0U, 0x0U, 0x0U);
561 }
562 else
563 {
564 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_WRITEENABLE].insrOperandPair1 =
565 XSPI_LUT_SEQ(cmdInstr, instrPad, wrenInstr, kXSPI_Command_STOP, instrPad, 0x0U);
566 }
567 }
568
XSPI_NOR_FillReadIdLutSeq(void)569 static void XSPI_NOR_FillReadIdLutSeq(void)
570 {
571 uint8_t readIdInstr = 0x9F;
572 xspi_lut_instr_t cmdInstr;
573 xspi_lut_instr_t readInstr;
574 xspi_lut_instr_t raddrInstr;
575
576 sfdp_flash_pad_num_t instrPad;
577 uint8_t instrDDR;
578 sfdp_flash_pad_num_t addrPad;
579 uint8_t addrDDR;
580 sfdp_flash_pad_num_t dataPad;
581 uint8_t dataDDR;
582
583 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
584
585 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
586 readInstr = g_xspiCommonInstr[dataDDR][XSPI_INSTR_READ_IDX];
587 raddrInstr = g_xspiCommonInstr[addrDDR][XSPI_INSTR_RADDR_IDX];
588
589 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
590 {
591 uint8_t instrExtension = SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, readIdInstr);
592 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READID].insrOperandPair1 =
593 XSPI_LUT_SEQ(cmdInstr, instrPad, readIdInstr, cmdInstr, instrPad, instrExtension);
594 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READID].insrOperandPair2 =
595 XSPI_LUT_SEQ(raddrInstr, addrPad, xspiMemNorHandle.addrSize, kXSPI_Command_DUMMY_SDR, instrPad, 0x4U);
596 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READID].insrOperandPair3 =
597 XSPI_LUT_SEQ(readInstr, dataPad, 0x08U, kXSPI_Command_STOP, kXSPI_1PAD, 0x0U);
598 }
599 else
600 {
601 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READID].insrOperandPair1 =
602 XSPI_LUT_SEQ(cmdInstr, instrPad, readIdInstr, raddrInstr, addrPad, xspiMemNorHandle.addrSize);
603 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READID].insrOperandPair2 =
604 XSPI_LUT_SEQ(kXSPI_Command_DUMMY_SDR, instrPad, 0x4U, readInstr, dataPad, 0x08U);
605 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READID].insrOperandPair3 =
606 XSPI_LUT_SEQ(kXSPI_Command_STOP, kXSPI_1PAD, 0x0U, 0x0U, 0x0U, 0x0U);
607 }
608 }
609
XSPI_NOR_FillReadDataLutSeq(void)610 static void XSPI_NOR_FillReadDataLutSeq(void)
611 {
612 xspi_lut_instr_t cmdInstr;
613 xspi_lut_instr_t readInstr;
614 xspi_lut_instr_t raddrInstr;
615
616 sfdp_flash_pad_num_t instrPad;
617 uint8_t instrDDR;
618 sfdp_flash_pad_num_t addrPad;
619 uint8_t addrDDR;
620 sfdp_flash_pad_num_t dataPad;
621 uint8_t dataDDR;
622
623 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
624
625 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
626 readInstr = g_xspiCommonInstr[dataDDR][XSPI_INSTR_READ_IDX];
627 raddrInstr = g_xspiCommonInstr[addrDDR][XSPI_INSTR_RADDR_IDX];
628
629 sfdp_read_cmd_info_t readCmdInfo;
630 uint32_t clkFreq = xspiMemNorHandle.clkFreq;
631
632 if (SFDP_CheckDTRSupported(xspiMemNorHandle.ptrSfdpHandle) == true)
633 {
634 clkFreq /= 2UL;
635 }
636
637 SFDP_GetReadCmdInfo(xspiMemNorHandle.ptrSfdpHandle, xspiMemNorHandle.curProtocolType, clkFreq, &readCmdInfo);
638
639 /* @TODO: In case of dummy cycle is updated in ROM, read register to check current dummy cycle value. */
640
641 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
642 {
643 uint8_t instrExtension = SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, readCmdInfo.instruction);
644
645 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READ].insrOperandPair1 =
646 XSPI_LUT_SEQ(cmdInstr, instrPad, readCmdInfo.instruction, cmdInstr, instrPad, instrExtension);
647 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READ].insrOperandPair2 = XSPI_LUT_SEQ(
648 raddrInstr, addrPad, xspiMemNorHandle.addrSize, kXSPI_Command_DUMMY_SDR, instrPad, readCmdInfo.dummyCycle);
649 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READ].insrOperandPair3 =
650 XSPI_LUT_SEQ(readInstr, dataPad, 0x8U, kXSPI_Command_STOP, instrPad, 0U);
651 }
652 else
653 {
654 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READ].insrOperandPair1 =
655 XSPI_LUT_SEQ(cmdInstr, instrPad, readCmdInfo.instruction, raddrInstr, addrPad, xspiMemNorHandle.addrSize);
656 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READ].insrOperandPair2 =
657 XSPI_LUT_SEQ(kXSPI_Command_DUMMY_SDR, instrPad, readCmdInfo.dummyCycle, readInstr, dataPad, 0x8U);
658 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READ].insrOperandPair3 =
659 XSPI_LUT_SEQ(kXSPI_Command_STOP, instrPad, 0U, 0U, 0U, 0U);
660 }
661 }
662
XSPI_NOR_FillChipEraseLutSeq(void)663 static void XSPI_NOR_FillChipEraseLutSeq(void)
664 {
665 xspi_lut_instr_t cmdInstr;
666
667 sfdp_flash_pad_num_t instrPad;
668 uint8_t instrDDR;
669 sfdp_flash_pad_num_t addrPad;
670 uint8_t addrDDR;
671 sfdp_flash_pad_num_t dataPad;
672 uint8_t dataDDR;
673
674 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
675 (void)addrDDR;
676 (void)addrPad;
677 (void)dataPad;
678 (void)dataDDR;
679
680 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
681 sfdp_chip_erase_cmd_info_t chipEraseCmdInfo;
682
683 SFDP_GetChipEraseCmdInfo(xspiMemNorHandle.ptrSfdpHandle, &chipEraseCmdInfo);
684 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
685 {
686 uint8_t instrExtension =
687 SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, chipEraseCmdInfo.instruction);
688
689 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_CHIPERASE].insrOperandPair1 =
690 XSPI_LUT_SEQ(cmdInstr, instrPad, chipEraseCmdInfo.instruction, cmdInstr, instrPad, instrExtension);
691 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_CHIPERASE].insrOperandPair2 =
692 XSPI_LUT_SEQ(kXSPI_Command_STOP, instrPad, 0U, 0U, 0U, 0U);
693 }
694 else
695 {
696 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_CHIPERASE].insrOperandPair1 =
697 XSPI_LUT_SEQ(cmdInstr, instrPad, chipEraseCmdInfo.instruction, kXSPI_Command_STOP, instrPad, 0U);
698 }
699 }
700
XSPI_NOR_FillReadStatusLutSeq(void)701 static void XSPI_NOR_FillReadStatusLutSeq(void)
702 {
703 xspi_lut_instr_t cmdInstr;
704 xspi_lut_instr_t raddrInstr;
705 xspi_lut_instr_t readInstr;
706
707 sfdp_flash_pad_num_t instrPad;
708 uint8_t instrDDR;
709 sfdp_flash_pad_num_t addrPad;
710 uint8_t addrDDR;
711 sfdp_flash_pad_num_t dataPad;
712 uint8_t dataDDR;
713
714 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
715
716 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
717 raddrInstr = g_xspiCommonInstr[addrDDR][XSPI_INSTR_RADDR_IDX];
718 readInstr = g_xspiCommonInstr[dataDDR][XSPI_INSTR_READ_IDX];
719
720 sfdp_read_status_cmd_info_t readStatusCmdInfo;
721 SFDP_GetReadStatusCmdInfo(xspiMemNorHandle.ptrSfdpHandle, xspiMemNorHandle.curProtocolType, &readStatusCmdInfo);
722
723 /* @TODO: In case of dummy cycle is updated. */
724
725 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
726 {
727 uint8_t instrExtension =
728 SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, readStatusCmdInfo.instruction);
729
730 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READSTATUS].insrOperandPair1 =
731 XSPI_LUT_SEQ(cmdInstr, instrPad, readStatusCmdInfo.instruction, cmdInstr, instrPad, instrExtension);
732 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READSTATUS].insrOperandPair2 =
733 XSPI_LUT_SEQ(raddrInstr, addrPad, readStatusCmdInfo.addrSize, kXSPI_Command_DUMMY_SDR, instrPad,
734 readStatusCmdInfo.dummyCycle);
735 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READSTATUS].insrOperandPair3 =
736 XSPI_LUT_SEQ(readInstr, dataPad, 0x4, kXSPI_Command_STOP, instrPad, 0x0U);
737 }
738 else if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_1s1s1s)
739 {
740 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READSTATUS].insrOperandPair1 =
741 XSPI_LUT_SEQ(cmdInstr, instrPad, readStatusCmdInfo.instruction, readInstr, dataPad, 0x8);
742 }
743 else
744 {
745 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READSTATUS].insrOperandPair1 = XSPI_LUT_SEQ(
746 cmdInstr, instrPad, readStatusCmdInfo.instruction, raddrInstr, addrPad, readStatusCmdInfo.addrSize);
747 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READSTATUS].insrOperandPair2 =
748 XSPI_LUT_SEQ(kXSPI_Command_DUMMY_SDR, instrPad, readStatusCmdInfo.dummyCycle, readInstr, dataPad, 0x8);
749 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_READSTATUS].insrOperandPair3 =
750 XSPI_LUT_SEQ(kXSPI_Command_STOP, instrPad, 0x0U, 0x0U, 0x0U, 0x0U);
751 }
752 }
753
XSPI_NOR_FillWriteStatusLutSeq(void)754 static void XSPI_NOR_FillWriteStatusLutSeq(void)
755 {
756 xspi_lut_instr_t cmdInstr;
757 xspi_lut_instr_t writeInstr;
758
759 sfdp_flash_pad_num_t instrPad;
760 uint8_t instrDDR;
761 sfdp_flash_pad_num_t addrPad;
762 uint8_t addrDDR;
763 sfdp_flash_pad_num_t dataPad;
764 uint8_t dataDDR;
765
766 SFDP_DECODE_PROTOCOL_TYPE(xspiMemNorHandle.curProtocolType);
767
768 cmdInstr = g_xspiCommonInstr[instrDDR][XSPI_INSTR_CMD_IDX];
769 writeInstr = g_xspiCommonInstr[dataDDR][XSPI_INSTR_WRITE_IDX];
770
771 (void)addrPad;
772 (void)addrDDR;
773
774 sfdp_write_status_cmd_info_t writeStatusCmdInfo;
775 SFDP_GetWriteStatusCmdInfo(xspiMemNorHandle.ptrSfdpHandle, &writeStatusCmdInfo);
776
777 if (xspiMemNorHandle.curProtocolType == kSFDP_Protocol_8d8d8d)
778 {
779 uint8_t instrExtension =
780 SFDP_GetOctalDTRCmdExtension(xspiMemNorHandle.ptrSfdpHandle, writeStatusCmdInfo.instruction);
781 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_WRITESTATUS].insrOperandPair1 =
782 XSPI_LUT_SEQ(cmdInstr, instrPad, writeStatusCmdInfo.instruction, cmdInstr, instrPad, instrExtension);
783 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_WRITESTATUS].insrOperandPair2 =
784 XSPI_LUT_SEQ(writeInstr, dataPad, 0x4U, kXSPI_Command_STOP, instrPad, 0x0U);
785 }
786 else
787 {
788 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_WRITESTATUS].insrOperandPair1 =
789 XSPI_LUT_SEQ(cmdInstr, instrPad, writeStatusCmdInfo.instruction, writeInstr, dataPad, 0x4U);
790 }
791 }
792
XSPI_NOR_UpdateLut(nor_handle_t * handle,xspi_memory_config_t * ptrUserInputMemConfig)793 static status_t XSPI_NOR_UpdateLut(nor_handle_t *handle, xspi_memory_config_t *ptrUserInputMemConfig)
794 {
795 /* If user input customized LUT use directly, else fill LUT from SFDP. */
796 if (ptrUserInputMemConfig->ptrCustomLut == NULL)
797 {
798 XSPI_NOR_FillReadDataLutSeq();
799 XSPI_NOR_FillReadStatusLutSeq();
800 XSPI_NOR_FillWriteStatusLutSeq();
801 XSPI_NOR_FillWriteEnableLutSeq();
802 XSPI_NOR_FillSectorEraseLutSeq();
803 XSPI_NOR_FillReadIdLutSeq();
804 XSPI_NOR_FillPageProgramLutSeq();
805 XSPI_NOR_FillChipEraseLutSeq();
806 XSPI_NOR_FillBlockEraseLutSeq();
807 }
808 else
809 {
810 memcpy((void *)g_xspiLut, (void *)(ptrUserInputMemConfig->ptrCustomLut), 80U * 4U);
811 }
812
813 XSPI_UpdateLUT(curXSPIBase, 0U, (uint32_t const *)&g_xspiLut, 80U);
814
815 return kStatus_Success;
816 }
817
XSPI_NOR_WriteEnable(nor_handle_t * handle,uint32_t address)818 static status_t XSPI_NOR_WriteEnable(nor_handle_t *handle, uint32_t address)
819 {
820 xspi_transfer_t flashXfer;
821 status_t status = kStatus_InvalidArgument;
822
823 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
824
825 if (address >= s_socXspiAmbaBase[xspiInstanceId])
826 {
827 flashXfer.deviceAddress = address;
828 }
829 else
830 {
831 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId] + address;
832 }
833 flashXfer.cmdType = kXSPI_Command;
834 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
835 flashXfer.data = NULL;
836 flashXfer.dataSize = 0UL;
837 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
838 flashXfer.lockArbitration = false;
839
840 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
841
842 return status;
843 }
844
XSPI_NOR_FindProtocolType(xspi_memory_config_t * ptrXspiMemConfig)845 sfdp_protocol_type_t XSPI_NOR_FindProtocolType(xspi_memory_config_t *ptrXspiMemConfig)
846 {
847 sfdp_protocol_type_t calculatedProtocolType;
848 sfdp_cmd_policy_t policy = kSFDP_CmdPolicy_HighestThroughput;
849 sfdp_ret_type_t ret = kSFDP_RET_Success;
850 sfdp_xspi_profile_opi_cmd_t opiCmd = kSFDP_OPICmd_Erase4K;
851
852 while ((uint8_t)policy < SFDP_CMD_POLICY_COUNT)
853 {
854 calculatedProtocolType = SFDP_GetFlashProtocolType(xspiMemNorHandle.ptrSfdpHandle, policy,
855 (sfdp_flash_pad_num_t)(ptrXspiMemConfig->numPadUsed));
856
857 if (calculatedProtocolType == kSFDP_Protocol_8d8d8d)
858 {
859 do
860 {
861 ret = SFDP_CheckOPICmdSupported(xspiMemNorHandle.ptrSfdpHandle, opiCmd);
862 opiCmd++;
863 } while ((ret == kSFDP_RET_Success) && ((uint8_t)opiCmd < SFDP_XSPI_PROFILE_OPI_CMD_COUNT));
864
865 if (ret != kSFDP_RET_Success)
866 {
867 policy++;
868 }
869 else
870 {
871 break;
872 }
873 }
874 else
875 {
876 break;
877 }
878 }
879
880 return calculatedProtocolType;
881 }
882
XSPI_NOR_QuadEnable(void)883 static status_t XSPI_NOR_QuadEnable(void)
884 {
885 status_t status = kStatus_Success;
886 sfdp_quad_enable_method_t quadEnableMethod = SFDP_GetQuadEnableMethod(xspiMemNorHandle.ptrSfdpHandle);
887
888 switch (quadEnableMethod)
889 {
890 case kSFDP_QuadEnableNotSupported:
891 {
892 /*Device doest not have a QE bit, device detects 1s-1s-4s and 1s-4s-4s reads based on instruction. */
893 break;
894 }
895 case kSFDP_QuadEnableMethod1:
896 {
897 break;
898 }
899 case kSFDP_QuadEnableMethod2:
900 {
901 break;
902 }
903 case kSFDP_QuadEnableMethod3:
904 {
905 break;
906 }
907 case kSFDP_QuadEnableMethod4:
908 {
909 break;
910 }
911 case kSFDP_QuadEnableMethod5:
912 {
913 break;
914 }
915 case kSFDP_QuadEnableMethod6:
916 {
917 break;
918 }
919 default:
920 {
921 assert(false);
922 }
923 }
924
925 return status;
926 }
927
XSPI_NOR_EnterQuadSSRMode(void)928 static status_t XSPI_NOR_EnterQuadSSRMode(void)
929 {
930 status_t status = kStatus_Success;
931 sfdp_4s4s4s_mode_enable_method_t enableMethod = SFDP_Get4s4s4sModeEnableMethod(xspiMemNorHandle.ptrSfdpHandle);
932 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
933 xspi_transfer_t flashXfer;
934
935 switch (enableMethod)
936 {
937 case kSFDP_4s4s4sModeEnableMethod0:
938 {
939 XSPI_NOR_QuadEnable();
940
941 memset((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, 0UL, sizeof(lut_seq_entry_t));
942 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1 =
943 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_1PAD, 0x38U, kXSPI_Command_STOP, kXSPI_1PAD, 0U);
944
945 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
946 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
947
948 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
949 flashXfer.cmdType = kXSPI_Command;
950 flashXfer.data = NULL;
951 flashXfer.dataSize = 0U;
952 flashXfer.lockArbitration = false;
953 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
954 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
955
956 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
957 if (status != kStatus_Success)
958 {
959 return status;
960 }
961 break;
962 }
963 case kSFDP_4s4s4sModeEnableMethod1:
964 {
965 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1 =
966 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_1PAD, 0x38U, kXSPI_Command_STOP, kXSPI_1PAD, 0U);
967
968 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
969 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
970
971 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
972 flashXfer.cmdType = kXSPI_Command;
973 flashXfer.data = NULL;
974 flashXfer.dataSize = 0U;
975 flashXfer.lockArbitration = false;
976 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
977 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
978
979 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
980 if (status != kStatus_Success)
981 {
982 return status;
983 }
984 break;
985 }
986 case kSFDP_4s4s4sModeEnableMethod2:
987 {
988 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1 =
989 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_1PAD, 0x35U, kXSPI_Command_STOP, kXSPI_1PAD, 0U);
990
991 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
992 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
993
994 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
995 flashXfer.cmdType = kXSPI_Command;
996 flashXfer.data = NULL;
997 flashXfer.dataSize = 0U;
998 flashXfer.lockArbitration = false;
999 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
1000 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
1001
1002 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
1003 if (status != kStatus_Success)
1004 {
1005 return status;
1006 }
1007 break;
1008 }
1009 case kSFDP_4s4s4sModeEnableMethod3:
1010 {
1011 /*!< Read configuration using instruction 65h followed by address 800003h,
1012 set bit 6, write configuration using instruction 71h followed by
1013 address 800003h. */
1014 break;
1015 }
1016 case kSFDP_4s4s4sModeEnableMethod4:
1017 {
1018 /*!< Read volatile enhanced configuration using instruction 65h, no
1019 address is required, set bit 7 to 1, write volatile enhanced
1020 configuration using instruction 61h, no address is required. */
1021 break;
1022 }
1023 }
1024
1025 return status;
1026 }
1027
XSPI_NOR_EnterQuadDDRMode(void)1028 static status_t XSPI_NOR_EnterQuadDDRMode(void)
1029 {
1030 status_t status = kStatus_Success;
1031 sfdp_4s4d4d_entry_seq_t quadEntrySeq;
1032
1033 if (SFDP_Get4s4d4dEntrySeq(xspiMemNorHandle.ptrSfdpHandle, &quadEntrySeq) != kSFDP_RET_Success)
1034 {
1035 return kStatus_Fail;
1036 }
1037
1038 uint8_t seqLength = 0U;
1039 uint32_t i = 0U;
1040 lut_seq_instr_operand_t altSeq[10];
1041 xspi_transfer_t flashXfer;
1042 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1043 uint32_t delayCount = 0UL;
1044
1045 sfdp_entry_seq_format_t *ptrSeq = &(quadEntrySeq.seq1);
1046 for (uint8_t seqId = 0U; seqId < 4U; seqId++)
1047 {
1048 if (ptrSeq->seqStruct.length != 0U)
1049 {
1050 seqLength = ptrSeq->seqStruct.length;
1051 memset(altSeq, 0UL, sizeof(altSeq));
1052 for (i = 0U; i < seqLength; i++)
1053 {
1054 altSeq[i].operand = SFDP_GET_SEQ_CMD((*ptrSeq), i + 1U);
1055 altSeq[i].instr = kXSPI_Command_SDR;
1056 altSeq[i].padNum = kXSPI_1PAD;
1057 }
1058 memset((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, 0UL, sizeof(lut_seq_entry_t));
1059 memcpy((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, (void *)&altSeq[0],
1060 seqLength * sizeof(altSeq));
1061
1062 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
1063 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
1064
1065 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
1066 flashXfer.cmdType = kXSPI_Command;
1067 flashXfer.data = NULL;
1068 flashXfer.dataSize = 0U;
1069 flashXfer.lockArbitration = false;
1070 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
1071 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
1072
1073 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
1074 __ISB();
1075 __DSB();
1076 for (delayCount = 0U; delayCount < 2000U; delayCount++)
1077 {
1078 /* Delay to make sure command effect. */
1079 __NOP();
1080 }
1081 }
1082 if (status != kStatus_Success)
1083 {
1084 break;
1085 }
1086 ptrSeq++;
1087 }
1088
1089 return status;
1090 }
1091
XSPI_NOR_OctalEnable(void)1092 static status_t XSPI_NOR_OctalEnable(void)
1093 {
1094 status_t status = kStatus_Success;
1095 sfdp_octal_enable_method_t octalEnableMethod = SFDP_GetOctalEnableMethod(xspiMemNorHandle.ptrSfdpHandle);
1096
1097 switch (octalEnableMethod)
1098 {
1099 case kSFDP_OctalEnableNotSupported:
1100 {
1101 /* Not supported. */
1102 break;
1103 }
1104 case kSFDP_OctalEnableMethod1:
1105 {
1106 /*!< Octal enable is bit 3 of status register, it is set via write status register2
1107 instruction 31h with one data byte where bit 3 is one, it is cleared via write
1108 register instruction 3Eh with one data byte where bit 3 is zero, the status
1109 register 2 is read using instruction 65h with address byte 02h and one dummy
1110 cycle. */
1111 break;
1112 }
1113 default:
1114 {
1115 assert(false);
1116 }
1117 }
1118
1119 return status;
1120 }
1121
XSPI_NOR_EnterOctalSSRMode(void)1122 static status_t XSPI_NOR_EnterOctalSSRMode(void)
1123 {
1124 status_t status = kStatus_Success;
1125 sfdp_8s8s8s_mode_enable_method_t enableMethod = SFDP_Get8s8s8sModeEnableMethod(xspiMemNorHandle.ptrSfdpHandle);
1126 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1127 xspi_transfer_t flashXfer;
1128
1129 switch (enableMethod)
1130 {
1131 case kSFDP_8s8s8sModeEnableMethod0:
1132 {
1133 memset((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, 0UL, sizeof(lut_seq_entry_t));
1134 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1 =
1135 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_1PAD, 0x06U, kXSPI_Command_SDR, kXSPI_1PAD, 0xE8U);
1136
1137 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
1138 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
1139
1140 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
1141 flashXfer.cmdType = kXSPI_Command;
1142 flashXfer.data = NULL;
1143 flashXfer.dataSize = 0U;
1144 flashXfer.lockArbitration = false;
1145 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
1146 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
1147
1148 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
1149 break;
1150 }
1151 case kSFDP_8s8s8sModeEnableMethod1:
1152 {
1153 memset((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, 0UL, sizeof(lut_seq_entry_t));
1154 g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1 =
1155 XSPI_LUT_SEQ(kXSPI_Command_SDR, kXSPI_1PAD, 0x06U, kXSPI_Command_SDR, kXSPI_1PAD, 0x72U);
1156
1157 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
1158 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
1159
1160 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
1161 flashXfer.cmdType = kXSPI_Command;
1162 flashXfer.data = NULL;
1163 flashXfer.dataSize = 0U;
1164 flashXfer.lockArbitration = false;
1165 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
1166 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
1167
1168 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
1169 break;
1170 }
1171 default:
1172 {
1173 assert(false);
1174 }
1175 }
1176
1177 return status;
1178 }
1179
XSPI_NOR_EnterOctalDDRMode(void)1180 static status_t XSPI_NOR_EnterOctalDDRMode(void)
1181 {
1182 sfdp_8d8d8d_entry_seq_t octalEntrySeq;
1183 status_t status = kStatus_Success;
1184
1185 if (SFDP_Get8d8d8dEntrySeq(xspiMemNorHandle.ptrSfdpHandle, &octalEntrySeq) != kSFDP_RET_Success)
1186 {
1187 return kStatus_Fail;
1188 }
1189 uint8_t seqLength = 0U;
1190 uint32_t i = 0U;
1191 lut_seq_instr_operand_t altSeq[10];
1192 xspi_transfer_t flashXfer;
1193 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1194 uint32_t delayCount = 0UL;
1195
1196 sfdp_entry_seq_format_t *ptrSeq = &(octalEntrySeq.seq1);
1197 for (uint8_t seqId = 0U; seqId < 4U; seqId++)
1198 {
1199 if (ptrSeq->seqStruct.length != 0U)
1200 {
1201 seqLength = ptrSeq->seqStruct.length;
1202 memset(altSeq, 0UL, sizeof(altSeq));
1203 for (i = 0U; i < seqLength; i++)
1204 {
1205 altSeq[i].operand = SFDP_GET_SEQ_CMD((*ptrSeq), i + 1U);
1206 altSeq[i].instr = kXSPI_Command_SDR;
1207 altSeq[i].padNum = kXSPI_1PAD;
1208 }
1209 memset((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, 0UL, sizeof(lut_seq_entry_t));
1210 memcpy((void *)&g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1, (void *)&altSeq[0], sizeof(altSeq));
1211
1212 XSPI_UpdateLUT(curXSPIBase, NOR_CMD_LUT_SEQ_IDX_ALT * 5U,
1213 &(g_xspiLut[NOR_CMD_LUT_SEQ_IDX_ALT].insrOperandPair1), 5U);
1214
1215 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
1216 flashXfer.cmdType = kXSPI_Command;
1217 flashXfer.data = NULL;
1218 flashXfer.dataSize = 0U;
1219 flashXfer.lockArbitration = false;
1220 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ALT;
1221 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
1222
1223 status = XSPI_TransferBlocking(curXSPIBase, &flashXfer);
1224 __ISB();
1225 __DSB();
1226 for (delayCount = 0U; delayCount < 2000U; delayCount++)
1227 {
1228 /* Delay to make sure command effect. */
1229 __NOP();
1230 }
1231 }
1232 if (status != kStatus_Success)
1233 {
1234 break;
1235 }
1236 ptrSeq++;
1237 }
1238
1239 return status;
1240 }
1241
Nor_Flash_Init(nor_config_t * config,nor_handle_t * handle)1242 status_t Nor_Flash_Init(nor_config_t *config, nor_handle_t *handle)
1243 {
1244 assert(config != NULL);
1245
1246 xspi_memory_config_t xspiNorMemConfig = *(xspi_memory_config_t *)(config->memControlConfig);
1247
1248 xspiMemNorHandle.selectedTg = xspiNorMemConfig.tgId;
1249 xspiMemNorHandle.clkFreq = xspiNorMemConfig.xspiRootClk;
1250
1251 xspi_ahb_write_config_t xspiAhbWriteConfig;
1252 xspi_ahb_access_config_t xspiAhbAccessConfig;
1253 xspi_ip_access_config_t xspiIpAccessConfig;
1254 xspi_config_t xspiConfig;
1255
1256 curXSPIBase = (XSPI_Type *)(uint32_t)(config->driverBaseAddr);
1257 XSPI_ResetSfmAndAhbDomain(curXSPIBase);
1258
1259 XSPI_UpdateByteOrder(curXSPIBase, kXSPI_32BitLE);
1260
1261 sfdp_handle_t sfdpHandle;
1262 (void)memset((void *)&sfdpHandle, 0UL, sizeof(sfdpHandle));
1263
1264 xspiMemNorHandle.ptrSfdpHandle = &sfdpHandle;
1265
1266 xspiConfig.enableDoze = xspiNorMemConfig.enableXspiDoze;
1267 xspiConfig.ptrAhbAccessConfig = &xspiAhbAccessConfig;
1268 xspiConfig.ptrIpAccessConfig = &xspiIpAccessConfig;
1269 XSPI_GetDefaultConfig(&xspiConfig);
1270
1271 if (xspiNorMemConfig.ptrXspiNorAhbAccessConfig != NULL)
1272 {
1273 /* In case of user customized AHB access configurations, overwrite the default settings. */
1274 xspiAhbAccessConfig.buffer[0] = xspiNorMemConfig.ptrXspiNorAhbAccessConfig->ahbBuffer0Config;
1275 xspiAhbAccessConfig.buffer[1] = xspiNorMemConfig.ptrXspiNorAhbAccessConfig->ahbBuffer1Config;
1276 xspiAhbAccessConfig.buffer[2] = xspiNorMemConfig.ptrXspiNorAhbAccessConfig->ahbBuffer2Config;
1277 xspiAhbAccessConfig.buffer[3] = xspiNorMemConfig.ptrXspiNorAhbAccessConfig->ahbBuffer3Config;
1278 xspiAhbAccessConfig.enableAHBPrefetch = xspiNorMemConfig.ptrXspiNorAhbAccessConfig->enablePrefetch;
1279 if (xspiNorMemConfig.ptrXspiNorAhbAccessConfig->enableAhbWrite)
1280 {
1281 xspiAhbAccessConfig.ptrAhbWriteConfig = &xspiAhbWriteConfig;
1282 }
1283 else
1284 {
1285 xspiAhbAccessConfig.ptrAhbWriteConfig = NULL;
1286 }
1287 }
1288
1289 xspiAhbAccessConfig.ahbAlignment = kXSPI_AhbAlignmentNoLimit;
1290 xspiAhbAccessConfig.ahbErrorPayload.highPayload = 0x5A5A5A5AUL; /* hard code in component. */
1291 xspiAhbAccessConfig.ahbErrorPayload.lowPayload = 0x5A5A5A5AUL; /* hard code in component. */
1292 xspiAhbAccessConfig.ahbSplitSize = kXSPI_AhbSplitSizeDisabled;
1293 xspiAhbAccessConfig.ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ;
1294
1295 xspiAhbAccessConfig.enableAHBBufferWriteFlush = true;
1296
1297 if (xspiNorMemConfig.ptrXspiNorIPAccessConfig != NULL)
1298 {
1299 /* In case of user customized IP access configurations, overwrite the default settings. */
1300 xspiIpAccessConfig.ipAccessTimeoutValue = xspiNorMemConfig.ptrXspiNorIPAccessConfig->ipAccessTimeoutValue;
1301 xspiIpAccessConfig.ptrSfpFradConfig = xspiNorMemConfig.ptrXspiNorIPAccessConfig->ptrSfpFradConfig;
1302 xspiIpAccessConfig.ptrSfpMdadConfig = xspiNorMemConfig.ptrXspiNorIPAccessConfig->ptrSfpMdadConfig;
1303 xspiIpAccessConfig.sfpArbitrationLockTimeoutValue =
1304 xspiNorMemConfig.ptrXspiNorIPAccessConfig->sfpArbitrationLockTimeoutValue;
1305 }
1306
1307 /* initialize host controller. */
1308 XSPI_Init(curXSPIBase, &xspiConfig);
1309
1310 if (XSPI_NOR_ProbeNorFlashSfdpHeader() != kStatus_Success)
1311 {
1312 return kStatus_Fail;
1313 }
1314
1315 if (SFDP_ReadAllSupportedTable(&sfdpHandle) != kSFDP_RET_Success)
1316 {
1317 return kStatus_Fail;
1318 }
1319
1320 if ((SFDP_GetAddressBytes(&sfdpHandle) != kSFDP_AddrMode_3ByteOnly) && (xspiMemNorHandle.addrSize != 32U))
1321 {
1322 XSPI_NOR_Enter4ByteMode();
1323 xspiMemNorHandle.addrSize = 32U;
1324 }
1325
1326 sfdp_protocol_type_t targetProtocolType = XSPI_NOR_FindProtocolType(&xspiNorMemConfig);
1327
1328 if ((targetProtocolType >= kSFDP_Protocol_1s1s4s) && (targetProtocolType <= kSFDP_Protocol_4s4d4d))
1329 {
1330 if (targetProtocolType <= kSFDP_Protocol_1s4d4d)
1331 {
1332 if (XSPI_NOR_QuadEnable() != kStatus_Success)
1333 {
1334 return kStatus_Fail;
1335 }
1336 }
1337 else if (targetProtocolType == kSFDP_Protocol_4s4s4s)
1338 {
1339 if (XSPI_NOR_EnterQuadSSRMode() != kStatus_Success)
1340 {
1341 return kStatus_Fail;
1342 }
1343 }
1344 else
1345 {
1346 if (XSPI_NOR_EnterQuadDDRMode() != kStatus_Success)
1347 {
1348 return kStatus_Fail;
1349 }
1350 }
1351 }
1352 if (targetProtocolType >= kSFDP_Protocol_1s1s8s)
1353 {
1354 if (targetProtocolType <= kSFDP_Protocol_1s8d8d)
1355 {
1356 if (XSPI_NOR_OctalEnable() != kStatus_Success)
1357 {
1358 return kStatus_Fail;
1359 }
1360 }
1361 else if (targetProtocolType == kSFDP_Protocol_8s8s8s)
1362 {
1363 if (XSPI_NOR_EnterOctalSSRMode() != kStatus_Success)
1364 {
1365 return kStatus_Fail;
1366 }
1367 }
1368 else
1369 {
1370 if (XSPI_NOR_EnterOctalDDRMode() != kStatus_Success)
1371 {
1372 return kStatus_Fail;
1373 }
1374 }
1375 }
1376
1377 xspiMemNorHandle.curProtocolType = targetProtocolType;
1378
1379 if (XSPI_NOR_SetNorFlashDeviceConfig(&xspiNorMemConfig) != kStatus_Success)
1380 {
1381 return kStatus_Fail;
1382 }
1383
1384 if (XSPI_NOR_UpdateLut(handle, &xspiNorMemConfig) != kStatus_Success)
1385 {
1386 return kStatus_Fail;
1387 }
1388 /* Update handle for other interfaces. */
1389 handle->driverBaseAddr = config->driverBaseAddr;
1390 handle->deviceSpecific = (void *)(uint32_t)(&xspiMemNorHandle);
1391 handle->bytesInSectorSize = xspiMemNorHandle.sectorSizeInByte;
1392 handle->bytesInMemorySize = xspiMemNorHandle.memSizeInByte;
1393 handle->bytesInPageSize = SFDP_GetPageSize(&sfdpHandle);
1394
1395 return kStatus_Success;
1396 }
1397
Nor_Flash_Read(nor_handle_t * handle,uint32_t address,uint8_t * buffer,uint32_t length)1398 status_t Nor_Flash_Read(nor_handle_t *handle, uint32_t address, uint8_t *buffer, uint32_t length)
1399 {
1400 assert(handle != NULL);
1401 assert(buffer != NULL);
1402
1403 xspi_transfer_t flashXfer;
1404 status_t status = kStatus_Success;
1405 xspi_mem_nor_handle_t *ptrXspiMemNorHandle = (xspi_mem_nor_handle_t *)(uint32_t)(handle->deviceSpecific);
1406
1407 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1408
1409 if (address >= s_socXspiAmbaBase[xspiInstanceId])
1410 {
1411 flashXfer.deviceAddress = address;
1412 }
1413 else
1414 {
1415 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId] + address;
1416 }
1417 flashXfer.cmdType = kXSPI_Read;
1418 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ; /* Hard code as 0, the first sequence of LUT is used to read
1419 data from Flash device. */
1420 flashXfer.data = (uint32_t *)(void *)buffer;
1421 flashXfer.dataSize = length;
1422 flashXfer.targetGroup = ptrXspiMemNorHandle->selectedTg; /* Target group selection is from application. */
1423 flashXfer.lockArbitration = false;
1424
1425 status = XSPI_TransferBlocking((XSPI_Type *)handle->driverBaseAddr, &flashXfer);
1426
1427 return status;
1428 }
1429
Nor_Flash_Page_Program(nor_handle_t * handle,uint32_t address,uint8_t * buffer)1430 status_t Nor_Flash_Page_Program(nor_handle_t *handle, uint32_t address, uint8_t *buffer)
1431 {
1432 assert(handle != NULL);
1433 assert(buffer != NULL);
1434
1435 xspi_transfer_t flashXfer;
1436 status_t status = kStatus_Success;
1437 bool isBusy = true;
1438
1439 /* Write Enable. */
1440 if (XSPI_NOR_WriteEnable(handle, address) != kStatus_Success)
1441 {
1442 return kStatus_Fail;
1443 }
1444
1445 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1446
1447 if (address >= s_socXspiAmbaBase[xspiInstanceId])
1448 {
1449 flashXfer.deviceAddress = address;
1450 }
1451 else
1452 {
1453 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId] + address;
1454 }
1455 flashXfer.cmdType = kXSPI_Write;
1456 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
1457 flashXfer.data = (uint32_t *)(void *)buffer;
1458 flashXfer.dataSize = handle->bytesInPageSize;
1459 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
1460 flashXfer.lockArbitration = true;
1461
1462 status = XSPI_TransferBlocking((XSPI_Type *)handle->driverBaseAddr, &flashXfer);
1463
1464 if (status == kStatus_Success)
1465 {
1466 /* Loop until WIP is cleared */
1467 do
1468 {
1469 (void)Nor_Flash_Is_Busy(handle, &isBusy);
1470 } while (isBusy == true);
1471 }
1472
1473 return status;
1474 }
1475
Nor_Flash_Program(nor_handle_t * handle,uint32_t address,uint8_t * buffer,uint32_t length)1476 status_t Nor_Flash_Program(nor_handle_t *handle, uint32_t address, uint8_t *buffer, uint32_t length)
1477 {
1478 assert(handle != NULL);
1479 assert(buffer != NULL);
1480
1481 assert(handle != NULL);
1482 assert(buffer != NULL);
1483 uint32_t startAddress = address;
1484 status_t status = kStatus_Success;
1485
1486 for (uint32_t i = 0x00U; i <= (length / handle->bytesInPageSize); i++)
1487 {
1488 status = Nor_Flash_Page_Program(handle, startAddress, buffer);
1489 /* Avoid buffer overflow. */
1490 if (length >= handle->bytesInPageSize)
1491 {
1492 buffer += handle->bytesInPageSize;
1493 startAddress += handle->bytesInPageSize;
1494 }
1495 }
1496
1497 return status;
1498 }
1499
Nor_Flash_Erase_Sector(nor_handle_t * handle,uint32_t address)1500 status_t Nor_Flash_Erase_Sector(nor_handle_t *handle, uint32_t address)
1501 {
1502 assert(handle != NULL);
1503
1504 xspi_transfer_t flashXfer;
1505 bool isBusy = true;
1506 status_t status = kStatus_Success;
1507
1508 /* Write Enable. */
1509 if (XSPI_NOR_WriteEnable(handle, address) != kStatus_Success)
1510 {
1511 return kStatus_Fail;
1512 }
1513
1514 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1515
1516 if (address >= s_socXspiAmbaBase[xspiInstanceId])
1517 {
1518 flashXfer.deviceAddress = address;
1519 }
1520 else
1521 {
1522 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId] + address;
1523 }
1524 flashXfer.cmdType = kXSPI_Command;
1525 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
1526 flashXfer.data = NULL;
1527 flashXfer.dataSize = 0UL;
1528 flashXfer.targetGroup = xspiMemNorHandle.selectedTg;
1529 flashXfer.lockArbitration = false;
1530
1531 status = XSPI_TransferBlocking((XSPI_Type *)handle->driverBaseAddr, &flashXfer);
1532
1533 if (status == kStatus_Success)
1534 {
1535 /* Loop until WIP is cleared */
1536 do
1537 {
1538 (void)Nor_Flash_Is_Busy(handle, &isBusy);
1539 } while (isBusy == true);
1540 }
1541
1542 return status;
1543 }
1544
Nor_Flash_Erase_Block(nor_handle_t * handle,uint32_t address)1545 status_t Nor_Flash_Erase_Block(nor_handle_t *handle, uint32_t address)
1546 {
1547 assert(handle != NULL);
1548
1549 xspi_transfer_t flashXfer;
1550 status_t status = kStatus_Success;
1551 xspi_mem_nor_handle_t *ptrXspiMemNorHandle = (xspi_mem_nor_handle_t *)(uint32_t)(handle->deviceSpecific);
1552 bool isBusy = false;
1553
1554 /* Write Enable. */
1555 if (XSPI_NOR_WriteEnable(handle, address) != kStatus_Success)
1556 {
1557 return kStatus_Fail;
1558 }
1559
1560 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1561
1562 if (address >= s_socXspiAmbaBase[xspiInstanceId])
1563 {
1564 flashXfer.deviceAddress = address;
1565 }
1566 else
1567 {
1568 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId] + address;
1569 }
1570 flashXfer.cmdType = kXSPI_Command;
1571 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK;
1572 flashXfer.data = NULL;
1573 flashXfer.dataSize = 0UL;
1574 flashXfer.targetGroup = ptrXspiMemNorHandle->selectedTg;
1575 flashXfer.lockArbitration = false;
1576
1577 status = XSPI_TransferBlocking((XSPI_Type *)handle->driverBaseAddr, &flashXfer);
1578
1579 if (status == kStatus_Success)
1580 {
1581 /* Loop until WIP is cleared */
1582 do
1583 {
1584 (void)Nor_Flash_Is_Busy(handle, &isBusy);
1585 } while (isBusy == false);
1586 }
1587
1588 return status;
1589 }
1590
Nor_Flash_Erase(nor_handle_t * handle,uint32_t address,uint32_t size_Byte)1591 status_t Nor_Flash_Erase(nor_handle_t *handle, uint32_t address, uint32_t size_Byte)
1592 {
1593 assert(handle != NULL);
1594 assert(size_Byte > 0x00U);
1595 uint32_t startAddress = address;
1596 status_t status = kStatus_Success;
1597
1598 for (uint32_t i = 0x00U; i <= (size_Byte / handle->bytesInSectorSize); i++)
1599 {
1600 status = Nor_Flash_Erase_Sector(handle, startAddress);
1601 startAddress += handle->bytesInSectorSize;
1602 }
1603
1604 return status;
1605 }
1606
Nor_Flash_Erase_Chip(nor_handle_t * handle)1607 status_t Nor_Flash_Erase_Chip(nor_handle_t *handle)
1608 {
1609 assert(handle != NULL);
1610
1611 xspi_transfer_t flashXfer;
1612 status_t status = kStatus_Success;
1613 xspi_mem_nor_handle_t *ptrXspiMemNorHandle = (xspi_mem_nor_handle_t *)(uint32_t)(handle->deviceSpecific);
1614 bool isBusy = false;
1615
1616 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1617
1618 /* Write Enable. */
1619 if (XSPI_NOR_WriteEnable(handle, s_socXspiAmbaBase[xspiInstanceId]) != kStatus_Success)
1620 {
1621 return kStatus_Fail;
1622 }
1623
1624 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
1625 flashXfer.cmdType = kXSPI_Command;
1626 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_CHIPERASE;
1627 flashXfer.data = NULL;
1628 flashXfer.dataSize = 0UL;
1629 flashXfer.targetGroup = ptrXspiMemNorHandle->selectedTg;
1630 flashXfer.lockArbitration = false;
1631
1632 status = XSPI_TransferBlocking((XSPI_Type *)handle->driverBaseAddr, &flashXfer);
1633
1634 if (status == kStatus_Success)
1635 {
1636 /* Loop until WIP is cleared */
1637 do
1638 {
1639 (void)Nor_Flash_Is_Busy(handle, &isBusy);
1640 } while (isBusy == false);
1641 }
1642
1643 return status;
1644 }
1645
Nor_Flash_Is_Busy(nor_handle_t * handle,bool * isBusy)1646 status_t Nor_Flash_Is_Busy(nor_handle_t *handle, bool *isBusy)
1647 {
1648 assert(handle != NULL);
1649
1650 xspi_transfer_t flashXfer;
1651 status_t status = kStatus_Success;
1652 xspi_mem_nor_handle_t *ptrXspiMemNorHandle = (xspi_mem_nor_handle_t *)(uint32_t)(handle->deviceSpecific);
1653 uint32_t readBuffer = 0UL;
1654 bool wip = true;
1655
1656 uint32_t xspiInstanceId = XSPI_GetInstance(curXSPIBase);
1657
1658 flashXfer.deviceAddress = s_socXspiAmbaBase[xspiInstanceId];
1659 flashXfer.cmdType = kXSPI_Read;
1660 flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS;
1661 flashXfer.data = &readBuffer;
1662 flashXfer.dataSize = 2UL;
1663 flashXfer.targetGroup = ptrXspiMemNorHandle->selectedTg;
1664 flashXfer.lockArbitration = false;
1665
1666 status = XSPI_TransferBlocking((XSPI_Type *)handle->driverBaseAddr, &flashXfer);
1667
1668 if (status == kStatus_Success)
1669 {
1670 /* Check if WIP is cleared. */
1671 if (ptrXspiMemNorHandle->norFlashStatusRegInfo.value1Expired)
1672 {
1673 wip =
1674 (((1U << ptrXspiMemNorHandle->norFlashStatusRegInfo.wipLocation) & readBuffer) != 0x0U) ? false : true;
1675 }
1676 else
1677 {
1678 wip =
1679 (((1U << ptrXspiMemNorHandle->norFlashStatusRegInfo.wipLocation) & readBuffer) != 0x0U) ? true : false;
1680 }
1681
1682 *isBusy = wip;
1683 }
1684
1685 return status;
1686 }
1687
Nor_Flash_DeInit(nor_handle_t * handle)1688 status_t Nor_Flash_DeInit(nor_handle_t *handle)
1689 {
1690 XSPI_Deinit((XSPI_Type *)handle->driverBaseAddr);
1691
1692 return kStatus_Success;
1693 }
1694
