1 // Copyright 2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "esp_system.h"
16 #include "esp_rom_sys.h"
17 #include "esp_private/system_internal.h"
18 #include "soc/rtc_periph.h"
19 #include "esp32s3/rom/rtc.h"
20
21 static void esp_reset_reason_clear_hint(void);
22
23 static esp_reset_reason_t s_reset_reason;
24
get_reset_reason(soc_reset_reason_t rtc_reset_reason,esp_reset_reason_t reset_reason_hint)25 static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
26 {
27 switch (rtc_reset_reason) {
28 case RESET_REASON_CHIP_POWER_ON:
29 return ESP_RST_POWERON;
30
31 case RESET_REASON_CPU0_SW:
32 case RESET_REASON_CORE_SW:
33 if (reset_reason_hint == ESP_RST_PANIC ||
34 reset_reason_hint == ESP_RST_BROWNOUT ||
35 reset_reason_hint == ESP_RST_TASK_WDT ||
36 reset_reason_hint == ESP_RST_INT_WDT) {
37 return reset_reason_hint;
38 }
39 return ESP_RST_SW;
40
41 case RESET_REASON_CORE_DEEP_SLEEP:
42 return ESP_RST_DEEPSLEEP;
43
44 case RESET_REASON_CORE_MWDT0:
45 return ESP_RST_TASK_WDT;
46
47 case RESET_REASON_CORE_MWDT1:
48 return ESP_RST_INT_WDT;
49
50 case RESET_REASON_CORE_RTC_WDT:
51 case RESET_REASON_SYS_RTC_WDT:
52 case RESET_REASON_SYS_SUPER_WDT:
53 case RESET_REASON_CPU0_RTC_WDT:
54 case RESET_REASON_CPU0_MWDT0:
55 case RESET_REASON_CPU0_MWDT1:
56 return ESP_RST_WDT;
57
58 case RESET_REASON_SYS_BROWN_OUT:
59 return ESP_RST_BROWNOUT;
60
61 default:
62 return ESP_RST_UNKNOWN;
63 }
64 }
65
esp_reset_reason_init(void)66 void esp_reset_reason_init(void)
67 {
68 esp_reset_reason_t hint = esp_reset_reason_get_hint();
69 s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
70 if (hint != ESP_RST_UNKNOWN) {
71 esp_reset_reason_clear_hint();
72 }
73 }
74
esp_reset_reason(void)75 esp_reset_reason_t esp_reset_reason(void)
76 {
77 return s_reset_reason;
78 }
79
80 /* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG,
81 * a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
82 * deep sleep wake stub entry address and for reset reason hint, since wake stub
83 * is only used for deep sleep reset, and in this case the reason provided by
84 * esp_rom_get_reset_reason is unambiguous.
85 *
86 * In addition to that, MSB is set to 1, which doesn't happen when
87 * RTC_CNTL_STORE6_REG contains deep sleep wake stub address.
88 */
89
90 #define RST_REASON_BIT 0x80000000
91 #define RST_REASON_MASK 0x7FFF
92 #define RST_REASON_SHIFT 16
93
94 /* in IRAM, can be called from panic handler */
esp_reset_reason_set_hint(esp_reset_reason_t hint)95 void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
96 {
97 assert((hint & (~RST_REASON_MASK)) == 0);
98 uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
99 REG_WRITE(RTC_RESET_CAUSE_REG, val);
100 }
101
102 /* in IRAM, can be called from panic handler */
esp_reset_reason_get_hint(void)103 esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void)
104 {
105 uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
106 uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;
107 uint32_t low = reset_reason_hint & RST_REASON_MASK;
108 if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) {
109 return ESP_RST_UNKNOWN;
110 }
111 return (esp_reset_reason_t) low;
112 }
esp_reset_reason_clear_hint(void)113 static void esp_reset_reason_clear_hint(void)
114 {
115 REG_WRITE(RTC_RESET_CAUSE_REG, 0);
116 }
117
