1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <sys/cdefs.h>
9 #if !defined(__ZEPHYR__)
10 #include <sys/time.h>
11 #endif
12 #include <sys/param.h>
13
14 #if !defined(__ZEPHYR__)
15 #include "sdkconfig.h"
16 #endif
17
18 #include "esp_attr.h"
19 #include "esp_log.h"
20 #include "esp32s2/clk.h"
21 #include "esp_clk_internal.h"
22 #include "esp_rom_uart.h"
23 #include "esp_rom_sys.h"
24 #include "soc/system_reg.h"
25 #include "soc/dport_access.h"
26 #include "soc/soc.h"
27 #include "soc/rtc.h"
28 #include "soc/rtc_periph.h"
29 #include "soc/i2s_reg.h"
30 #include "hal/cpu_hal.h"
31 #include "hal/wdt_hal.h"
32 #include "driver/periph_ctrl.h"
33 #include "bootloader_clock.h"
34 #include "soc/syscon_reg.h"
35 #include "hal/clk_gate_ll.h"
36
37 #if defined(__ZEPHYR__)
38 #include "stubs.h"
39 #endif /* defined(__ZEPHYR__) */
40
41 static const char *TAG = "clk";
42
43 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
44 * Larger values increase startup delay. Smaller values may cause false positive
45 * detection (i.e. oscillator runs for a few cycles and then stops).
46 */
47 #define SLOW_CLK_CAL_CYCLES CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES
48
49 #ifdef CONFIG_ESP32S2_RTC_XTAL_CAL_RETRY
50 #define RTC_XTAL_CAL_RETRY CONFIG_ESP32S2_RTC_XTAL_CAL_RETRY
51 #else
52 #define RTC_XTAL_CAL_RETRY 1
53 #endif
54
55 /* Lower threshold for a reasonably-looking calibration value for a 32k XTAL.
56 * The ideal value (assuming 32768 Hz frequency) is 1000000/32768*(2**19) = 16*10^6.
57 */
58 #define MIN_32K_XTAL_CAL_VAL 15000000L
59
60 /* Indicates that this 32k oscillator gets input from external oscillator, rather
61 * than a crystal.
62 */
63 #define EXT_OSC_FLAG BIT(3)
64
65 /* This is almost the same as rtc_slow_freq_t, except that we define
66 * an extra enum member for the external 32k oscillator.
67 * For convenience, lower 2 bits should correspond to rtc_slow_freq_t values.
68 */
69 typedef enum {
70 SLOW_CLK_RTC = RTC_SLOW_FREQ_RTC, //!< Internal 90 kHz RC oscillator
71 SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL
72 SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256
73 SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
74 } slow_clk_sel_t;
75
76 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
77
esp_clk_init(void)78 __attribute__((weak)) void esp_clk_init(void)
79 {
80 rtc_config_t cfg = RTC_CONFIG_DEFAULT();
81 soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0);
82 if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
83 cfg.cali_ocode = 1;
84 }
85 rtc_init(cfg);
86
87 rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
88
89 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
90 // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
91 // If the frequency changes from 90kHz to 32kHz, then the timeout set for the WDT will increase 2.8 times.
92 // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
93 // This prevents excessive delay before resetting in case the supply voltage is drawdown.
94 // (If frequency is changed from 90kHz to 32kHz then WDT timeout will increased to 1.6sec * 90/32 = 4.5 sec).
95 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
96 uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
97 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
98 wdt_hal_feed(&rtc_wdt_ctx);
99 //Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
100 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
101 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
102 #endif
103
104 #if defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS)
105 select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
106 #elif defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC)
107 select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
108 #elif defined(CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256)
109 select_rtc_slow_clk(SLOW_CLK_8MD256);
110 #else
111 select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
112 #endif
113
114 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
115 // After changing a frequency WDT timeout needs to be set for new frequency.
116 stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000ULL);
117 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
118 wdt_hal_feed(&rtc_wdt_ctx);
119 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
120 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
121 #endif
122
123 rtc_cpu_freq_config_t old_config, new_config;
124 rtc_clk_cpu_freq_get_config(&old_config);
125 const uint32_t old_freq_mhz = old_config.freq_mhz;
126 const uint32_t new_freq_mhz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ;
127
128 bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
129 assert(res);
130
131 // Wait for UART TX to finish, otherwise some UART output will be lost
132 // when switching APB frequency
133 #ifdef CONFIG_ESP_CONSOLE_UART
134 esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
135 #endif
136
137 if (res) {
138 rtc_clk_cpu_freq_set_config(&new_config);
139 }
140
141 // Re calculate the ccount to make time calculation correct.
142 cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
143 }
144
select_rtc_slow_clk(slow_clk_sel_t slow_clk)145 static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
146 {
147 #ifdef CONFIG_IDF_ENV_FPGA
148 return;
149 #endif
150 rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
151 uint32_t cal_val = 0;
152 /* number of times to repeat 32k XTAL calibration
153 * before giving up and switching to the internal RC
154 */
155 int retry_32k_xtal = RTC_XTAL_CAL_RETRY;
156
157 do {
158 if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
159 /* 32k XTAL oscillator needs to be enabled and running before it can
160 * be used. Hardware doesn't have a direct way of checking if the
161 * oscillator is running. Here we use rtc_clk_cal function to count
162 * the number of main XTAL cycles in the given number of 32k XTAL
163 * oscillator cycles. If the 32k XTAL has not started up, calibration
164 * will time out, returning 0.
165 */
166 ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
167 if (slow_clk == SLOW_CLK_32K_XTAL) {
168 rtc_clk_32k_enable(true);
169 } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
170 rtc_clk_32k_enable_external();
171 }
172 // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
173 if (SLOW_CLK_CAL_CYCLES > 0) {
174 cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
175 if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) {
176 if (retry_32k_xtal-- > 0) {
177 continue;
178 }
179 ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 90 kHz oscillator");
180 rtc_slow_freq = RTC_SLOW_FREQ_RTC;
181 }
182 }
183 } else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) {
184 rtc_clk_8m_enable(true, true);
185 }
186 rtc_clk_slow_freq_set(rtc_slow_freq);
187
188 if (SLOW_CLK_CAL_CYCLES > 0) {
189 /* TODO: 32k XTAL oscillator has some frequency drift at startup.
190 * Improve calibration routine to wait until the frequency is stable.
191 */
192 cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
193 } else {
194 const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
195 cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
196 }
197 } while (cal_val == 0);
198 ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
199 esp_clk_slowclk_cal_set(cal_val);
200 }
201
rtc_clk_select_rtc_slow_clk(void)202 void rtc_clk_select_rtc_slow_clk(void)
203 {
204 select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
205 }
206
207 /* This function is not exposed as an API at this point.
208 * All peripheral clocks are default enabled after chip is powered on.
209 * This function disables some peripheral clocks when cpu starts.
210 * These peripheral clocks are enabled when the peripherals are initialized
211 * and disabled when they are de-initialized.
212 */
esp_perip_clk_init(void)213 __attribute__((weak)) void esp_perip_clk_init(void)
214 {
215 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
216 uint32_t common_perip_clk1 = 0;
217
218 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
219
220 /* For reason that only reset CPU, do not disable the clocks
221 * that have been enabled before reset.
222 */
223 if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
224 rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
225 common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
226 hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
227 wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
228 } else {
229 common_perip_clk = DPORT_WDG_CLK_EN |
230 DPORT_I2S0_CLK_EN |
231 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
232 DPORT_UART_CLK_EN |
233 #endif
234 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
235 DPORT_UART1_CLK_EN |
236 #endif
237 DPORT_SPI2_CLK_EN |
238 DPORT_I2C_EXT0_CLK_EN |
239 DPORT_UHCI0_CLK_EN |
240 DPORT_RMT_CLK_EN |
241 DPORT_PCNT_CLK_EN |
242 DPORT_LEDC_CLK_EN |
243 DPORT_TIMERGROUP1_CLK_EN |
244 DPORT_SPI3_CLK_EN |
245 DPORT_PWM0_CLK_EN |
246 DPORT_TWAI_CLK_EN |
247 DPORT_PWM1_CLK_EN |
248 DPORT_I2S1_CLK_EN |
249 DPORT_SPI2_DMA_CLK_EN |
250 DPORT_SPI3_DMA_CLK_EN |
251 DPORT_PWM2_CLK_EN |
252 DPORT_PWM3_CLK_EN;
253 common_perip_clk1 = 0;
254 hwcrypto_perip_clk = DPORT_CRYPTO_AES_CLK_EN |
255 DPORT_CRYPTO_SHA_CLK_EN |
256 DPORT_CRYPTO_RSA_CLK_EN;
257 wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
258 DPORT_WIFI_CLK_BT_EN_M |
259 DPORT_WIFI_CLK_UNUSED_BIT5 |
260 DPORT_WIFI_CLK_UNUSED_BIT12 |
261 DPORT_WIFI_CLK_SDIOSLAVE_EN |
262 DPORT_WIFI_CLK_SDIO_HOST_EN |
263 DPORT_WIFI_CLK_EMAC_EN;
264 }
265
266 //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
267 common_perip_clk |= DPORT_I2S0_CLK_EN |
268 #if CONFIG_ESP_CONSOLE_UART_NUM != 0
269 DPORT_UART_CLK_EN |
270 #endif
271 #if CONFIG_ESP_CONSOLE_UART_NUM != 1
272 DPORT_UART1_CLK_EN |
273 #endif
274 #ifndef CONFIG_ESP32S2_KEEP_USB_ALIVE
275 DPORT_USB_CLK_EN |
276 #endif
277 DPORT_SPI2_CLK_EN |
278 DPORT_I2C_EXT0_CLK_EN |
279 DPORT_UHCI0_CLK_EN |
280 DPORT_RMT_CLK_EN |
281 DPORT_UHCI1_CLK_EN |
282 DPORT_SPI3_CLK_EN |
283 DPORT_I2C_EXT1_CLK_EN |
284 DPORT_I2S1_CLK_EN |
285 DPORT_SPI2_DMA_CLK_EN |
286 DPORT_SPI3_DMA_CLK_EN;
287 common_perip_clk1 = 0;
288
289 #ifndef CONFIG_IDF_ENV_FPGA
290 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
291 * the current is not reduced when disable I2S clock.
292 */
293 REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
294 REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
295 #endif // CONFIG_IDF_ENV_FPGA
296
297 /* Disable some peripheral clocks. */
298 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
299 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
300
301 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, common_perip_clk1);
302 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1);
303
304 /* Disable hardware crypto clocks. */
305 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
306 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
307
308 /* Disable WiFi/BT/SDIO clocks. */
309 DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
310
311 /* Enable WiFi MAC and POWER clocks */
312 DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
313
314 /* Set WiFi light sleep clock source to RTC slow clock */
315 DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0);
316 DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
317 DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
318
319
320 /* Enable RNG clock. */
321 periph_module_enable(PERIPH_RNG_MODULE);
322 }
323
