1 /*
2 Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip).
3 */
4
5 /*
6 * SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11 #if defined(__ZEPHYR__)
12 #include <zephyr/kernel.h>
13 #include <zephyr/logging/log.h>
14 #endif
15 #include "sdkconfig.h"
16 #include "string.h"
17 #include "esp_attr.h"
18 #include "esp_err.h"
19 #include "esp_types.h"
20 #include "esp_log.h"
21 #include "spiram_psram.h"
22 #include "esp32s3/rom/spi_flash.h"
23 #include "esp32s3/rom/opi_flash.h"
24 #include "esp32s3/rom/cache.h"
25 #include "esp32s3/rom/efuse.h"
26 #include "esp_rom_gpio.h"
27 #include "esp_rom_efuse.h"
28 #include "soc/dport_reg.h"
29 #include "soc/efuse_periph.h"
30 #include "soc/soc_caps.h"
31 #include "soc/io_mux_reg.h"
32 #include "soc/syscon_reg.h"
33 #include "soc/efuse_reg.h"
34 #include "soc/soc.h"
35 #include "soc/io_mux_reg.h"
36 #include "driver/gpio.h"
37 #include "hal/gpio_hal.h"
38 #if !defined(__ZEPHYR__)
39 #include "driver/spi_common_internal.h"
40 #endif
41 #include "driver/spi_common.h"
42 #include "driver/periph_ctrl.h"
43 #include "bootloader_common.h"
44
45 #if CONFIG_SPIRAM_MODE_QUAD
46 #include "soc/rtc.h"
47 #include "esp_private/spi_flash_os.h"
48
49 static const char* TAG = "psram";
50
51 //Commands for PSRAM chip
52 #define PSRAM_READ 0x03
53 #define PSRAM_FAST_READ 0x0B
54 #define PSRAM_FAST_READ_QUAD 0xEB
55 #define PSRAM_WRITE 0x02
56 #define PSRAM_QUAD_WRITE 0x38
57 #define PSRAM_ENTER_QMODE 0x35
58 #define PSRAM_EXIT_QMODE 0xF5
59 #define PSRAM_RESET_EN 0x66
60 #define PSRAM_RESET 0x99
61 #define PSRAM_SET_BURST_LEN 0xC0
62 #define PSRAM_DEVICE_ID 0x9F
63
64 #define PSRAM_FAST_READ_DUMMY 4
65 #define PSRAM_FAST_READ_QUAD_DUMMY 6
66
67 // ID
68 #define PSRAM_ID_KGD_M 0xff
69 #define PSRAM_ID_KGD_S 8
70 #define PSRAM_ID_KGD 0x5d
71 #define PSRAM_ID_EID_M 0xff
72 #define PSRAM_ID_EID_S 16
73
74 // Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
75 //
76 // BIT7 | BIT6 | BIT5 | SIZE(MBIT)
77 // -------------------------------------
78 // 0 | 0 | 0 | 16
79 // 0 | 0 | 1 | 32
80 // 0 | 1 | 0 | 64
81 #define PSRAM_EID_SIZE_M 0x07
82 #define PSRAM_EID_SIZE_S 5
83
84 #define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
85 #define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
86 #define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
87 #define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
88
89 #define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
90
91 // IO-pins for PSRAM.
92 // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
93 // hardcode the flash pins as well, making this code incompatible with either a setup
94 // that has the flash on non-standard pins or ESP32s with built-in flash.
95 #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
96 #define FLASH_CS_IO SPI_CS0_GPIO_NUM
97 // PSRAM clock and cs IO should be configured based on hardware design.
98 #define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30
99 #define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26
100 #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
101 #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
102 #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
103 #define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
104
105 #define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
106 #define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
107
108 #define SPI1_NUM 1
109 #define SPI0_NUM 0
110
111
112 typedef enum {
113 PSRAM_EID_SIZE_16MBITS = 0,
114 PSRAM_EID_SIZE_32MBITS = 1,
115 PSRAM_EID_SIZE_64MBITS = 2,
116 } psram_eid_size_t;
117
118 typedef enum {
119 PSRAM_CMD_QPI,
120 PSRAM_CMD_SPI,
121 } psram_cmd_mode_t;
122
123 typedef esp_rom_spi_cmd_t psram_cmd_t;
124
125 static uint32_t s_psram_id = 0;
126 static void config_psram_spi_phases(void);
127 extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
128
129 static uint8_t s_psram_cs_io = (uint8_t)-1;
130
psram_get_cs_io(void)131 uint8_t psram_get_cs_io(void)
132 {
133 return s_psram_cs_io;
134 }
135
psram_set_op_mode(int spi_num,psram_cmd_mode_t mode)136 static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
137 {
138 if (mode == PSRAM_CMD_QPI) {
139 esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE);
140 SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
141 } else if (mode == PSRAM_CMD_SPI) {
142 esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE);
143 }
144 }
_psram_exec_cmd(int spi_num,uint32_t cmd,int cmd_bit_len,uint32_t addr,int addr_bit_len,int dummy_bits,uint8_t * mosi_data,int mosi_bit_len,uint8_t * miso_data,int miso_bit_len)145 static void _psram_exec_cmd(int spi_num,
146 uint32_t cmd, int cmd_bit_len,
147 uint32_t addr, int addr_bit_len,
148 int dummy_bits,
149 uint8_t* mosi_data, int mosi_bit_len,
150 uint8_t* miso_data, int miso_bit_len)
151 {
152 esp_rom_spi_cmd_t conf;
153 uint32_t _addr = addr;
154 conf.addr = &_addr;
155 conf.addrBitLen = addr_bit_len;
156 conf.cmd = cmd;
157 conf.cmdBitLen = cmd_bit_len;
158 conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723
159 conf.txData = (uint32_t*) mosi_data;
160 conf.txDataBitLen = mosi_bit_len;
161 conf.rxData = (uint32_t*) miso_data;
162 conf.rxDataBitLen = miso_bit_len;
163 esp_rom_spi_cmd_config(spi_num, &conf);
164 }
165
psram_exec_cmd(int spi_num,psram_cmd_mode_t mode,uint32_t cmd,int cmd_bit_len,uint32_t addr,int addr_bit_len,int dummy_bits,uint8_t * mosi_data,int mosi_bit_len,uint8_t * miso_data,int miso_bit_len,uint32_t cs_mask,bool is_write_erase_operation)166 void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
167 uint32_t cmd, int cmd_bit_len,
168 uint32_t addr, int addr_bit_len,
169 int dummy_bits,
170 uint8_t* mosi_data, int mosi_bit_len,
171 uint8_t* miso_data, int miso_bit_len,
172 uint32_t cs_mask,
173 bool is_write_erase_operation)
174 {
175 uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
176 uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
177 uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
178 uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
179 psram_set_op_mode(spi_num, mode);
180 _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
181 dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
182 esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
183
184 WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
185 WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
186 WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
187 WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl);
188 }
189
190 //exit QPI mode(set back to SPI mode)
psram_disable_qio_mode(int spi_num)191 static void psram_disable_qio_mode(int spi_num)
192 {
193 psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
194 PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
195 0, 0, /* address and address bit len*/
196 0, /* dummy bit len */
197 NULL, 0, /* tx data and tx bit len*/
198 NULL, 0, /* rx data and rx bit len*/
199 CS_PSRAM_SEL, /* cs bit mask*/
200 false); /* whether is program/erase operation */
201 }
202
203 //switch psram burst length(32 bytes or 1024 bytes)
204 //datasheet says it should be 1024 bytes by default
psram_set_wrap_burst_length(int spi_num,psram_cmd_mode_t mode)205 static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
206 {
207 psram_exec_cmd(spi_num, mode,
208 PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
209 0, 0, /* address and address bit len*/
210 0, /* dummy bit len */
211 NULL, 0, /* tx data and tx bit len*/
212 NULL, 0, /* rx data and rx bit len*/
213 CS_PSRAM_SEL, /* cs bit mask*/
214 false); /* whether is program/erase operation */
215 }
216
217 //send reset command to psram, in spi mode
psram_reset_mode(int spi_num)218 static void psram_reset_mode(int spi_num)
219 {
220 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
221 PSRAM_RESET_EN, 8, /* command and command bit len*/
222 0, 0, /* address and address bit len*/
223 0, /* dummy bit len */
224 NULL, 0, /* tx data and tx bit len*/
225 NULL, 0, /* rx data and rx bit len*/
226 CS_PSRAM_SEL, /* cs bit mask*/
227 false); /* whether is program/erase operation */
228
229 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
230 PSRAM_RESET, 8, /* command and command bit len*/
231 0, 0, /* address and address bit len*/
232 0, /* dummy bit len */
233 NULL, 0, /* tx data and tx bit len*/
234 NULL, 0, /* rx data and rx bit len*/
235 CS_PSRAM_SEL, /* cs bit mask*/
236 false); /* whether is program/erase operation */
237 }
238
psram_enable_wrap(uint32_t wrap_size)239 esp_err_t psram_enable_wrap(uint32_t wrap_size)
240 {
241 static uint32_t current_wrap_size = 0;
242 if (current_wrap_size == wrap_size) {
243 return ESP_OK;
244 }
245 switch (wrap_size) {
246 case 32:
247 case 0:
248 psram_set_wrap_burst_length(1, PSRAM_CMD_QPI);
249 current_wrap_size = wrap_size;
250 return ESP_OK;
251 case 16:
252 case 64:
253 default:
254 return ESP_FAIL;
255 }
256 }
257
psram_support_wrap_size(uint32_t wrap_size)258 bool psram_support_wrap_size(uint32_t wrap_size)
259 {
260 switch (wrap_size) {
261 case 0:
262 case 32:
263 return true;
264 case 16:
265 case 64:
266 default:
267 return false;
268 }
269
270 }
271
272 //Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this
psram_read_id(int spi_num,uint32_t * dev_id)273 static void psram_read_id(int spi_num, uint32_t* dev_id)
274 {
275 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
276 PSRAM_DEVICE_ID, 8, /* command and command bit len*/
277 0, 24, /* address and address bit len*/
278 0, /* dummy bit len */
279 NULL, 0, /* tx data and tx bit len*/
280 (uint8_t*) dev_id, 24, /* rx data and rx bit len*/
281 CS_PSRAM_SEL, /* cs bit mask*/
282 false); /* whether is program/erase operation */
283 }
284
285 //enter QPI mode
psram_enable_qio_mode(int spi_num)286 static void psram_enable_qio_mode(int spi_num)
287 {
288 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
289 PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
290 0, 0, /* address and address bit len*/
291 0, /* dummy bit len */
292 NULL, 0, /* tx data and tx bit len*/
293 NULL, 0, /* rx data and rx bit len*/
294 CS_PSRAM_SEL, /* cs bit mask*/
295 false); /* whether is program/erase operation */
296 }
297
psram_set_cs_timing(void)298 static void psram_set_cs_timing(void)
299 {
300 //SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers for PSRAM, so we only need to set SPI0 related registers here
301 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S);
302 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S);
303 SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M);
304 }
305
psram_gpio_config(void)306 static void psram_gpio_config(void)
307 {
308 //CS1
309 uint8_t cs1_io = PSRAM_CS_IO;
310 if (cs1_io == SPI_CS1_GPIO_NUM) {
311 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], FUNC_SPICS1_SPICS1);
312 } else {
313 esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, 0, 0);
314 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], PIN_FUNC_GPIO);
315 }
316 s_psram_cs_io = cs1_io;
317
318 //WP HD
319 uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
320 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
321 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
322 // MSPI pins (except wp / hd) are all configured via IO_MUX in 1st bootloader.
323 } else {
324 // MSPI pins (except wp / hd) are all configured via GPIO matrix in 1st bootloader.
325 wp_io = esp_rom_efuse_get_flash_wp_gpio();
326 }
327 //This ROM function will init both WP and HD pins.
328 esp_rom_spiflash_select_qio_pins(wp_io, spiconfig);
329 }
330
psram_get_size(void)331 psram_size_t psram_get_size(void)
332 {
333 if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
334 return PSRAM_SIZE_64MBITS;
335 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) {
336 return PSRAM_SIZE_32MBITS;
337 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) {
338 return PSRAM_SIZE_16MBITS;
339 } else {
340 return PSRAM_SIZE_MAX;
341 }
342 return PSRAM_SIZE_MAX;
343 }
344
345 /*
346 * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
347 * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
348 */
psram_enable(psram_cache_mode_t mode,psram_vaddr_mode_t vaddrmode)349 esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
350 {
351 assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
352
353 psram_gpio_config();
354 psram_set_cs_timing();
355
356 //enter MSPI slow mode to init PSRAM device registers
357 spi_timing_enter_mspi_low_speed_mode(true);
358
359 //We use SPI1 to init PSRAM
360 psram_disable_qio_mode(SPI1_NUM);
361 psram_read_id(SPI1_NUM, &s_psram_id);
362 if (!PSRAM_IS_VALID(s_psram_id)) {
363 /* 16Mbit psram ID read error workaround:
364 * treat the first read id as a dummy one as the pre-condition,
365 * Send Read ID command again
366 */
367 psram_read_id(SPI1_NUM, &s_psram_id);
368 if (!PSRAM_IS_VALID(s_psram_id)) {
369 ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
370 return ESP_FAIL;
371 }
372 }
373
374 //SPI1: send psram reset command
375 psram_reset_mode(SPI1_NUM);
376 //SPI1: send QPI enable command
377 psram_enable_qio_mode(SPI1_NUM);
378
379 //Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
380 spi_timing_psram_tuning();
381
382 //Configure SPI0 PSRAM related SPI Phases
383 config_psram_spi_phases();
384 //Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
385 spi_timing_enter_mspi_high_speed_mode(true);
386
387 return ESP_OK;
388 }
389
390 //Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
config_psram_spi_phases(void)391 static void config_psram_spi_phases(void)
392 {
393 //Config CMD phase
394 CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
395 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command
396 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command
397 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command
398 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
399 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
400 SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
401 SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
402
403 //Config ADDR phase
404 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S);
405
406 //Dummy
407 /**
408 * We set the PSRAM chip required dummy here. If timing tuning is needed,
409 * the dummy length will be updated in `spi_timing_enter_mspi_high_speed_mode()`
410 */
411 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
412 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUAD_DUMMY - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy
413
414 CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
415 }
416 #endif // CONFIG_SPIRAM
417
