1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifdef __ZEPHYR__
8 #include <zephyr/kernel.h>
9 #endif
10
11 #include <stdint.h>
12 #include "esp_rom_sys.h"
13 #include "soc/rtc.h"
14 #include "soc/rtc_cntl_reg.h"
15 #include "soc/timer_group_reg.h"
16 #include "rtc_clk_common.h"
17
18 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
19 * This feature counts the number of XTAL clock cycles within a given number of
20 * RTC_SLOW_CLK cycles.
21 *
22 * Slow clock calibration feature has two modes of operation: one-off and cycling.
23 * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
24 * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
25 * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
26 * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
27 * enabled using TIMG_RTC_CALI_START bit.
28 */
29
30 /**
31 * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
32 * @param cal_clk which clock to calibrate
33 * @param slowclk_cycles number of slow clock cycles to count
34 * @return number of XTAL clock cycles within the given number of slow clock cycles
35 */
rtc_clk_cal_internal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)36 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
37 {
38 /* On ESP32S3, choosing RTC_CAL_RTC_MUX results in calibration of
39 * the 150k RTC clock regardless of the currenlty selected SLOW_CLK.
40 * On the ESP32, it used the currently selected SLOW_CLK.
41 * The following code emulates ESP32 behavior:
42 */
43 if (cal_clk == RTC_CAL_RTC_MUX) {
44 rtc_slow_freq_t slow_freq = rtc_clk_slow_freq_get();
45 if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
46 cal_clk = RTC_CAL_32K_XTAL;
47 } else if (slow_freq == RTC_SLOW_FREQ_8MD256) {
48 cal_clk = RTC_CAL_8MD256;
49 }
50 } else if (cal_clk == RTC_CAL_INTERNAL_OSC) {
51 cal_clk = RTC_CAL_RTC_MUX;
52 }
53
54 /* Enable requested clock (150k clock is always on) */
55 int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
56 if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) {
57 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
58 }
59
60 if (cal_clk == RTC_CAL_8MD256) {
61 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
62 }
63 /* There may be another calibration process already running during we call this function,
64 * so we should wait the last process is done.
65 */
66 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
67 /**
68 * Set a small timeout threshold to accelerate the generation of timeout.
69 * The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
70 */
71 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
72 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
73 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
74 }
75
76 /* Prepare calibration */
77 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
78 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
79 REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
80 /* Figure out how long to wait for calibration to finish */
81
82 /* Set timeout reg and expect time delay*/
83 uint32_t expected_freq;
84 if (cal_clk == RTC_CAL_32K_XTAL) {
85 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles));
86 expected_freq = RTC_SLOW_CLK_FREQ_32K;
87 } else if (cal_clk == RTC_CAL_8MD256) {
88 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles));
89 expected_freq = RTC_SLOW_CLK_FREQ_8MD256;
90 } else {
91 REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
92 expected_freq = RTC_SLOW_CLK_FREQ_150K;
93 }
94 uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * 1000000 / expected_freq);
95 /* Start calibration */
96 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
97 SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
98
99 /* Wait for calibration to finish up to another us_time_estimate */
100 #ifdef __ZEPHYR__
101 k_busy_wait(us_time_estimate);
102 #else
103 esp_rom_delay_us(us_time_estimate);
104 #endif
105 uint32_t cal_val;
106 while (true) {
107 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
108 cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
109 break;
110 }
111 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
112 cal_val = 0;
113 break;
114 }
115 }
116 CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
117
118 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state);
119
120 if (cal_clk == RTC_CAL_8MD256) {
121 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
122 }
123
124 return cal_val;
125 }
126
rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)127 uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
128 {
129 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
130 uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
131 uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
132 return ratio;
133 }
134
rtc_clk_cal(rtc_cal_sel_t cal_clk,uint32_t slowclk_cycles)135 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
136 {
137 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
138 uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
139 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
140 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
141 uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
142 return period;
143 }
144
rtc_time_us_to_slowclk(uint64_t time_in_us,uint32_t period)145 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
146 {
147 /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
148 * TODO: fix overflow.
149 */
150 return (time_in_us << RTC_CLK_CAL_FRACT) / period;
151 }
152
rtc_time_slowclk_to_us(uint64_t rtc_cycles,uint32_t period)153 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
154 {
155 return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
156 }
157
rtc_time_get(void)158 uint64_t rtc_time_get(void)
159 {
160 SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
161 uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
162 t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
163 return t;
164 }
165
rtc_light_slp_time_get(void)166 uint64_t rtc_light_slp_time_get(void)
167 {
168 uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG);
169 t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32;
170 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
171 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
172 return (t_wake - t_slp);
173 }
174
rtc_deep_slp_time_get(void)175 uint64_t rtc_deep_slp_time_get(void)
176 {
177 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
178 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
179 uint64_t t_wake = rtc_time_get();
180 return (t_wake - t_slp);
181 }
182
rtc_clk_wait_for_slow_cycle(void)183 void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
184 {
185 SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
186 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {
187 esp_rom_delay_us(1);
188 }
189 }
190
rtc_clk_freq_cal(uint32_t cal_val)191 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
192 {
193 if (cal_val == 0) {
194 return 0; // cal_val will be denominator, return 0 as the symbol of failure.
195 }
196 return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
197 }
198
