1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include "esp_attr.h"
9 #include "soc/soc.h"
10 #include "soc/rtc.h"
11 #include "soc/rtc_cntl_reg.h"
12 #include "soc/syscon_reg.h"
13 #include "soc/dport_reg.h"
14 #include "soc/rtc.h"
15 #include "soc/i2s_reg.h"
16 #include "soc/timer_group_reg.h"
17 #include "soc/bb_reg.h"
18 #include "soc/nrx_reg.h"
19 #include "soc/fe_reg.h"
20 #include "soc/rtc.h"
21 #include "regi2c_ctrl.h"
22 #include "soc/rtc.h"
23
24 #define RTC_CNTL_MEM_FOLW_CPU (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
25
26 static const DRAM_ATTR rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
27
28 /**
29 * Configure whether certain peripherals are powered up in sleep
30 * @param cfg power down flags as rtc_sleep_pu_config_t structure
31 */
rtc_sleep_pu(rtc_sleep_pu_config_t cfg)32 void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
33 {
34 REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
35 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
36 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
37 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
38 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
39 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
40 REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
41 REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
42 REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
43 REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
44 REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
45 REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
46 REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
47 if (cfg.sram_fpu) {
48 REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
49 } else {
50 REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
51 }
52 if (cfg.rom_ram_fpu) {
53 REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
54 } else {
55 REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
56 }
57 }
58
rtc_sleep_get_default_config(uint32_t sleep_flags,rtc_sleep_config_t * out_config)59 void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config)
60 {
61 *out_config = (rtc_sleep_config_t) {
62 .lslp_mem_inf_fpu = 0,
63 .rtc_mem_inf_follow_cpu = (sleep_flags & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0,
64 .rtc_fastmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0,
65 .rtc_slowmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0,
66 .rtc_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0,
67 .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0,
68 .bt_pd_en = (sleep_flags & RTC_SLEEP_PD_BT) ? 1 : 0,
69 .cpu_pd_en = (sleep_flags & RTC_SLEEP_PD_CPU) ? 1 : 0,
70 .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0,
71 .dig_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0,
72 .deep_slp = (sleep_flags & RTC_SLEEP_PD_DIG) ? 1 : 0,
73 .wdt_flashboot_mod_en = 0,
74 .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0,
75 .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1,
76 .deep_slp_reject = 1,
77 .light_slp_reject = 1,
78 .rtc_dbias_slp = RTC_CNTL_DBIAS_1V10
79 };
80
81 if (sleep_flags & RTC_SLEEP_PD_DIG) {
82 assert(sleep_flags & RTC_SLEEP_PD_XTAL);
83 out_config->dig_dbias_slp = 0; //not used
84 //rtc voltage from high to low
85 if ((sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || (!(sleep_flags & RTC_SLEEP_PD_INT_8M))) {
86 /*
87 * rtc voltage in sleep mode >= 0.9v
88 * if 8MD256 select as RTC slow clock src, only need dbg_atten_slp set to 0
89 * Support all features:
90 * - 8MD256 as RTC slow clock src
91 * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0)
92 * - RTC IO as input
93 * - RTC Memory at high temperature
94 * - ULP
95 * - Touch sensor
96 */
97 out_config->rtc_regulator_fpu = 1;
98 out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP;
99 } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) {
100 /*
101 * rtc voltage in sleep mode >= 0.7v (default mode):
102 * Support follow features:
103 * - RTC IO as input
104 * - RTC Memory at high temperature
105 * - ULP
106 * - Touch sensor
107 */
108 out_config->rtc_regulator_fpu = 1;
109 out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
110 } else {
111 /*
112 * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power):
113 * Support follow features:
114 * - ULP
115 * - Touch sensor
116 */
117 out_config->rtc_regulator_fpu = 0;
118 out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW;
119 }
120 } else {
121 out_config->rtc_regulator_fpu = 1;
122 //voltage from high to low
123 if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) {
124 /*
125 * digital voltage not less than 1.1v, rtc voltage is about 1.1v
126 * Support all features:
127 * - XTAL
128 * - RC 8M used by digital system
129 * - 8MD256 as RTC slow clock src (only need dbg_atten_slp to 0)
130 * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0)
131
132 * - ULP
133 * - Touch sensor
134 */
135 out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
136 out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10;
137 } else if (!(sleep_flags & RTC_SLEEP_PD_INT_8M)){
138 /*
139 * dbg_atten_slp need to set to 0.
140 * digital voltage is about 0.67v, rtc voltage is about 1.1v
141 * Support features:
142 * - 8MD256 as RTC slow clock src
143 * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0)
144 * - ULP
145 * - Touch sensor
146 */
147 out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
148 out_config->dig_dbias_slp = 0;
149 } else {
150 /*
151 * digital voltage not less than 0.6v, rtc voltage is about 0.95v
152 * Support features:
153 * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monitor = 0)
154 * - ULP
155 * - Touch sensor
156 */
157 out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
158 out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP;
159 }
160 }
161
162 if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) {
163 out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_ON;
164 out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_ON;
165
166 out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON;
167 out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON;
168 } else {
169 out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
170 out_config->pd_cur_monitor = (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR)?
171 RTC_CNTL_PD_CUR_MONITOR_ON : RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
172
173 out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
174 out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
175 }
176 }
177
rtc_sleep_init(rtc_sleep_config_t cfg)178 void rtc_sleep_init(rtc_sleep_config_t cfg)
179 {
180 if (cfg.lslp_mem_inf_fpu) {
181 rtc_sleep_pu(pu_cfg);
182 }
183 /* mem force pu */
184 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
185 if (cfg.wifi_pd_en) {
186 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO);
187 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
188 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
189 } else {
190 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
191 }
192 if (cfg.bt_pd_en) {
193 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO);
194 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
195 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
196 } else {
197 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
198 }
199 if (cfg.cpu_pd_en) {
200 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO);
201 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
202 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
203 } else {
204 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
205 }
206 if (cfg.dig_peri_pd_en) {
207 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO);
208 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
209 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
210 } else {
211 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
212 }
213 if (cfg.rtc_peri_pd_en) {
214 REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO | RTC_CNTL_FORCE_ISO | RTC_CNTL_FORCE_PU);
215 SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
216 } else {
217 CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
218 }
219
220 assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor);
221 assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp);
222 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
223 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
224
225 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp);
226 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp);
227 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
228
229 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
230 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor);
231 REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor);
232
233 if (cfg.deep_slp) {
234 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
235 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
236 RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
237 RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
238 } else {
239 REG_SET_FIELD(RTC_CNTL_REGULATOR_DRV_CTRL_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
240 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
241 }
242 /* mem pd */
243 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
244
245 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu);
246 if (!cfg.int_8m_pd_en) {
247 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
248 } else {
249 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
250 }
251
252 /* enable VDDSDIO control by state machine */
253 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
254 REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
255
256 REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
257 REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
258 /* Set wait cycle for touch or COCPU after deep sleep and light sleep. */
259 REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP);
260
261 REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
262 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
263 }
264
rtc_sleep_low_init(uint32_t slowclk_period)265 void rtc_sleep_low_init(uint32_t slowclk_period)
266 {
267 // set 5 PWC state machine times to fit in main state machine time
268 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
269 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
270 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
271 }
272
rtc_sleep_set_wakeup_time(uint64_t t)273 void rtc_sleep_set_wakeup_time(uint64_t t)
274 {
275 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
276 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
277 }
278
279 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
280
rtc_sleep_start(uint32_t wakeup_opt,uint32_t reject_opt,uint32_t lslp_mem_inf_fpu)281 __attribute__((weak)) uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
282 {
283 REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
284 REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
285
286 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
287 RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
288
289 /* Start entry into sleep mode */
290 SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
291
292 while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
293 RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
294 ;
295 }
296 return rtc_sleep_finish(lslp_mem_inf_fpu);
297 }
298
rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)299 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
300 {
301 /* In deep sleep mode, we never get here */
302 uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
303 SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
304 RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
305
306 /* restore config if it is a light sleep */
307 if (lslp_mem_inf_fpu) {
308 rtc_sleep_pu(pu_cfg);
309 }
310
311 /* Recover default wait cycle for touch or COCPU after wakeup. */
312 REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
313
314 return reject;
315 }
316
