1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include "soc/soc.h"
9 #include "soc/rtc.h"
10 #include "soc/rtc_cntl_reg.h"
11 #include "soc/dport_reg.h"
12 #include "soc/gpio_reg.h"
13 #include "soc/syscon_reg.h"
14 #include "soc/spi_mem_reg.h"
15 #include "soc/extmem_reg.h"
16 #include "soc/syscon_reg.h"
17 #include "regi2c_ctrl.h"
18 #include "regi2c_ulp.h"
19 #include "soc_log.h"
20 #include "esp_err.h"
21 #include "esp_attr.h"
22 #include "esp_efuse.h"
23 #include "esp_efuse_table.h"
24 #include "esp_private/spi_flash_os.h"
25 #ifndef BOOTLOADER_BUILD
26 #include "esp_private/sar_periph_ctrl.h"
27 #endif
28
29
30 #define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
31
32 static const char *TAG = "rtcinit";
33
34 static void set_ocode_by_efuse(int calib_version);
35 static void calibrate_ocode(void);
36 static void rtc_set_stored_dbias(void);
37
38 // Initial values are used for bootloader, and these variables will be re-assigned based on efuse values during application startup
39 uint32_t g_dig_dbias_pvt_240m = 28;
40 uint32_t g_rtc_dbias_pvt_240m = 28;
41 uint32_t g_dig_dbias_pvt_non_240m = 27;
42 uint32_t g_rtc_dbias_pvt_non_240m = 27;
43
rtc_init(rtc_config_t cfg)44 void rtc_init(rtc_config_t cfg)
45 {
46 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
47 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
48 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
49 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
50 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
51
52 /* Moved from rtc sleep to rtc init to save sleep function running time */
53 // set shortest possible sleep time limit
54 REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
55
56 // set wifi timer
57 rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
58 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
59 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
60 // set bt timer
61 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles);
62 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles);
63
64 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles);
65 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles);
66
67 // set rtc peri timer
68 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles);
69 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles);
70 // set digital wrap timer
71 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
72 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
73
74 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
75 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
76
77 /* Reset RTC bias to default value (needed if waking up from deep sleep) */
78 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10);
79 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, RTC_CNTL_DBIAS_1V10);
80 /* Set the wait time to the default value. */
81 REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
82
83 if (cfg.cali_ocode) {
84 uint32_t blk_ver_major = 0;
85 esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
86 if (err != ESP_OK) {
87 blk_ver_major = 0;
88 SOC_LOGW(TAG, "efuse read fail, set default blk_ver_major: %d\n", blk_ver_major);
89 }
90
91 //default blk_ver_major will fallback to using the self-calibration way for OCode
92 bool ocode_efuse_cali = (blk_ver_major == 1);
93 if (ocode_efuse_cali) {
94 set_ocode_by_efuse(blk_ver_major);
95 } else {
96 calibrate_ocode();
97 }
98 }
99
100 //LDO dbias initialization
101 rtc_set_stored_dbias();
102
103 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
104 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
105
106 if (cfg.clkctl_init) {
107 //clear CMMU clock force on
108 CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
109 //clear clkgate force on
110 REG_WRITE(SYSCON_CLKGATE_FORCE_ON_REG, 0);
111 //clear tag clock force on
112 CLEAR_PERI_REG_MASK(EXTMEM_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_DCACHE_TAG_MEM_FORCE_ON);
113 CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);
114 //clear register clock force on
115 CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN);
116 CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN);
117 }
118
119 if (cfg.pwrctl_init) {
120 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
121 //cancel xtal force pu if no need to force power up
122 //cannot cancel xtal force pu if pll is force power on
123 if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) {
124 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
125 } else {
126 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
127 }
128
129 //open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
130 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
131
132 //cancel bbpll force pu if setting no force power up
133 if (!cfg.bbpll_fpu) {
134 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
135 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
136 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
137 } else {
138 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
139 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
140 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
141 }
142 //cancel RTC REG force PU
143 CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU);
144 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
145 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
146
147 CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO);
148
149 if (cfg.rtc_dboost_fpd) {
150 SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
151 } else {
152 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
153 }
154 //clear i2c_reset_protect pd force, need tested in low temperature.
155 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
156
157 /* If this mask is enabled, all soc memories cannot enter power down mode */
158 /* We should control soc memory power down mode from RTC, so we will not touch this register any more */
159 CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
160 /* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
161 /* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
162 rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0);
163 rtc_sleep_pu(pu_cfg);
164
165 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
166 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | RTC_CNTL_DG_WRAP_FORCE_ISO);
167
168 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO);
169 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
170
171 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO);
172 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
173
174 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO);
175 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
176
177 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO);
178 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
179
180 REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
181 REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_ISO);
182 REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU);
183
184 //cancel digital PADS force no iso
185 if (cfg.cpu_waiti_clk_gate) {
186 CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
187 } else {
188 SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
189 }
190 /*if SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/
191 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
192 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
193 }
194 /* force power down wifi and bt power domain */
195 SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
196 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
197
198 REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
199 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
200
201 #ifndef BOOTLOADER_BUILD
202 //initialise SAR related peripheral register settings
203 // sar_periph_ctrl_init();
204 #endif
205 }
206
rtc_vddsdio_get_config(void)207 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
208 {
209 rtc_vddsdio_config_t result;
210 uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
211 result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
212 result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
213 result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
214 if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
215 // Get configuration from RTC
216 result.force = 1;
217 result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
218 result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
219 return result;
220 } else {
221 result.force = 0;
222 }
223 // Otherwise, VDD_SDIO is controlled by bootstrapping pin
224 uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
225 result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
226 result.enable = 1;
227 return result;
228 }
229
rtc_vddsdio_set_config(rtc_vddsdio_config_t config)230 void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
231 {
232 uint32_t val = 0;
233 val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
234 val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
235 val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
236 val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
237 val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
238 val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
239 val |= RTC_CNTL_SDIO_PD_EN;
240 REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
241 }
242
set_ocode_by_efuse(int calib_version)243 static void set_ocode_by_efuse(int calib_version)
244 {
245 assert(calib_version == 1);
246 // use efuse ocode.
247 uint32_t ocode;
248 esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8);
249 assert(err == ESP_OK);
250 (void) err;
251 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
252 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
253 }
254
255 /**
256 * TODO: IDF-4141
257 * 1. This function will change the system clock source to XTAL. Under lower frequency (e.g. XTAL), MSPI timing tuning configures should be modified accordingly.
258 * 2. RTC related should be done before SPI0 initialisation
259 */
calibrate_ocode(void)260 static void calibrate_ocode(void)
261 {
262 #ifndef BOOTLOADER_BUILD
263 /**
264 * Background:
265 * 1. Following code will switch the system clock to XTAL first, to self-calibrate the OCode.
266 * 2. For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
267 * Certain delay will be added to the MSPI RX direction.
268 *
269 * When CPU clock switches down, the delay should be cleared. Therefore here we call this function to remove the delays.
270 */
271 spi_timing_change_speed_mode_cache_safe(true);
272 #endif
273 /*
274 Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL).
275 Method:
276 1. read current cpu config, save in old_config;
277 2. switch cpu to xtal because PLL will be closed when o-code calibration;
278 3. begin o-code calibration;
279 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
280 5. set cpu to old-config.
281 */
282 rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
283 rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
284 rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
285 rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
286 if (slow_clk_freq == (rtc_slow_freq_x32k)) {
287 cal_clk = RTC_CAL_32K_XTAL;
288 } else if (slow_clk_freq == rtc_slow_freq_8MD256) {
289 cal_clk = RTC_CAL_8MD256;
290 }
291
292 uint64_t max_delay_time_us = 10000;
293 uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
294 uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
295 uint64_t cycle0 = rtc_time_get();
296 uint64_t timeout_cycle = cycle0 + max_delay_cycle;
297 uint64_t cycle1 = 0;
298
299 rtc_cpu_freq_config_t old_config;
300 rtc_clk_cpu_freq_get_config(&old_config);
301 rtc_clk_cpu_freq_set_xtal();
302
303 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
304 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
305 bool odone_flag = 0;
306 bool bg_odone_flag = 0;
307 while (1) {
308 odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG);
309 bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
310 cycle1 = rtc_time_get();
311 if (odone_flag && bg_odone_flag) {
312 break;
313 }
314 if (cycle1 >= timeout_cycle) {
315 SOC_LOGW(TAG, "o_code calibration fail\n");
316 break;
317 }
318 }
319 rtc_clk_cpu_freq_set_config(&old_config);
320 #ifndef BOOTLOADER_BUILD
321 //System clock is switched back to PLL. Here we switch to the MSPI high speed mode, add the delays back
322 spi_timing_change_speed_mode_cache_safe(false);
323 #endif
324 }
325
get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver)326 static uint32_t get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver)
327 {
328 assert(pvt_scheme_ver == 1);
329 uint32_t dig_dbias = 28;
330 esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, ESP_EFUSE_DIG_DBIAS_HVT[0]->bit_count);
331 if (err != ESP_OK) {
332 dig_dbias = 28;
333 SOC_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias);
334 }
335 return dig_dbias;
336 }
337
get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver,uint32_t dig_dbias)338 static uint32_t get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver, uint32_t dig_dbias)
339 {
340 assert(pvt_scheme_ver == 1);
341 uint32_t rtc_dbias = 0;
342 signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0;
343 esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, ESP_EFUSE_K_RTC_LDO[0]->bit_count);
344 esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count);
345 esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, ESP_EFUSE_V_RTC_DBIAS20[0]->bit_count);
346 esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count);
347 if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) {
348 k_rtc_ldo = 0;
349 k_dig_ldo = 0;
350 v_rtc_bias20 = 0;
351 v_dig_bias20 = 0;
352 SOC_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20);
353 }
354
355 k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): (uint8_t)k_rtc_ldo;
356 k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
357 v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
358 v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
359
360 uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
361 uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
362 signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
363 signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
364 uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
365 for (rtc_dbias = 15; rtc_dbias < 31; rtc_dbias++) {
366 uint32_t v_rtc_nearest_1v15_mul10000 = 0;
367 v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
368 if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250) {
369 break;
370 }
371 }
372 return rtc_dbias;
373 }
374
get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver)375 static uint32_t get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver)
376 {
377 assert(pvt_scheme_ver == 1);
378 signed int k_dig_ldo = 0, v_dig_bias20 = 0;
379 esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count);
380 esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count);
381 if ((err0 != ESP_OK) | (err1 != ESP_OK)) {
382 k_dig_ldo = 0;
383 v_dig_bias20 = 0;
384 SOC_LOGW(TAG, "efuse read fail, k_dig_ldo: %d, v_dig_bias20: %d\n", k_dig_ldo, v_dig_bias20);
385 }
386
387 k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
388 v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
389
390 uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
391 signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
392 uint32_t dig_dbias =15;
393 for (dig_dbias = 15; dig_dbias < 31; dig_dbias++) {
394 uint32_t v_dig_nearest_1v3_mul10000 = 0;
395 v_dig_nearest_1v3_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
396 if (v_dig_nearest_1v3_mul10000 >= 13000) {
397 break;
398 }
399 }
400 return dig_dbias;
401 }
402
rtc_set_stored_dbias(void)403 static void rtc_set_stored_dbias(void)
404 {
405 /*
406 1. a reasonable dig_dbias which by scaning pvt to make 240 CPU run successful stored in efuse;
407 2. also we store some value in efuse, include:
408 k_rtc_ldo (slope of rtc voltage & rtc_dbias);
409 k_dig_ldo (slope of digital voltage & digital_dbias);
410 v_rtc_bias20 (rtc voltage when rtc dbais is 20);
411 v_dig_bias20 (digital voltage when digital dbais is 20).
412 3. a reasonable rtc_dbias can be calculated by a certion formula.
413 4. save these values for reuse
414 */
415 uint32_t blk_minor = 0, blk_major = 0;
416 esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &blk_minor, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count);
417 esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count);
418 if ((err0 != ESP_OK) | (err1 != ESP_OK)) {
419 blk_minor = 0;
420 blk_major = 0;
421 SOC_LOGW(TAG, "efuse read fail, blk_minor: %d, blk_major: %d\n", blk_minor, blk_major);
422 }
423 uint8_t pvt_scheme_ver = 0;
424 if ( (blk_major <= 1 && blk_minor == 1) || blk_major > 1 || (blk_major == 1 && blk_minor >= 2) ) {
425 /* PVT supported after blk_ver 1.2 */
426 pvt_scheme_ver = 1;
427 }
428
429 if (pvt_scheme_ver == 1) {
430 uint32_t dig1v3_dbias = get_dig1v3_dbias_by_efuse(pvt_scheme_ver);
431 uint32_t dig_dbias = get_dig_dbias_by_efuse(pvt_scheme_ver);
432 if (dig_dbias != 0) {
433 g_dig_dbias_pvt_240m = MIN(dig1v3_dbias, dig_dbias + 3);
434 g_dig_dbias_pvt_non_240m = MIN(dig1v3_dbias, dig_dbias + 2);
435 g_rtc_dbias_pvt_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_240m);
436 g_rtc_dbias_pvt_non_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_non_240m);
437 } else {
438 SOC_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in blk version: 0%d\n", pvt_scheme_ver);
439 }
440 } else {
441 SOC_LOGD(TAG, "core voltage not decided in efuse, use default value.");
442 }
443 }
444
