1 /*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <drivers/arm/css/css_scpi.h>
14 #include <drivers/arm/gicv2.h>
15 #include <lib/mmio.h>
16 #include <lib/psci/psci.h>
17
18 #include <sunxi_mmap.h>
19 #include <sunxi_private.h>
20
21 /*
22 * The addresses for the SCP exception vectors are defined in the or1k
23 * architecture specification.
24 */
25 #define OR1K_VEC_FIRST 0x01
26 #define OR1K_VEC_LAST 0x0e
27 #define OR1K_VEC_ADDR(n) (0x100 * (n))
28
29 /*
30 * This magic value is the little-endian representation of the or1k
31 * instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the
32 * first instruction in the SCP firmware.
33 */
34 #define SCP_FIRMWARE_MAGIC 0xb4400012
35
36 #define PLAT_LOCAL_PSTATE_WIDTH U(4)
37 #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
38
39 #define CPU_PWR_LVL MPIDR_AFFLVL0
40 #define CLUSTER_PWR_LVL MPIDR_AFFLVL1
41 #define SYSTEM_PWR_LVL MPIDR_AFFLVL2
42
43 #define CPU_PWR_STATE(state) \
44 ((state)->pwr_domain_state[CPU_PWR_LVL])
45 #define CLUSTER_PWR_STATE(state) \
46 ((state)->pwr_domain_state[CLUSTER_PWR_LVL])
47 #define SYSTEM_PWR_STATE(state) \
48 ((state)->pwr_domain_state[SYSTEM_PWR_LVL])
49
sunxi_cpu_standby(plat_local_state_t cpu_state)50 static void sunxi_cpu_standby(plat_local_state_t cpu_state)
51 {
52 u_register_t scr = read_scr_el3();
53
54 assert(is_local_state_retn(cpu_state));
55
56 write_scr_el3(scr | SCR_IRQ_BIT);
57 wfi();
58 write_scr_el3(scr);
59 }
60
sunxi_pwr_domain_on(u_register_t mpidr)61 static int sunxi_pwr_domain_on(u_register_t mpidr)
62 {
63 scpi_set_css_power_state(mpidr,
64 scpi_power_on,
65 scpi_power_on,
66 scpi_power_on);
67
68 return PSCI_E_SUCCESS;
69 }
70
sunxi_pwr_domain_off(const psci_power_state_t * target_state)71 static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
72 {
73 plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state);
74 plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state);
75 plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state);
76
77 if (is_local_state_off(cpu_pwr_state)) {
78 gicv2_cpuif_disable();
79 }
80
81 scpi_set_css_power_state(read_mpidr(),
82 cpu_pwr_state,
83 cluster_pwr_state,
84 system_pwr_state);
85 }
86
sunxi_pwr_domain_on_finish(const psci_power_state_t * target_state)87 static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
88 {
89 if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
90 gicv2_distif_init();
91 }
92 if (is_local_state_off(CPU_PWR_STATE(target_state))) {
93 gicv2_pcpu_distif_init();
94 gicv2_cpuif_enable();
95 }
96 }
97
sunxi_system_off(void)98 static void __dead2 sunxi_system_off(void)
99 {
100 uint32_t ret;
101
102 gicv2_cpuif_disable();
103
104 /* Send the power down request to the SCP. */
105 ret = scpi_sys_power_state(scpi_system_shutdown);
106 if (ret != SCP_OK) {
107 ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret);
108 }
109
110 psci_power_down_wfi();
111 }
112
sunxi_system_reset(void)113 static void __dead2 sunxi_system_reset(void)
114 {
115 uint32_t ret;
116
117 gicv2_cpuif_disable();
118
119 /* Send the system reset request to the SCP. */
120 ret = scpi_sys_power_state(scpi_system_reboot);
121 if (ret != SCP_OK) {
122 ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret);
123 }
124
125 psci_power_down_wfi();
126 }
127
sunxi_system_reset2(int is_vendor,int reset_type,u_register_t cookie)128 static int sunxi_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
129 {
130 uint32_t ret;
131
132 if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET))
133 return PSCI_E_NOT_SUPPORTED;
134
135 gicv2_cpuif_disable();
136
137 /* Send the system reset request to the SCP. */
138 ret = scpi_sys_power_state(scpi_system_reset);
139 if (ret != SCP_OK) {
140 ERROR("PSCI: SCPI %s failed: %d\n", "reset", ret);
141 return PSCI_E_INVALID_PARAMS;
142 }
143
144 psci_power_down_wfi();
145
146 /*
147 * Should not reach here.
148 * However sunxi_system_reset2 has to return some value
149 * according to PSCI v1.1 spec.
150 */
151 return PSCI_E_SUCCESS;
152 }
153
sunxi_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)154 static int sunxi_validate_power_state(unsigned int power_state,
155 psci_power_state_t *req_state)
156 {
157 unsigned int power_level = psci_get_pstate_pwrlvl(power_state);
158 unsigned int state_id = psci_get_pstate_id(power_state);
159 unsigned int type = psci_get_pstate_type(power_state);
160 unsigned int i;
161
162 assert(req_state != NULL);
163
164 if (power_level > PLAT_MAX_PWR_LVL) {
165 return PSCI_E_INVALID_PARAMS;
166 }
167
168 if (type == PSTATE_TYPE_STANDBY) {
169 return PSCI_E_INVALID_PARAMS;
170 }
171
172 /* Pass through the requested PSCI state as-is. */
173 for (i = 0; i <= power_level; ++i) {
174 unsigned int local_pstate = state_id & PLAT_LOCAL_PSTATE_MASK;
175
176 req_state->pwr_domain_state[i] = local_pstate;
177 state_id >>= PLAT_LOCAL_PSTATE_WIDTH;
178 }
179
180 /* Higher power domain levels should all remain running */
181 for (; i <= PLAT_MAX_PWR_LVL; ++i) {
182 req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
183 }
184
185 return PSCI_E_SUCCESS;
186 }
187
sunxi_get_sys_suspend_power_state(psci_power_state_t * req_state)188 static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state)
189 {
190 assert(req_state != NULL);
191
192 for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) {
193 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
194 }
195 }
196
197 static const plat_psci_ops_t sunxi_scpi_psci_ops = {
198 .cpu_standby = sunxi_cpu_standby,
199 .pwr_domain_on = sunxi_pwr_domain_on,
200 .pwr_domain_off = sunxi_pwr_domain_off,
201 .pwr_domain_suspend = sunxi_pwr_domain_off,
202 .pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
203 .pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish,
204 .system_off = sunxi_system_off,
205 .system_reset = sunxi_system_reset,
206 .system_reset2 = sunxi_system_reset2,
207 .validate_power_state = sunxi_validate_power_state,
208 .validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
209 .get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state,
210 };
211
sunxi_set_scpi_psci_ops(const plat_psci_ops_t ** psci_ops)212 int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
213 {
214 *psci_ops = &sunxi_scpi_psci_ops;
215
216 /* Check for a valid SCP firmware. */
217 if (mmio_read_32(SUNXI_SCP_BASE) != SCP_FIRMWARE_MAGIC) {
218 return -1;
219 }
220
221 /* Program SCP exception vectors to the firmware entrypoint. */
222 for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
223 uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i);
224 uint32_t offset = SUNXI_SCP_BASE - vector;
225
226 mmio_write_32(vector, offset >> 2);
227 }
228
229 /* Take the SCP out of reset. */
230 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
231
232 /* Wait for the SCP firmware to boot. */
233 return scpi_wait_ready();
234 }
235
