1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2021 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_spi_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.spi_cmsis"
26 #endif
27
28 #if ((defined(RTE_SPI0) && RTE_SPI0) || (defined(RTE_SPI1) && RTE_SPI1))
29
30 #define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 3) /* driver version */
31
32 /*
33 * ARMCC does not support split the data section automatically, so the driver
34 * needs to split the data to separate sections explicitly, to reduce codesize.
35 */
36 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
37 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
38 #endif
39
40 static clock_ip_name_t const s_SPIClock[] = SPI_CLOCKS;
41
42 typedef const struct _cmsis_spi_resource
43 {
44 SPI_Type *base;
45 uint32_t instance;
46 uint32_t (*GetFreq)(void);
47 } cmsis_spi_resource_t;
48
49 typedef union _cmsis_spi_handle
50 {
51 spi_master_handle_t masterHandle;
52 spi_slave_handle_t slaveHandle;
53 } cmsis_spi_handle_t;
54
55 typedef struct _cmsis_spi_interrupt_driver_state
56 {
57 cmsis_spi_resource_t *resource;
58 cmsis_spi_handle_t *handle;
59 ARM_SPI_SignalEvent_t cb_event;
60 uint32_t baudRate_Bps;
61 uint8_t flags; /*!< Control and state flags. */
62 } cmsis_spi_interrupt_driver_state_t;
63
64 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
65
66 typedef const struct _cmsis_spi_dma_resource
67 {
68 DMA_Type *txdmaBase;
69 uint32_t txdmaChannel;
70 DMAMUX_Type *txDmamuxBase;
71 uint8_t txDmaRequest;
72
73 DMA_Type *rxdmaBase;
74 uint32_t rxdmaChannel;
75 DMAMUX_Type *rxDmamuxBase;
76 uint8_t rxDmaRequest;
77
78 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
79 uint32_t txdmamuxChannel;
80 uint32_t rxdmamuxChannel;
81 #endif
82 } cmsis_spi_dma_resource_t;
83
84 typedef union _cmsis_spi_dma_handle
85 {
86 spi_dma_handle_t masterHandle;
87 spi_dma_handle_t slaveHandle;
88 } cmsis_spi_dma_handle_t;
89
90 typedef struct _cmsis_spi_dma_driver_state
91 {
92 cmsis_spi_resource_t *resource;
93 cmsis_spi_dma_resource_t *dmaResource;
94 cmsis_spi_dma_handle_t *handle;
95 dma_handle_t *dmaRxDataHandle;
96 dma_handle_t *dmaTxDataHandle;
97
98 uint8_t flags; /*!< Control and state flags. */
99 uint32_t baudRate_Bps;
100 ARM_SPI_SignalEvent_t event;
101 } cmsis_SPI_dma_driver_state_t;
102 #endif
103
104 /* Driver Version */
105 static const ARM_DRIVER_VERSION s_SPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION};
106
107 /* Driver Capabilities */
108 static const ARM_SPI_CAPABILITIES s_SPIDriverCapabilities = {
109 1, /* Simplex Mode (Master and Slave) */
110 0, /* TI Synchronous Serial Interface */
111 0, /* Microwire Interface */
112 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
113 };
114
115 /*******************************************************************************
116 * Code
117 ******************************************************************************/
SPI_IsMaster(SPI_Type * base)118 static inline bool SPI_IsMaster(SPI_Type *base)
119 {
120 return ((base->C1 & (uint8_t)SPI_C1_MSTR_MASK) != 0U);
121 }
SPI_CommonControl(uint32_t control,uint32_t arg,cmsis_spi_resource_t * resource,uint8_t * isConfigured)122 static int32_t SPI_CommonControl(uint32_t control, uint32_t arg, cmsis_spi_resource_t *resource, uint8_t *isConfigured)
123 {
124 spi_master_config_t masterConfig;
125 SPI_MasterGetDefaultConfig(&masterConfig);
126 spi_slave_config_t slaveConfig;
127 SPI_SlaveGetDefaultConfig(&slaveConfig);
128 int32_t result = ARM_DRIVER_OK;
129
130 switch (control & ARM_SPI_CONTROL_Msk)
131 {
132 case ARM_SPI_MODE_MASTER_SIMPLEX:
133 masterConfig.pinMode = kSPI_PinModeOutput;
134 break;
135 case ARM_SPI_MODE_SLAVE_SIMPLEX:
136 slaveConfig.pinMode = kSPI_PinModeOutput;
137 break;
138 default:
139 /* Avoid MISRA 16.4 violations. */
140 break;
141 }
142 switch (control & ARM_SPI_FRAME_FORMAT_Msk)
143 {
144 case ARM_SPI_CPOL0_CPHA0:
145 if (SPI_IsMaster(resource->base))
146 {
147 masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
148
149 masterConfig.phase = kSPI_ClockPhaseFirstEdge;
150 }
151 else
152 {
153 slaveConfig.polarity = kSPI_ClockPolarityActiveHigh;
154
155 slaveConfig.phase = kSPI_ClockPhaseFirstEdge;
156 }
157 break;
158
159 case ARM_SPI_CPOL0_CPHA1:
160 if (SPI_IsMaster(resource->base))
161 {
162 masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
163 masterConfig.phase = kSPI_ClockPhaseSecondEdge;
164 }
165 else
166 {
167 slaveConfig.polarity = kSPI_ClockPolarityActiveHigh;
168 slaveConfig.phase = kSPI_ClockPhaseSecondEdge;
169 }
170 break;
171
172 case ARM_SPI_CPOL1_CPHA0:
173 if (SPI_IsMaster(resource->base))
174 {
175 masterConfig.polarity = kSPI_ClockPolarityActiveLow;
176 masterConfig.phase = kSPI_ClockPhaseFirstEdge;
177 }
178 else
179 {
180 slaveConfig.polarity = kSPI_ClockPolarityActiveLow;
181 slaveConfig.phase = kSPI_ClockPhaseFirstEdge;
182 }
183 break;
184
185 case ARM_SPI_CPOL1_CPHA1:
186 if (SPI_IsMaster(resource->base))
187 {
188 masterConfig.polarity = kSPI_ClockPolarityActiveLow;
189 masterConfig.phase = kSPI_ClockPhaseSecondEdge;
190 }
191 else
192 {
193 slaveConfig.polarity = kSPI_ClockPolarityActiveLow;
194 slaveConfig.phase = kSPI_ClockPhaseSecondEdge;
195 }
196 break;
197
198 default:
199 /* Avoid MISRA 16.4 violations. */
200 break;
201 }
202 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
203 if ((control & ARM_SPI_DATA_BITS_Msk) != 0U)
204 {
205 if (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) == 8U)
206 {
207 if (SPI_IsMaster(resource->base))
208 {
209 masterConfig.dataMode = kSPI_8BitMode;
210 }
211 else
212 {
213 slaveConfig.dataMode = kSPI_8BitMode;
214 }
215 }
216 else if (((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) == 16U)
217 {
218 if (SPI_IsMaster(resource->base))
219 {
220 masterConfig.dataMode = kSPI_16BitMode;
221 }
222 else
223 {
224 slaveConfig.dataMode = kSPI_16BitMode;
225 }
226 }
227 else
228 {
229 result = ARM_SPI_ERROR_DATA_BITS;
230 }
231 }
232 if (result != ARM_DRIVER_OK)
233 {
234 return result;
235 }
236 #endif
237 switch (control & ARM_SPI_BIT_ORDER_Msk)
238 {
239 case ARM_SPI_LSB_MSB:
240 if (SPI_IsMaster(resource->base))
241 {
242 masterConfig.direction = kSPI_LsbFirst;
243 }
244 else
245 {
246 slaveConfig.direction = kSPI_LsbFirst;
247 }
248 break;
249 case ARM_SPI_MSB_LSB:
250 if (SPI_IsMaster(resource->base))
251 {
252 masterConfig.direction = kSPI_MsbFirst;
253 }
254 else
255 {
256 slaveConfig.direction = kSPI_MsbFirst;
257 }
258
259 break;
260
261 default:
262 /* Avoid MISRA 16.4 violations. */
263 break;
264 }
265 if (SPI_IsMaster(resource->base))
266 {
267 switch (control & ARM_SPI_SS_MASTER_MODE_Msk)
268 {
269 case ARM_SPI_SS_MASTER_UNUSED:
270 masterConfig.outputMode = kSPI_SlaveSelectAsGpio; /*!< Slave select pin configured as GPIO. */
271 break;
272
273 case ARM_SPI_SS_MASTER_SW:
274 result = ARM_DRIVER_ERROR_UNSUPPORTED;
275 break;
276
277 case ARM_SPI_SS_MASTER_HW_OUTPUT:
278 masterConfig.outputMode =
279 kSPI_SlaveSelectAutomaticOutput; /*!< Slave select pin configured for automatic SPI output. */
280 break;
281
282 case ARM_SPI_SS_MASTER_HW_INPUT:
283 masterConfig.outputMode =
284 kSPI_SlaveSelectFaultInput; /*!< Slave select pin configured for fault detection. */
285 break;
286
287 default:
288 /* Avoid MISRA 16.4 violations. */
289 break;
290 }
291 }
292
293 if (result != ARM_DRIVER_OK)
294 {
295 return result;
296 }
297
298 if (SPI_IsMaster(resource->base))
299 {
300 if (((*isConfigured) & SPI_FLAG_CONFIGURED) != 0U)
301 {
302 SPI_Deinit(resource->base);
303 }
304 SPI_MasterInit(resource->base, &masterConfig, resource->GetFreq());
305 *isConfigured |= (uint8_t)SPI_FLAG_CONFIGURED;
306 }
307 else
308 {
309 if (((*isConfigured) & SPI_FLAG_CONFIGURED) != 0U)
310 {
311 SPI_Deinit(resource->base);
312 }
313 SPI_SlaveInit(resource->base, &slaveConfig);
314 *isConfigured |= (uint8_t)SPI_FLAG_CONFIGURED;
315 }
316
317 return ARM_DRIVER_OK;
318 }
319
SPIx_GetVersion(void)320 static ARM_DRIVER_VERSION SPIx_GetVersion(void)
321 {
322 return s_SPIDriverVersion;
323 }
324
SPIx_GetCapabilities(void)325 static ARM_SPI_CAPABILITIES SPIx_GetCapabilities(void)
326 {
327 return s_SPIDriverCapabilities;
328 }
329
330 #endif
331
332 #if ((defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN) || (defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN))
333
334 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
335
KSDK_SPI_MasterDMACallback(SPI_Type * base,spi_dma_handle_t * handle,status_t status,void * userData)336 static void KSDK_SPI_MasterDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
337 {
338 uint32_t event = 0U;
339
340 if (kStatus_Success == status)
341 {
342 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
343 }
344
345 if ((uint8_t)kStatus_SPI_Error == status)
346 {
347 event = ARM_SPI_EVENT_DATA_LOST;
348 }
349
350 if ((0U != event) && (userData != NULL))
351 {
352 ((ARM_SPI_SignalEvent_t)userData)(event);
353 }
354 }
KSDK_SPI_SlaveDMACallback(SPI_Type * base,spi_dma_handle_t * handle,status_t status,void * userData)355 static void KSDK_SPI_SlaveDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
356 {
357 uint32_t event = 0U;
358
359 if (kStatus_Success == status)
360 {
361 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
362 }
363
364 if ((uint8_t)kStatus_SPI_Error == status)
365 {
366 event = ARM_SPI_EVENT_DATA_LOST;
367 }
368 /* User data is actually CMSIS driver callback. */
369 if ((0U != event) && (userData != NULL))
370 {
371 ((ARM_SPI_SignalEvent_t)userData)(event);
372 }
373 }
374
SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_SPI_dma_driver_state_t * SPI)375 static int32_t SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_SPI_dma_driver_state_t *SPI)
376 {
377 if (0U == (SPI->flags & (uint8_t)SPI_FLAG_INIT))
378 {
379 SPI->event = cb_event;
380 SPI->flags = (uint8_t)SPI_FLAG_INIT;
381 }
382
383 return ARM_DRIVER_OK;
384 }
385
SPI_DMAUninitialize(cmsis_SPI_dma_driver_state_t * SPI)386 static int32_t SPI_DMAUninitialize(cmsis_SPI_dma_driver_state_t *SPI)
387 {
388 SPI->flags = (uint8_t)SPI_FLAG_UNINIT;
389 return ARM_DRIVER_OK;
390 }
391
SPI_DMAPowerControl(ARM_POWER_STATE state,cmsis_SPI_dma_driver_state_t * SPI)392 static int32_t SPI_DMAPowerControl(ARM_POWER_STATE state, cmsis_SPI_dma_driver_state_t *SPI)
393 {
394 switch (state)
395 {
396 case ARM_POWER_OFF:
397 if ((SPI->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
398 {
399 SPI_Deinit(SPI->resource->base);
400 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
401 DMAMUX_DisableChannel(SPI->dmaResource->rxDmamuxBase, SPI->dmaResource->rxdmamuxChannel);
402 DMAMUX_DisableChannel(SPI->dmaResource->txDmamuxBase, SPI->dmaResource->txdmamuxChannel);
403 #else
404 DMAMUX_DisableChannel(SPI->dmaResource->rxDmamuxBase, SPI->dmaResource->rxdmaChannel);
405 DMAMUX_DisableChannel(SPI->dmaResource->txDmamuxBase, SPI->dmaResource->txdmaChannel);
406 #endif
407 SPI->flags = (uint8_t)SPI_FLAG_INIT;
408 }
409 break;
410 case ARM_POWER_LOW:
411 return ARM_DRIVER_ERROR_UNSUPPORTED;
412
413 case ARM_POWER_FULL:
414 if (SPI->flags == (uint8_t)SPI_FLAG_UNINIT)
415 {
416 return ARM_DRIVER_ERROR;
417 }
418
419 if ((SPI->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
420 {
421 /* Driver already powered */
422 break;
423 }
424 /* Enable Clock gate */
425 CLOCK_EnableClock(s_SPIClock[SPI->resource->instance]);
426 SPI->flags |= (uint8_t)SPI_FLAG_POWER;
427 break;
428 default:
429 return ARM_DRIVER_ERROR_UNSUPPORTED;
430 }
431 return ARM_DRIVER_OK;
432 }
433
SPI_DMASend(const void * data,uint32_t num,cmsis_SPI_dma_driver_state_t * SPI)434 static int32_t SPI_DMASend(const void *data, uint32_t num, cmsis_SPI_dma_driver_state_t *SPI)
435 {
436 int32_t ret;
437 status_t status;
438 spi_transfer_t xfer = {0};
439
440 xfer.rxData = NULL;
441 xfer.txData = (uint8_t *)data;
442 xfer.dataSize = num;
443 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
444 if ((SPI->resource->base->C2 & (uint8_t)SPI_C2_SPIMODE_MASK) != 0U)
445 {
446 xfer.dataSize *= 2U;
447 }
448 #endif
449
450 /* If transfer mode is single wire. */
451 if (((uint8_t)SPI_C2_SPC0_MASK & SPI->resource->base->C2) != 0U)
452 {
453 SPI_SetPinMode(SPI->resource->base, kSPI_PinModeOutput);
454 }
455
456 if (SPI_IsMaster(SPI->resource->base))
457 {
458 status = SPI_MasterTransferDMA(SPI->resource->base, &SPI->handle->masterHandle, &xfer);
459 }
460 else
461 {
462 status = SPI_SlaveTransferDMA(SPI->resource->base, &SPI->handle->slaveHandle, &xfer);
463 }
464
465 switch (status)
466 {
467 case kStatus_Success:
468 ret = ARM_DRIVER_OK;
469 break;
470 case kStatus_InvalidArgument:
471 ret = ARM_DRIVER_ERROR_PARAMETER;
472 break;
473 case kStatus_SPI_Busy:
474 ret = ARM_DRIVER_ERROR_BUSY;
475 break;
476 default:
477 ret = ARM_DRIVER_ERROR;
478 break;
479 }
480
481 return ret;
482 }
483
SPI_DMAReceive(void * data,uint32_t num,cmsis_SPI_dma_driver_state_t * SPI)484 static int32_t SPI_DMAReceive(void *data, uint32_t num, cmsis_SPI_dma_driver_state_t *SPI)
485 {
486 int32_t ret;
487 status_t status;
488 spi_transfer_t xfer = {0};
489
490 xfer.txData = NULL;
491 xfer.rxData = (uint8_t *)data;
492 xfer.dataSize = num;
493 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
494 if ((SPI->resource->base->C2 & (uint8_t)SPI_C2_SPIMODE_MASK) != 0U)
495 {
496 xfer.dataSize *= 2U;
497 }
498 #endif
499
500 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO)
501 /* If using DMA, disable FIFO, as the FIFO may cause data loss if the data size is not integer
502 times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO
503 size. */
504 if (FSL_FEATURE_SPI_FIFO_SIZEn(SPI->resource->base) != 0)
505 {
506 SPI->resource->base->C3 &= ~(uint8_t)SPI_C3_FIFOMODE_MASK;
507 }
508 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
509
510 /* If transfer mode is single wire. */
511 if (((uint8_t)SPI_C2_SPC0_MASK & SPI->resource->base->C2) != 0U)
512 {
513 SPI_SetPinMode(SPI->resource->base, kSPI_PinModeInput);
514 }
515
516 if (SPI_IsMaster(SPI->resource->base))
517 {
518 status = SPI_MasterTransferDMA(SPI->resource->base, &SPI->handle->masterHandle, &xfer);
519 }
520 else
521 {
522 status = SPI_SlaveTransferDMA(SPI->resource->base, &SPI->handle->slaveHandle, &xfer);
523 }
524
525 switch (status)
526 {
527 case kStatus_Success:
528 ret = ARM_DRIVER_OK;
529 break;
530 case kStatus_InvalidArgument:
531 ret = ARM_DRIVER_ERROR_PARAMETER;
532 break;
533 case kStatus_SPI_Busy:
534 ret = ARM_DRIVER_ERROR_BUSY;
535 break;
536 default:
537 ret = ARM_DRIVER_ERROR;
538 break;
539 }
540
541 return ret;
542 }
543
SPI_DMATransfer(const void * data_out,void * data_in,uint32_t num,cmsis_SPI_dma_driver_state_t * SPI)544 static int32_t SPI_DMATransfer(const void *data_out, void *data_in, uint32_t num, cmsis_SPI_dma_driver_state_t *SPI)
545 {
546 int32_t ret;
547 status_t status;
548 spi_transfer_t xfer = {0};
549
550 if ((NULL == data_in) && (NULL == data_out))
551 {
552 return ARM_DRIVER_ERROR_PARAMETER;
553 }
554
555 xfer.txData = (uint8_t *)data_out;
556 xfer.rxData = (uint8_t *)data_in;
557 xfer.dataSize = num;
558 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
559 if ((SPI->resource->base->C2 & (uint8_t)SPI_C2_SPIMODE_MASK) != 0U)
560 {
561 xfer.dataSize *= 2U;
562 }
563 #endif
564
565 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO)
566 /* If using DMA, disable FIFO, as the FIFO may cause data loss if the data size is not integer
567 times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO
568 size. */
569 if (FSL_FEATURE_SPI_FIFO_SIZEn(SPI->resource->base) != 0)
570 {
571 SPI->resource->base->C3 &= ~(uint8_t)SPI_C3_FIFOMODE_MASK;
572 }
573 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
574
575 /* If transfer mode is single wire. */
576 if (((uint8_t)SPI_C2_SPC0_MASK & SPI->resource->base->C2) != 0U)
577 {
578 if (NULL == data_out)
579 {
580 SPI_SetPinMode(SPI->resource->base, kSPI_PinModeInput);
581 }
582 if (NULL == data_in)
583 {
584 SPI_SetPinMode(SPI->resource->base, kSPI_PinModeOutput);
585 }
586 }
587
588 if (SPI_IsMaster(SPI->resource->base))
589 {
590 status = SPI_MasterTransferDMA(SPI->resource->base, &SPI->handle->masterHandle, &xfer);
591 }
592 else
593 {
594 status = SPI_SlaveTransferDMA(SPI->resource->base, &SPI->handle->slaveHandle, &xfer);
595 }
596
597 switch (status)
598 {
599 case kStatus_Success:
600 ret = ARM_DRIVER_OK;
601 break;
602 case kStatus_InvalidArgument:
603 ret = ARM_DRIVER_ERROR_PARAMETER;
604 break;
605 case kStatus_SPI_Busy:
606 ret = ARM_DRIVER_ERROR_BUSY;
607 break;
608 default:
609 ret = ARM_DRIVER_ERROR;
610 break;
611 }
612
613 return ret;
614 }
SPI_DMAGetCount(cmsis_SPI_dma_driver_state_t * SPI)615 static uint32_t SPI_DMAGetCount(cmsis_SPI_dma_driver_state_t *SPI)
616 {
617 uint32_t cnt;
618 size_t bytes;
619
620 bytes = DMA_GetRemainingBytes(SPI->dmaResource->rxdmaBase, SPI->dmaResource->rxdmaChannel);
621
622 if (SPI_IsMaster(SPI->resource->base))
623 {
624 cnt = SPI->handle->masterHandle.transferSize - bytes;
625 }
626 else
627 {
628 cnt = SPI->handle->slaveHandle.transferSize - bytes;
629 }
630 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
631 if ((SPI->resource->base->C2 & (uint8_t)SPI_C2_SPIMODE_MASK) != 0U)
632 {
633 cnt /= 2U;
634 }
635 #endif
636 return cnt;
637 }
638
SPI_DMAControl(uint32_t control,uint32_t arg,cmsis_SPI_dma_driver_state_t * SPI)639 static int32_t SPI_DMAControl(uint32_t control, uint32_t arg, cmsis_SPI_dma_driver_state_t *SPI)
640 {
641 if (0U == (SPI->flags & (uint8_t)SPI_FLAG_POWER))
642 {
643 return ARM_DRIVER_ERROR;
644 }
645
646 cmsis_spi_dma_resource_t *dmaResource = SPI->dmaResource;
647
648 switch (control & ARM_SPI_CONTROL_Msk)
649 {
650 case ARM_SPI_MODE_INACTIVE:
651 SPI_Enable(SPI->resource->base, false);
652 break;
653
654 case ARM_SPI_MODE_MASTER:
655 SPI->resource->base->C1 |= (uint8_t)SPI_C1_MSTR_MASK;
656
657 (void)memset(SPI->dmaRxDataHandle, 0, sizeof(dma_handle_t));
658 (void)memset(SPI->dmaTxDataHandle, 0, sizeof(dma_handle_t));
659
660 DMA_CreateHandle(SPI->dmaRxDataHandle, dmaResource->rxdmaBase, dmaResource->rxdmaChannel);
661 DMA_CreateHandle(SPI->dmaTxDataHandle, dmaResource->txdmaBase, dmaResource->txdmaChannel);
662 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
663 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxdmamuxChannel, (int32_t)dmaResource->rxDmaRequest);
664 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxdmamuxChannel);
665
666 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txdmamuxChannel, (int32_t)dmaResource->txDmaRequest);
667 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txdmamuxChannel);
668 #else
669 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxdmaChannel, (int32_t)dmaResource->rxDmaRequest);
670 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxdmaChannel);
671
672 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txdmaChannel, (int32_t)dmaResource->txDmaRequest);
673 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txdmaChannel);
674 #endif
675 SPI_MasterTransferCreateHandleDMA(SPI->resource->base, &SPI->handle->masterHandle,
676 KSDK_SPI_MasterDMACallback, (void *)SPI->event, SPI->dmaTxDataHandle,
677 SPI->dmaRxDataHandle);
678
679 SPI->baudRate_Bps = arg;
680 SPI->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
681 break;
682
683 case ARM_SPI_MODE_SLAVE:
684 SPI->resource->base->C1 &= ~(uint8_t)SPI_C1_MSTR_MASK;
685
686 (void)memset(SPI->dmaRxDataHandle, 0, sizeof(dma_handle_t));
687 (void)memset(SPI->dmaTxDataHandle, 0, sizeof(dma_handle_t));
688
689 DMA_CreateHandle(SPI->dmaTxDataHandle, dmaResource->txdmaBase, dmaResource->txdmaChannel);
690 DMA_CreateHandle(SPI->dmaRxDataHandle, dmaResource->rxdmaBase, dmaResource->rxdmaChannel);
691 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
692 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txdmamuxChannel, (int32_t)dmaResource->txDmaRequest);
693 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txdmamuxChannel);
694
695 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxdmamuxChannel, (int32_t)dmaResource->rxDmaRequest);
696 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxdmamuxChannel);
697 #else
698 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txdmaChannel, (int32_t)dmaResource->txDmaRequest);
699 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txdmaChannel);
700
701 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxdmaChannel, (int32_t)dmaResource->rxDmaRequest);
702 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxdmaChannel);
703 #endif
704 SPI_SlaveTransferCreateHandleDMA(SPI->resource->base, &SPI->handle->slaveHandle, KSDK_SPI_SlaveDMACallback,
705 (void *)SPI->event, SPI->dmaTxDataHandle, SPI->dmaRxDataHandle);
706
707 SPI->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
708 break;
709
710 case ARM_SPI_SET_BUS_SPEED:
711 if (!SPI_IsMaster(SPI->resource->base))
712 {
713 return ARM_DRIVER_ERROR_UNSUPPORTED;
714 }
715
716 SPI_MasterSetBaudRate(SPI->resource->base, arg, SPI->resource->GetFreq());
717
718 SPI->baudRate_Bps = arg;
719 return ARM_DRIVER_OK;
720
721 case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */
722 if (!SPI_IsMaster(SPI->resource->base))
723 {
724 return ARM_DRIVER_ERROR_UNSUPPORTED;
725 }
726
727 return (int32_t)SPI->baudRate_Bps;
728
729 case ARM_SPI_CONTROL_SS:
730 return ARM_DRIVER_ERROR_UNSUPPORTED;
731
732 case ARM_SPI_ABORT_TRANSFER:
733 if (SPI_IsMaster(SPI->resource->base))
734 {
735 SPI_MasterTransferAbortDMA(SPI->resource->base, &SPI->handle->masterHandle);
736 }
737 else
738 {
739 SPI_SlaveTransferAbortDMA(SPI->resource->base, &SPI->handle->slaveHandle);
740 }
741 return ARM_DRIVER_OK;
742
743 case ARM_SPI_MODE_MASTER_SIMPLEX:
744 SPI->resource->base->C1 |= (uint8_t)SPI_C1_MSTR_MASK;
745
746 (void)memset(SPI->dmaRxDataHandle, 0, sizeof(dma_handle_t));
747 (void)memset(SPI->dmaTxDataHandle, 0, sizeof(dma_handle_t));
748
749 DMA_CreateHandle(SPI->dmaRxDataHandle, dmaResource->rxdmaBase, dmaResource->rxdmaChannel);
750 DMA_CreateHandle(SPI->dmaTxDataHandle, dmaResource->txdmaBase, dmaResource->txdmaChannel);
751 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
752 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxdmamuxChannel, (int32_t)dmaResource->rxDmaRequest);
753 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxdmamuxChannel);
754
755 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txdmamuxChannel, (int32_t)dmaResource->txDmaRequest);
756 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txdmamuxChannel);
757 #else
758 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxdmaChannel, (int32_t)dmaResource->rxDmaRequest);
759 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxdmaChannel);
760
761 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txdmaChannel, (int32_t)dmaResource->txDmaRequest);
762 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txdmaChannel);
763 #endif
764 SPI_MasterTransferCreateHandleDMA(SPI->resource->base, &SPI->handle->masterHandle,
765 KSDK_SPI_MasterDMACallback, (void *)SPI->event, SPI->dmaTxDataHandle,
766 SPI->dmaRxDataHandle);
767
768 SPI->baudRate_Bps = arg;
769 SPI->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
770 break;
771
772 case ARM_SPI_MODE_SLAVE_SIMPLEX:
773 SPI->resource->base->C1 &= ~(uint8_t)SPI_C1_MSTR_MASK;
774
775 (void)memset(SPI->dmaRxDataHandle, 0, sizeof(dma_handle_t));
776 (void)memset(SPI->dmaTxDataHandle, 0, sizeof(dma_handle_t));
777
778 DMA_CreateHandle(SPI->dmaTxDataHandle, dmaResource->txdmaBase, dmaResource->txdmaChannel);
779 DMA_CreateHandle(SPI->dmaRxDataHandle, dmaResource->rxdmaBase, dmaResource->rxdmaChannel);
780 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
781 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txdmamuxChannel, (int32_t)dmaResource->txDmaRequest);
782 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txdmamuxChannel);
783
784 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxdmamuxChannel, (int32_t)dmaResource->rxDmaRequest);
785 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxdmamuxChannel);
786 #else
787 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txdmaChannel, (int32_t)dmaResource->txDmaRequest);
788 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txdmaChannel);
789
790 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxdmaChannel, (int32_t)dmaResource->rxDmaRequest);
791 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxdmaChannel);
792 #endif
793 SPI_SlaveTransferCreateHandleDMA(SPI->resource->base, &SPI->handle->slaveHandle, KSDK_SPI_SlaveDMACallback,
794 (void *)SPI->event, SPI->dmaTxDataHandle, SPI->dmaRxDataHandle);
795
796 SPI->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
797 break;
798
799 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
800 SPI_SetDummyData(SPI->resource->base, (uint8_t)arg);
801 return ARM_DRIVER_OK;
802
803 default:
804 /* Avoid MISRA 16.4 violation */
805 break;
806 }
807
808 return SPI_CommonControl(control, arg, SPI->resource, &SPI->flags);
809 }
810
SPI_DMAGetStatus(cmsis_SPI_dma_driver_state_t * SPI)811 static ARM_SPI_STATUS SPI_DMAGetStatus(cmsis_SPI_dma_driver_state_t *SPI)
812 {
813 ARM_SPI_STATUS stat = {0};
814
815 if (SPI_IsMaster(SPI->resource->base))
816 {
817 stat.busy =
818 ((SPI->handle->masterHandle.txInProgress == true) || (SPI->handle->masterHandle.rxInProgress == true)) ?
819 (0U) :
820 (1U);
821 }
822 else
823 {
824 stat.busy =
825 ((SPI->handle->slaveHandle.txInProgress == true) || (SPI->handle->slaveHandle.rxInProgress == true)) ?
826 (0U) :
827 (1U);
828 }
829 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
830 stat.data_lost = (((SPI_GetStatusFlags(SPI->resource->base) & (uint32_t)kSPI_RxOverflow) != 0U) ||
831 ((SPI_GetStatusFlags(SPI->resource->base) & (uint32_t)kSPI_TxOverflow) != 0U)) ?
832 (1U) :
833 (0U);
834 #else
835 stat.data_lost = ((uint8_t)kStatus_SPI_Error == SPI->handle->slaveHandle.state) ? (1U) : (0U);
836 #endif
837
838 stat.mode_fault = 0U;
839 stat.reserved = 0U;
840
841 return stat;
842 }
843 #endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */
844
845 #endif
846
847 #if ((defined(RTE_SPI0) && RTE_SPI0 && !(defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN)) || \
848 (defined(RTE_SPI1) && RTE_SPI1 && !(defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN)))
849
KSDK_SPI_MasterInterruptCallback(SPI_Type * base,spi_master_handle_t * handle,status_t status,void * userData)850 static void KSDK_SPI_MasterInterruptCallback(SPI_Type *base,
851 spi_master_handle_t *handle,
852 status_t status,
853 void *userData)
854 {
855 uint32_t event = 0U;
856
857 if ((kStatus_Success == status) || (kStatus_SPI_Idle == status))
858 {
859 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
860 }
861
862 if (kStatus_SPI_Error == status)
863 {
864 event = ARM_SPI_EVENT_DATA_LOST;
865 }
866
867 /* User data is actually CMSIS driver callback. */
868 if ((0U != event) && (userData != NULL))
869 {
870 ((ARM_SPI_SignalEvent_t)userData)(event);
871 }
872 }
873
KSDK_SPI_SlaveInterruptCallback(SPI_Type * base,spi_slave_handle_t * handle,status_t status,void * userData)874 static void KSDK_SPI_SlaveInterruptCallback(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData)
875 {
876 uint32_t event = 0U;
877
878 if ((kStatus_Success == status) || (kStatus_SPI_Idle == status))
879 {
880 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
881 }
882
883 if (kStatus_SPI_Error == status)
884 {
885 event = ARM_SPI_EVENT_DATA_LOST;
886 }
887
888 /* User data is actually CMSIS driver callback. */
889 if ((0U != event) && (userData != NULL))
890 {
891 ((ARM_SPI_SignalEvent_t)userData)(event);
892 }
893 }
894
SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_spi_interrupt_driver_state_t * SPI)895 static int32_t SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_interrupt_driver_state_t *SPI)
896 {
897 if (0U == (SPI->flags & (uint8_t)SPI_FLAG_INIT))
898 {
899 SPI->cb_event = cb_event;
900 SPI->flags = (uint8_t)SPI_FLAG_INIT;
901 }
902 return ARM_DRIVER_OK;
903 }
904
SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t * SPI)905 static int32_t SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t *SPI)
906 {
907 SPI->flags = (uint8_t)SPI_FLAG_UNINIT;
908 return ARM_DRIVER_OK;
909 }
910
SPI_InterruptPowerControl(ARM_POWER_STATE state,cmsis_spi_interrupt_driver_state_t * SPI)911 static int32_t SPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_spi_interrupt_driver_state_t *SPI)
912 {
913 int32_t result = ARM_DRIVER_OK;
914 switch (state)
915 {
916 case ARM_POWER_OFF:
917 if ((SPI->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
918 {
919 SPI_Deinit(SPI->resource->base);
920 SPI->flags = (uint8_t)SPI_FLAG_INIT;
921 }
922 break;
923
924 case ARM_POWER_LOW:
925 result = ARM_DRIVER_ERROR_UNSUPPORTED;
926 break;
927
928 case ARM_POWER_FULL:
929 if (SPI->flags == (uint8_t)SPI_FLAG_UNINIT)
930 {
931 return ARM_DRIVER_ERROR;
932 }
933
934 if ((SPI->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
935 {
936 /* Driver already powered */
937 break;
938 }
939
940 CLOCK_EnableClock(s_SPIClock[SPI->resource->instance]);
941 SPI->flags |= (uint8_t)SPI_FLAG_POWER;
942 break;
943 default:
944 result = ARM_DRIVER_ERROR_UNSUPPORTED;
945 break;
946 }
947 return result;
948 }
949
SPI_InterruptSend(const void * data,uint32_t num,cmsis_spi_interrupt_driver_state_t * SPI)950 static int32_t SPI_InterruptSend(const void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *SPI)
951 {
952 int32_t ret;
953 status_t status;
954 spi_transfer_t xfer = {0};
955
956 xfer.rxData = NULL;
957 xfer.txData = (uint8_t *)data;
958 xfer.dataSize = num;
959 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
960 if ((SPI->resource->base->C2 & (uint8_t)SPI_C2_SPIMODE_MASK) != 0U)
961 {
962 xfer.dataSize *= 2U;
963 }
964 #endif
965
966 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO)
967 /* If using DMA, disable FIFO, as the FIFO may cause data loss if the data size is not integer
968 times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO
969 size. */
970 if (FSL_FEATURE_SPI_FIFO_SIZEn(SPI->resource->base) != 0)
971 {
972 SPI->resource->base->C3 &= ~(uint8_t)SPI_C3_FIFOMODE_MASK;
973 }
974 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
975
976 /* If transfer mode is single wire. */
977 if (((uint8_t)SPI_C2_SPC0_MASK & SPI->resource->base->C2) != 0U)
978 {
979 SPI_SetPinMode(SPI->resource->base, kSPI_PinModeOutput);
980 }
981
982 if (SPI_IsMaster(SPI->resource->base))
983 {
984 status = SPI_MasterTransferNonBlocking(SPI->resource->base, &SPI->handle->masterHandle, &xfer);
985 }
986 else
987 {
988 status = SPI_SlaveTransferNonBlocking(SPI->resource->base, &SPI->handle->slaveHandle, &xfer);
989 }
990
991 switch (status)
992 {
993 case kStatus_Success:
994 ret = ARM_DRIVER_OK;
995 break;
996 case kStatus_InvalidArgument:
997 ret = ARM_DRIVER_ERROR_PARAMETER;
998 break;
999 case kStatus_SPI_Busy:
1000 ret = ARM_DRIVER_ERROR_BUSY;
1001 break;
1002 default:
1003 ret = ARM_DRIVER_ERROR;
1004 break;
1005 }
1006
1007 return ret;
1008 }
1009
SPI_InterruptReceive(void * data,uint32_t num,cmsis_spi_interrupt_driver_state_t * SPI)1010 static int32_t SPI_InterruptReceive(void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *SPI)
1011 {
1012 int32_t ret;
1013 status_t status;
1014 spi_transfer_t xfer = {0};
1015
1016 xfer.txData = NULL;
1017 xfer.rxData = (uint8_t *)data;
1018 xfer.dataSize = num;
1019 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
1020 if ((SPI->resource->base->C2 & (uint8_t)SPI_C2_SPIMODE_MASK) != 0U)
1021 {
1022 xfer.dataSize *= 2U;
1023 }
1024 #endif
1025
1026 /* If transfer mode is single wire. */
1027 if (((uint8_t)SPI_C2_SPC0_MASK & SPI->resource->base->C2) != 0U)
1028 {
1029 SPI_SetPinMode(SPI->resource->base, kSPI_PinModeInput);
1030 }
1031
1032 if (SPI_IsMaster(SPI->resource->base))
1033 {
1034 status = SPI_MasterTransferNonBlocking(SPI->resource->base, &SPI->handle->masterHandle, &xfer);
1035 }
1036 else
1037 {
1038 status = SPI_SlaveTransferNonBlocking(SPI->resource->base, &SPI->handle->slaveHandle, &xfer);
1039 }
1040
1041 switch (status)
1042 {
1043 case kStatus_Success:
1044 ret = ARM_DRIVER_OK;
1045 break;
1046 case kStatus_InvalidArgument:
1047 ret = ARM_DRIVER_ERROR_PARAMETER;
1048 break;
1049 case kStatus_SPI_Busy:
1050 ret = ARM_DRIVER_ERROR_BUSY;
1051 break;
1052 default:
1053 ret = ARM_DRIVER_ERROR;
1054 break;
1055 }
1056
1057 return ret;
1058 }
1059
SPI_InterruptTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_spi_interrupt_driver_state_t * SPI)1060 static int32_t SPI_InterruptTransfer(const void *data_out,
1061 void *data_in,
1062 uint32_t num,
1063 cmsis_spi_interrupt_driver_state_t *SPI)
1064 {
1065 int32_t ret;
1066 status_t status;
1067 spi_transfer_t xfer = {0};
1068
1069 if ((NULL == data_in) && (NULL == data_out))
1070 {
1071 return ARM_DRIVER_ERROR_PARAMETER;
1072 }
1073
1074 xfer.txData = (uint8_t *)data_out;
1075 xfer.rxData = (uint8_t *)data_in;
1076 xfer.dataSize = num;
1077 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
1078 if ((SPI->resource->base->C2 & (uint8_t)SPI_C2_SPIMODE_MASK) != 0U)
1079 {
1080 xfer.dataSize *= 2U;
1081 }
1082 #endif
1083
1084 /* If transfer mode is single wire. */
1085 if (((uint8_t)SPI_C2_SPC0_MASK & SPI->resource->base->C2) != 0U)
1086 {
1087 if (NULL == data_out)
1088 {
1089 SPI_SetPinMode(SPI->resource->base, kSPI_PinModeInput);
1090 }
1091 if (NULL == data_in)
1092 {
1093 SPI_SetPinMode(SPI->resource->base, kSPI_PinModeOutput);
1094 }
1095 }
1096
1097 if (SPI_IsMaster(SPI->resource->base))
1098 {
1099 status = SPI_MasterTransferNonBlocking(SPI->resource->base, &SPI->handle->masterHandle, &xfer);
1100 }
1101 else
1102 {
1103 status = SPI_SlaveTransferNonBlocking(SPI->resource->base, &SPI->handle->slaveHandle, &xfer);
1104 }
1105
1106 switch (status)
1107 {
1108 case kStatus_Success:
1109 ret = ARM_DRIVER_OK;
1110 break;
1111 case kStatus_InvalidArgument:
1112 ret = ARM_DRIVER_ERROR_PARAMETER;
1113 break;
1114 case kStatus_SPI_Busy:
1115 ret = ARM_DRIVER_ERROR_BUSY;
1116 break;
1117 default:
1118 ret = ARM_DRIVER_ERROR;
1119 break;
1120 }
1121
1122 return ret;
1123 }
SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t * SPI)1124 static uint32_t SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t *SPI)
1125 {
1126 uint32_t cnt;
1127 if (SPI_IsMaster(SPI->resource->base))
1128 {
1129 cnt = SPI->handle->masterHandle.transferSize - SPI->handle->masterHandle.rxRemainingBytes;
1130 }
1131 else
1132 {
1133 cnt = SPI->handle->slaveHandle.transferSize - SPI->handle->slaveHandle.rxRemainingBytes;
1134 }
1135 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
1136 if ((SPI->resource->base->C2 & (uint8_t)SPI_C2_SPIMODE_MASK) != 0U)
1137 {
1138 cnt /= 2U;
1139 }
1140 #endif
1141 return cnt;
1142 }
1143
SPI_InterruptControl(uint32_t control,uint32_t arg,cmsis_spi_interrupt_driver_state_t * SPI)1144 static int32_t SPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_spi_interrupt_driver_state_t *SPI)
1145 {
1146 int32_t result = ARM_DRIVER_OK;
1147 bool isContinue = false;
1148 if (0U == (SPI->flags & (uint8_t)SPI_FLAG_POWER))
1149 {
1150 return ARM_DRIVER_ERROR;
1151 }
1152
1153 switch (control & ARM_SPI_CONTROL_Msk)
1154 {
1155 case ARM_SPI_MODE_INACTIVE: /* SPI Inactive */
1156 SPI_Enable(SPI->resource->base, false);
1157 isContinue = true;
1158 break;
1159
1160 case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */
1161 SPI->resource->base->C1 |= (uint8_t)SPI_C1_MSTR_MASK;
1162 SPI_MasterTransferCreateHandle(SPI->resource->base, &SPI->handle->masterHandle,
1163 KSDK_SPI_MasterInterruptCallback, (void *)SPI->cb_event);
1164 SPI->baudRate_Bps = arg;
1165 SPI->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1166 isContinue = true;
1167 break;
1168
1169 case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on MISO, Input on MOSI) */
1170 SPI->resource->base->C1 &= ~(uint8_t)SPI_C1_MSTR_MASK;
1171 SPI_SlaveTransferCreateHandle(SPI->resource->base, &SPI->handle->slaveHandle,
1172 KSDK_SPI_SlaveInterruptCallback, (void *)SPI->cb_event);
1173 SPI->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1174 isContinue = true;
1175 break;
1176
1177 case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */
1178 if (!SPI_IsMaster(SPI->resource->base))
1179 {
1180 return ARM_DRIVER_ERROR_UNSUPPORTED;
1181 }
1182 result = (int32_t)SPI->baudRate_Bps;
1183 break;
1184
1185 case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */
1186 if (!SPI_IsMaster(SPI->resource->base))
1187 {
1188 return ARM_DRIVER_ERROR_UNSUPPORTED;
1189 }
1190
1191 SPI_MasterSetBaudRate(SPI->resource->base, arg, SPI->resource->GetFreq());
1192
1193 SPI->baudRate_Bps = arg;
1194 break;
1195
1196 case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */
1197 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1198 break;
1199
1200 case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */
1201 if (SPI_IsMaster(SPI->resource->base))
1202 {
1203 SPI_MasterTransferAbort(SPI->resource->base, &SPI->handle->masterHandle);
1204 }
1205 else
1206 {
1207 SPI_SlaveTransferAbort(SPI->resource->base, &SPI->handle->slaveHandle);
1208 }
1209 break;
1210
1211 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
1212 SPI->resource->base->C1 |= (uint8_t)SPI_C1_MSTR_MASK;
1213 SPI_MasterTransferCreateHandle(SPI->resource->base, &SPI->handle->masterHandle,
1214 KSDK_SPI_MasterInterruptCallback, (void *)SPI->cb_event);
1215 SPI->baudRate_Bps = arg;
1216 SPI->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1217 isContinue = true;
1218 break;
1219
1220 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */
1221 SPI->resource->base->C1 &= ~(uint8_t)SPI_C1_MSTR_MASK;
1222 SPI_SlaveTransferCreateHandle(SPI->resource->base, &SPI->handle->slaveHandle,
1223 KSDK_SPI_SlaveInterruptCallback, (void *)SPI->cb_event);
1224 SPI->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1225 isContinue = true;
1226 break;
1227
1228 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
1229 SPI_SetDummyData(SPI->resource->base, (uint8_t)arg);
1230 result = ARM_DRIVER_OK;
1231 break;
1232
1233 default:
1234 isContinue = true;
1235 /* Avoid MISRA 16.4 violation */
1236 break;
1237 }
1238
1239 if (isContinue)
1240 {
1241 return SPI_CommonControl(control, arg, SPI->resource, &SPI->flags);
1242 }
1243 else
1244 {
1245 return result;
1246 }
1247 }
1248
SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t * SPI)1249 static ARM_SPI_STATUS SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t *SPI)
1250 {
1251 ARM_SPI_STATUS stat = {0};
1252
1253 if (SPI_IsMaster(SPI->resource->base))
1254 {
1255 stat.busy =
1256 ((SPI->handle->masterHandle.txRemainingBytes > 0U) || (SPI->handle->masterHandle.rxRemainingBytes > 0U)) ?
1257 (0U) :
1258 (1U);
1259 }
1260 else
1261 {
1262 stat.busy =
1263 ((SPI->handle->slaveHandle.txRemainingBytes > 0U) || (SPI->handle->slaveHandle.rxRemainingBytes > 0U)) ?
1264 (0U) :
1265 (1U);
1266 }
1267 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
1268 stat.data_lost = (((SPI_GetStatusFlags(SPI->resource->base) & (uint32_t)kSPI_RxOverflow) != 0U) ||
1269 ((SPI_GetStatusFlags(SPI->resource->base) & (uint32_t)kSPI_TxOverflow) != 0U)) ?
1270 (1U) :
1271 (0U);
1272 #else
1273 stat.data_lost = ((uint8_t)kStatus_SPI_Error == SPI->handle->slaveHandle.state) ? (1U) : (0U);
1274 #endif
1275 stat.mode_fault = 0U;
1276 stat.reserved = 0U;
1277
1278 return stat;
1279 }
1280
1281 #endif
1282
1283 #if defined(SPI0) && defined(RTE_SPI0) && RTE_SPI0
1284
1285 /* User needs to provide the implementation for SPI0_GetFreq/InitPins/DeinitPins
1286 in the application for enabling according instance. */
1287 extern uint32_t SPI0_GetFreq(void);
1288
1289 static cmsis_spi_resource_t SPI0_Resource = {SPI0, 0, SPI0_GetFreq};
1290
1291 #if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
1292
1293 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1294 static cmsis_spi_dma_resource_t SPI0_DMAResource = {
1295 RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, RTE_SPI0_DMA_TX_DMAMUX_BASE, RTE_SPI0_DMA_TX_PERI_SEL,
1296
1297 RTE_SPI0_DMA_RX_DMA_BASE, RTE_SPI0_DMA_RX_CH, RTE_SPI0_DMA_RX_DMAMUX_BASE, RTE_SPI0_DMA_RX_PERI_SEL,
1298 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
1299 RTE_SPI0_DMAMUX_TX_CH, RTE_SPI0_DMAMUX_RX_CH
1300 #endif
1301 };
1302
1303 static cmsis_spi_dma_handle_t SPI0_DmaHandle;
1304 static dma_handle_t SPI0_DmaTxDataHandle;
1305 static dma_handle_t SPI0_DmaRxDataHandle;
1306
1307 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1308 ARMCC_SECTION("spi0_d_m_a_driver_state")
1309 static cmsis_SPI_dma_driver_state_t SPI0_DMADriverState = {
1310 #else
1311 static cmsis_SPI_dma_driver_state_t SPI0_DMADriverState = {
1312 #endif
1313 &SPI0_Resource, &SPI0_DMAResource, &SPI0_DmaHandle, &SPI0_DmaRxDataHandle, &SPI0_DmaTxDataHandle,
1314
1315 };
1316
SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)1317 static int32_t SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1318 {
1319 #ifdef RTE_SPI0_PIN_INIT
1320 RTE_SPI0_PIN_INIT();
1321 #endif
1322 return SPI_DMAInitialize(cb_event, &SPI0_DMADriverState);
1323 }
1324
SPI0_DMAUninitialize(void)1325 static int32_t SPI0_DMAUninitialize(void)
1326 {
1327 #ifdef RTE_SPI0_PIN_DEINIT
1328 RTE_SPI0_PIN_DEINIT();
1329 #endif
1330 return SPI_DMAUninitialize(&SPI0_DMADriverState);
1331 }
1332
SPI0_DMAPowerControl(ARM_POWER_STATE state)1333 static int32_t SPI0_DMAPowerControl(ARM_POWER_STATE state)
1334 {
1335 return SPI_DMAPowerControl(state, &SPI0_DMADriverState);
1336 }
1337
SPI0_DMASend(const void * data,uint32_t num)1338 static int32_t SPI0_DMASend(const void *data, uint32_t num)
1339 {
1340 return SPI_DMASend(data, num, &SPI0_DMADriverState);
1341 }
1342
SPI0_DMAReceive(void * data,uint32_t num)1343 static int32_t SPI0_DMAReceive(void *data, uint32_t num)
1344 {
1345 return SPI_DMAReceive(data, num, &SPI0_DMADriverState);
1346 }
1347
SPI0_DMATransfer(const void * data_out,void * data_in,uint32_t num)1348 static int32_t SPI0_DMATransfer(const void *data_out, void *data_in, uint32_t num)
1349 {
1350 return SPI_DMATransfer(data_out, data_in, num, &SPI0_DMADriverState);
1351 }
1352
SPI0_DMAGetCount(void)1353 static uint32_t SPI0_DMAGetCount(void)
1354 {
1355 return SPI_DMAGetCount(&SPI0_DMADriverState);
1356 }
1357
SPI0_DMAControl(uint32_t control,uint32_t arg)1358 static int32_t SPI0_DMAControl(uint32_t control, uint32_t arg)
1359 {
1360 return SPI_DMAControl(control, arg, &SPI0_DMADriverState);
1361 }
1362
SPI0_DMAGetStatus(void)1363 static ARM_SPI_STATUS SPI0_DMAGetStatus(void)
1364 {
1365 return SPI_DMAGetStatus(&SPI0_DMADriverState);
1366 }
1367
1368 #endif
1369
1370 #else
1371
1372 static cmsis_spi_handle_t SPI0_Handle;
1373
1374 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1375 ARMCC_SECTION("spi0_interrupt_driver_state")
1376 static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = {
1377 #else
1378 static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = {
1379 #endif
1380 &SPI0_Resource,
1381 &SPI0_Handle,
1382 };
1383
SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1384 static int32_t SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1385 {
1386 #ifdef RTE_SPI0_PIN_INIT
1387 RTE_SPI0_PIN_INIT();
1388 #endif
1389 return SPI_InterruptInitialize(cb_event, &SPI0_InterruptDriverState);
1390 }
1391
SPI0_InterruptUninitialize(void)1392 static int32_t SPI0_InterruptUninitialize(void)
1393 {
1394 #ifdef RTE_SPI0_PIN_DEINIT
1395 RTE_SPI0_PIN_DEINIT();
1396 #endif
1397 return SPI_InterruptUninitialize(&SPI0_InterruptDriverState);
1398 }
1399
SPI0_InterruptPowerControl(ARM_POWER_STATE state)1400 static int32_t SPI0_InterruptPowerControl(ARM_POWER_STATE state)
1401 {
1402 return SPI_InterruptPowerControl(state, &SPI0_InterruptDriverState);
1403 }
1404
SPI0_InterruptSend(const void * data,uint32_t num)1405 static int32_t SPI0_InterruptSend(const void *data, uint32_t num)
1406 {
1407 return SPI_InterruptSend(data, num, &SPI0_InterruptDriverState);
1408 }
1409
SPI0_InterruptReceive(void * data,uint32_t num)1410 static int32_t SPI0_InterruptReceive(void *data, uint32_t num)
1411 {
1412 return SPI_InterruptReceive(data, num, &SPI0_InterruptDriverState);
1413 }
1414
SPI0_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1415 static int32_t SPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1416 {
1417 return SPI_InterruptTransfer(data_out, data_in, num, &SPI0_InterruptDriverState);
1418 }
1419
SPI0_InterruptGetCount(void)1420 static uint32_t SPI0_InterruptGetCount(void)
1421 {
1422 return SPI_InterruptGetCount(&SPI0_InterruptDriverState);
1423 }
1424
SPI0_InterruptControl(uint32_t control,uint32_t arg)1425 static int32_t SPI0_InterruptControl(uint32_t control, uint32_t arg)
1426 {
1427 return SPI_InterruptControl(control, arg, &SPI0_InterruptDriverState);
1428 }
1429
SPI0_InterruptGetStatus(void)1430 static ARM_SPI_STATUS SPI0_InterruptGetStatus(void)
1431 {
1432 return SPI_InterruptGetStatus(&SPI0_InterruptDriverState);
1433 }
1434
1435 #endif
1436
1437 ARM_DRIVER_SPI Driver_SPI0 = {SPIx_GetVersion, SPIx_GetCapabilities,
1438 #if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
1439 SPI0_DMAInitialize, SPI0_DMAUninitialize, SPI0_DMAPowerControl, SPI0_DMASend,
1440 SPI0_DMAReceive, SPI0_DMATransfer, SPI0_DMAGetCount, SPI0_DMAControl,
1441 SPI0_DMAGetStatus
1442 #else
1443 SPI0_InterruptInitialize,
1444 SPI0_InterruptUninitialize,
1445 SPI0_InterruptPowerControl,
1446 SPI0_InterruptSend,
1447 SPI0_InterruptReceive,
1448 SPI0_InterruptTransfer,
1449 SPI0_InterruptGetCount,
1450 SPI0_InterruptControl,
1451 SPI0_InterruptGetStatus
1452 #endif
1453
1454 };
1455
1456 #endif /* SPI0 */
1457
1458 #if defined(SPI1) && defined(RTE_SPI1) && RTE_SPI1
1459
1460 /* User needs to provide the implementation for SPI1_GetFreq/InitPins/DeinitPins
1461 in the application for enabling according instance. */
1462 extern uint32_t SPI1_GetFreq(void);
1463
1464 static cmsis_spi_resource_t SPI1_Resource = {SPI1, 1, SPI1_GetFreq};
1465
1466 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1467
1468 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1469 static cmsis_spi_dma_resource_t SPI1_DMAResource = {
1470 RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_TX_DMAMUX_BASE, RTE_SPI1_DMA_TX_PERI_SEL,
1471
1472 RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, RTE_SPI1_DMA_RX_DMAMUX_BASE, RTE_SPI1_DMA_RX_PERI_SEL,
1473 #if FSL_FEATURE_DMA_MODULE_CHANNEL != FSL_FEATURE_DMAMUX_MODULE_CHANNEL
1474 RTE_SPI1_DMAMUX_TX_CH, RTE_SPI1_DMAMUX_RX_CH
1475 #endif
1476 };
1477
1478 static cmsis_spi_dma_handle_t SPI1_DmaHandle;
1479 static dma_handle_t SPI1_DmaTxDataHandle;
1480 static dma_handle_t SPI1_DmaRxDataHandle;
1481
1482 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1483 ARMCC_SECTION("spi1_d_m_a_driver_state")
1484 static cmsis_SPI_dma_driver_state_t SPI1_DMADriverState = {
1485 #else
1486 static cmsis_SPI_dma_driver_state_t SPI1_DMADriverState = {
1487 #endif
1488 &SPI1_Resource, &SPI1_DMAResource, &SPI1_DmaHandle, &SPI1_DmaRxDataHandle, &SPI1_DmaTxDataHandle,
1489 };
1490
SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)1491 static int32_t SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1492 {
1493 #ifdef RTE_SPI1_PIN_INIT
1494 RTE_SPI1_PIN_INIT();
1495 #endif
1496 return SPI_DMAInitialize(cb_event, &SPI1_DMADriverState);
1497 }
1498
SPI1_DMAUninitialize(void)1499 static int32_t SPI1_DMAUninitialize(void)
1500 {
1501 #ifdef RTE_SPI1_PIN_DEINIT
1502 RTE_SPI1_PIN_DEINIT();
1503 #endif
1504 return SPI_DMAUninitialize(&SPI1_DMADriverState);
1505 }
1506
SPI1_DMAPowerControl(ARM_POWER_STATE state)1507 static int32_t SPI1_DMAPowerControl(ARM_POWER_STATE state)
1508 {
1509 return SPI_DMAPowerControl(state, &SPI1_DMADriverState);
1510 }
1511
SPI1_DMASend(const void * data,uint32_t num)1512 static int32_t SPI1_DMASend(const void *data, uint32_t num)
1513 {
1514 return SPI_DMASend(data, num, &SPI1_DMADriverState);
1515 }
1516
SPI1_DMAReceive(void * data,uint32_t num)1517 static int32_t SPI1_DMAReceive(void *data, uint32_t num)
1518 {
1519 return SPI_DMAReceive(data, num, &SPI1_DMADriverState);
1520 }
1521
SPI1_DMATransfer(const void * data_out,void * data_in,uint32_t num)1522 static int32_t SPI1_DMATransfer(const void *data_out, void *data_in, uint32_t num)
1523 {
1524 return SPI_DMATransfer(data_out, data_in, num, &SPI1_DMADriverState);
1525 }
1526
SPI1_DMAGetCount(void)1527 static uint32_t SPI1_DMAGetCount(void)
1528 {
1529 return SPI_DMAGetCount(&SPI1_DMADriverState);
1530 }
1531
SPI1_DMAControl(uint32_t control,uint32_t arg)1532 static int32_t SPI1_DMAControl(uint32_t control, uint32_t arg)
1533 {
1534 return SPI_DMAControl(control, arg, &SPI1_DMADriverState);
1535 }
1536
SPI1_DMAGetStatus(void)1537 static ARM_SPI_STATUS SPI1_DMAGetStatus(void)
1538 {
1539 return SPI_DMAGetStatus(&SPI1_DMADriverState);
1540 }
1541
1542 #endif
1543
1544 #else
1545
1546 static cmsis_spi_handle_t SPI1_Handle;
1547
1548 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1549 ARMCC_SECTION("spi1_interrupt_driver_state")
1550 static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = {
1551 #else
1552 static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = {
1553 #endif
1554 &SPI1_Resource,
1555 &SPI1_Handle,
1556 };
1557
SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1558 static int32_t SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1559 {
1560 #ifdef RTE_SPI1_PIN_INIT
1561 RTE_SPI1_PIN_INIT();
1562 #endif
1563 return SPI_InterruptInitialize(cb_event, &SPI1_InterruptDriverState);
1564 }
1565
SPI1_InterruptUninitialize(void)1566 static int32_t SPI1_InterruptUninitialize(void)
1567 {
1568 #ifdef RTE_SPI1_PIN_DEINIT
1569 RTE_SPI1_PIN_DEINIT();
1570 #endif
1571 return SPI_InterruptUninitialize(&SPI1_InterruptDriverState);
1572 }
1573
SPI1_InterruptPowerControl(ARM_POWER_STATE state)1574 static int32_t SPI1_InterruptPowerControl(ARM_POWER_STATE state)
1575 {
1576 return SPI_InterruptPowerControl(state, &SPI1_InterruptDriverState);
1577 }
1578
SPI1_InterruptSend(const void * data,uint32_t num)1579 static int32_t SPI1_InterruptSend(const void *data, uint32_t num)
1580 {
1581 return SPI_InterruptSend(data, num, &SPI1_InterruptDriverState);
1582 }
1583
SPI1_InterruptReceive(void * data,uint32_t num)1584 static int32_t SPI1_InterruptReceive(void *data, uint32_t num)
1585 {
1586 return SPI_InterruptReceive(data, num, &SPI1_InterruptDriverState);
1587 }
1588
SPI1_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1589 static int32_t SPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1590 {
1591 return SPI_InterruptTransfer(data_out, data_in, num, &SPI1_InterruptDriverState);
1592 }
1593
SPI1_InterruptGetCount(void)1594 static uint32_t SPI1_InterruptGetCount(void)
1595 {
1596 return SPI_InterruptGetCount(&SPI1_InterruptDriverState);
1597 }
1598
SPI1_InterruptControl(uint32_t control,uint32_t arg)1599 static int32_t SPI1_InterruptControl(uint32_t control, uint32_t arg)
1600 {
1601 return SPI_InterruptControl(control, arg, &SPI1_InterruptDriverState);
1602 }
1603
SPI1_InterruptGetStatus(void)1604 static ARM_SPI_STATUS SPI1_InterruptGetStatus(void)
1605 {
1606 return SPI_InterruptGetStatus(&SPI1_InterruptDriverState);
1607 }
1608
1609 #endif
1610
1611 ARM_DRIVER_SPI Driver_SPI1 = {SPIx_GetVersion, SPIx_GetCapabilities,
1612 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1613 SPI1_DMAInitialize, SPI1_DMAUninitialize, SPI1_DMAPowerControl, SPI1_DMASend,
1614 SPI1_DMAReceive, SPI1_DMATransfer, SPI1_DMAGetCount, SPI1_DMAControl,
1615 SPI1_DMAGetStatus
1616 #else
1617 SPI1_InterruptInitialize,
1618 SPI1_InterruptUninitialize,
1619 SPI1_InterruptPowerControl,
1620 SPI1_InterruptSend,
1621 SPI1_InterruptReceive,
1622 SPI1_InterruptTransfer,
1623 SPI1_InterruptGetCount,
1624 SPI1_InterruptControl,
1625 SPI1_InterruptGetStatus
1626 #endif
1627
1628 };
1629
1630 #endif /* SPI1 */
1631
