1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2017,2020,2021,2024 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_lpspi_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.lpspi_cmsis"
26 #endif
27
28 #if ((defined(RTE_SPI0) && RTE_SPI0 && defined(LPSPI0)) || (defined(RTE_SPI1) && RTE_SPI1 && defined(LPSPI1)) || \
29 (defined(RTE_SPI2) && RTE_SPI2 && defined(LPSPI2)) || (defined(RTE_SPI3) && RTE_SPI3 && defined(LPSPI3)) || \
30 (defined(RTE_SPI4) && RTE_SPI4 && defined(LPSPI4)) || (defined(RTE_SPI5) && RTE_SPI5 && defined(LPSPI5)) || \
31 (defined(RTE_SPI6) && RTE_SPI6 && defined(LPSPI6)) || (defined(RTE_SPI7) && RTE_SPI7 && defined(LPSPI7)) || \
32 (defined(RTE_SPI8) && RTE_SPI8 && defined(LPSPI8)) || (defined(RTE_SPI9) && RTE_SPI9 && defined(LPSPI9)) || \
33 (defined(RTE_SPI10) && RTE_SPI10 && defined(LPSPI10)) || (defined(RTE_SPI11) && RTE_SPI11 && defined(LPSPI11)) || \
34 (defined(RTE_SPI12) && RTE_SPI12 && defined(LPSPI12)) || (defined(RTE_SPI13) && RTE_SPI13 && defined(LPSPI13)) || \
35 (defined(RTE_SPI14) && RTE_SPI14 && defined(LPSPI14)) || (defined(RTE_SPI15) && RTE_SPI15 && defined(LPSPI15)) || \
36 (defined(RTE_SPI16) && RTE_SPI16 && defined(LPSPI16)) || (defined(RTE_SPI17) && RTE_SPI17 && defined(LPSPI17)) || \
37 (defined(RTE_SPI18) && RTE_SPI18 && defined(LPSPI18)) || (defined(RTE_SPI19) && RTE_SPI19 && defined(LPSPI19)) || \
38 (defined(RTE_SPI20) && RTE_SPI20 && defined(LPSPI20)))
39
40 #define ARM_LPSPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (9)) /* driver version */
41
42 /*
43 * ARMCC does not support split the data section automatically, so the driver
44 * needs to split the data to separate sections explicitly, to reduce codesize.
45 */
46 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
47 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
48 #endif
49
50 static clock_ip_name_t const s_lpspiClock[] = LPSPI_CLOCKS;
51
52 typedef const struct _cmsis_lpspi_resource
53 {
54 LPSPI_Type *base;
55 uint32_t instance;
56 uint32_t (*GetFreq)(void);
57 } cmsis_lpspi_resource_t;
58
59 typedef union _cmsis_lpspi_handle
60 {
61 lpspi_master_handle_t masterHandle;
62 lpspi_slave_handle_t slaveHandle;
63 } cmsis_lpspi_handle_t;
64
65 typedef struct _cmsis_lpspi_interrupt_driver_state
66 {
67 cmsis_lpspi_resource_t *resource;
68 cmsis_lpspi_handle_t *handle;
69 ARM_SPI_SignalEvent_t cb_event;
70 uint32_t baudRate_Bps;
71 uint8_t flags; /*!< Control and state flags. */
72 } cmsis_lpspi_interrupt_driver_state_t;
73
74 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
75 typedef const struct _cmsis_lpspi_edma_resource
76 {
77 void *txEdmaBase;
78 uint32_t txEdmaChannel;
79 uint16_t txDmaRequest;
80
81 void *rxEdmaBase;
82 uint32_t rxEdmaChannel;
83 uint16_t rxDmaRequest;
84
85 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
86 DMAMUX_Type *txDmamuxBase;
87 DMAMUX_Type *rxDmamuxBase;
88 #endif
89 } cmsis_lpspi_edma_resource_t;
90
91 typedef union _cmsis_lpspi_edma_handle
92 {
93 lpspi_master_edma_handle_t masterHandle;
94 lpspi_slave_edma_handle_t slaveHandle;
95 } cmsis_lpspi_edma_handle_t;
96
97 typedef struct _cmsis_lpspi_edma_driver_state
98 {
99 cmsis_lpspi_resource_t *resource;
100 cmsis_lpspi_edma_resource_t *dmaResource;
101 cmsis_lpspi_edma_handle_t *handle;
102 edma_handle_t *edmaRxRegToRxDataHandle;
103 edma_handle_t *edmaTxDataToTxRegHandle;
104 ARM_SPI_SignalEvent_t cb_event;
105 uint32_t baudRate_Bps;
106 uint8_t flags; /*!< Control and state flags. */
107 } cmsis_lpspi_edma_driver_state_t;
108 #endif
109
110 /* Driver Version */
111 static const ARM_DRIVER_VERSION s_lpspiDriverVersion = {ARM_SPI_API_VERSION, ARM_LPSPI_DRV_VERSION};
112
113 /* Driver Capabilities */
114 static const ARM_SPI_CAPABILITIES s_lpspiDriverCapabilities = {
115 1, /* Simplex Mode (Master and Slave) */
116 0, /* TI Synchronous Serial Interface */
117 0, /* Microwire Interface */
118 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
119 };
120
121 /*
122 *Common Control function used by LPSPI_InterruptControl / LPSPI_EdmaControl.
123 */
LPSPI_CommonControl(uint32_t control,uint32_t arg,cmsis_lpspi_resource_t * resource,uint8_t * isConfigured)124 static int32_t LPSPI_CommonControl(uint32_t control,
125 uint32_t arg,
126 cmsis_lpspi_resource_t *resource,
127 uint8_t *isConfigured)
128 {
129 lpspi_master_config_t masterConfig;
130 LPSPI_MasterGetDefaultConfig(&masterConfig);
131 lpspi_slave_config_t slaveConfig;
132 LPSPI_SlaveGetDefaultConfig(&slaveConfig);
133 bool isMaster = ((control & ARM_SPI_CONTROL_Msk) == ARM_SPI_MODE_MASTER) ||
134 ((control & ARM_SPI_CONTROL_Msk) == ARM_SPI_MODE_MASTER_SIMPLEX);
135 masterConfig.baudRate = arg;
136
137 if (ARM_SPI_MODE_MASTER_SIMPLEX == (control & (uint32_t)ARM_SPI_CONTROL_Msk))
138 {
139 masterConfig.pinCfg = kLPSPI_SdoInSdoOut;
140 }
141 if (ARM_SPI_MODE_SLAVE_SIMPLEX == (control & (uint32_t)ARM_SPI_CONTROL_Msk))
142 {
143 slaveConfig.pinCfg = kLPSPI_SdiInSdiOut;
144 }
145
146 #if (defined(RTE_SPI0_PCS_TO_SCK_DELAY) && defined(RTE_SPI0_SCK_TO_PSC_DELAY) && \
147 defined(RTE_SPI0_BETWEEN_TRANSFER_DELAY))
148 if (0U == resource->instance)
149 {
150 masterConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI0_PCS_TO_SCK_DELAY;
151 masterConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI0_SCK_TO_PSC_DELAY;
152 masterConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI0_BETWEEN_TRANSFER_DELAY;
153 }
154 #endif /*RTE LPSPI0 trnafer delay time configure */
155
156 #if (defined(RTE_SPI1_PCS_TO_SCK_DELAY) && defined(RTE_SPI1_SCK_TO_PSC_DELAY) && \
157 defined(RTE_SPI1_BETWEEN_TRANSFER_DELAY))
158 if (1U == resource->instance)
159 {
160 masterConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI1_PCS_TO_SCK_DELAY;
161 masterConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI1_SCK_TO_PSC_DELAY;
162 masterConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI1_BETWEEN_TRANSFER_DELAY;
163 }
164 #endif /*RTE LPSPI1 trnafer delay time configure */
165
166 #if (defined(RTE_SPI2_PCS_TO_SCK_DELAY) && defined(RTE_SPI2_SCK_TO_PSC_DELAY) && \
167 defined(RTE_SPI2_BETWEEN_TRANSFER_DELAY))
168 if (2U == resource->instance)
169 {
170 masterConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI2_PCS_TO_SCK_DELAY;
171 masterConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI2_SCK_TO_PSC_DELAY;
172 masterConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI2_BETWEEN_TRANSFER_DELAY;
173 }
174 #endif /*RTE LPSPI2 trnafer delay time configure */
175 #if (defined(RTE_SPI3_PCS_TO_SCK_DELAY) && defined(RTE_SPI3_SCK_TO_PSC_DELAY) && \
176 defined(RTE_SPI3_BETWEEN_TRANSFER_DELAY))
177 if (3U == resource->instance)
178 {
179 masterConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI3_PCS_TO_SCK_DELAY;
180 masterConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI3_SCK_TO_PSC_DELAY;
181 masterConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI3_BETWEEN_TRANSFER_DELAY;
182 }
183 #endif /*RTE LPSPI3 trnafer delay time configure */
184
185 #if (defined(RTE_SPI4_PCS_TO_SCK_DELAY) && defined(RTE_SPI4_SCK_TO_PSC_DELAY) && \
186 defined(RTE_SPI4_BETWEEN_TRANSFER_DELAY))
187 if (4U == resource->instance)
188 {
189 masterConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI4_PCS_TO_SCK_DELAY;
190 masterConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI4_SCK_TO_PSC_DELAY;
191 masterConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI4_BETWEEN_TRANSFER_DELAY;
192 }
193 #endif /*RTE LPSPI4 trnafer delay time configure */
194
195 #if (defined(RTE_SPI5_PCS_TO_SCK_DELAY) && defined(RTE_SPI5_SCK_TO_PSC_DELAY) && \
196 defined(RTE_SPI5_BETWEEN_TRANSFER_DELAY))
197 if (5U == resource->instance)
198 {
199 masterConfig.pcsToSckDelayInNanoSec = (uint32_t)RTE_SPI5_PCS_TO_SCK_DELAY;
200 masterConfig.lastSckToPcsDelayInNanoSec = (uint32_t)RTE_SPI5_SCK_TO_PSC_DELAY;
201 masterConfig.betweenTransferDelayInNanoSec = (uint32_t)RTE_SPI5_BETWEEN_TRANSFER_DELAY;
202 }
203 #endif /*RTE LPSPI5 trnafer delay time configure */
204
205 switch (control & (uint32_t)ARM_SPI_FRAME_FORMAT_Msk)
206 {
207 case ARM_SPI_CPOL0_CPHA0: /* Clock Polarity 0, Clock Phase 0*/
208 if (isMaster)
209 {
210 masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
211 masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
212 }
213 else
214 {
215 slaveConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
216 slaveConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
217 }
218 break;
219 case ARM_SPI_CPOL0_CPHA1: /* Clock Polarity 0, Clock Phase 1*/
220 if (isMaster)
221 {
222 masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
223 masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge;
224 }
225 else
226 {
227 slaveConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
228 slaveConfig.cpha = kLPSPI_ClockPhaseSecondEdge;
229 }
230 break;
231 case ARM_SPI_CPOL1_CPHA0: /* Clock Polarity 1, Clock Phase 0*/
232 if (isMaster)
233 {
234 masterConfig.cpol = kLPSPI_ClockPolarityActiveLow;
235 masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
236 }
237 else
238 {
239 slaveConfig.cpol = kLPSPI_ClockPolarityActiveLow;
240 slaveConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
241 }
242 break;
243 case ARM_SPI_CPOL1_CPHA1: /* Clock Polarity 1, Clock Phase 1*/
244 if (isMaster)
245 {
246 masterConfig.cpol = kLPSPI_ClockPolarityActiveLow;
247 masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge;
248 }
249 else
250 {
251 slaveConfig.cpol = kLPSPI_ClockPolarityActiveLow;
252 slaveConfig.cpha = kLPSPI_ClockPhaseSecondEdge;
253 }
254 break;
255 default:
256 /* Avoid MISRA 16.4 violations. */
257 break;
258 }
259
260 if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* Number of Data bits */
261 {
262 if ((((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 8UL))
263 {
264 if (isMaster)
265 {
266 masterConfig.bitsPerFrame = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos);
267 }
268 else
269 {
270 slaveConfig.bitsPerFrame = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos);
271 }
272 }
273 else
274 {
275 return ARM_SPI_ERROR_DATA_BITS;
276 }
277 }
278
279 switch (control & (uint32_t)ARM_SPI_BIT_ORDER_Msk)
280 {
281 case ARM_SPI_LSB_MSB: /* SPI Bit order from LSB to MSB */
282 if (isMaster)
283 {
284 masterConfig.direction = kLPSPI_LsbFirst;
285 }
286 else
287 {
288 slaveConfig.direction = kLPSPI_LsbFirst;
289 }
290 break;
291 case ARM_SPI_MSB_LSB: /* SPI Bit order from MSB to LSB */
292 if (isMaster)
293 {
294 masterConfig.direction = kLPSPI_MsbFirst;
295 }
296 else
297 {
298 slaveConfig.direction = kLPSPI_MsbFirst;
299 }
300 break;
301 default:
302 /* Avoid MISRA 16.4 violations. */
303 break;
304 }
305
306 if (isMaster)
307 {
308 /* The SPI slave select is controlled by hardware, the other mode is not supported by current driver. */
309 switch (control & (uint32_t)ARM_SPI_SS_MASTER_MODE_Msk)
310 {
311 case ARM_SPI_SS_MASTER_UNUSED:
312 break;
313 case ARM_SPI_SS_MASTER_SW:
314 break;
315 case ARM_SPI_SS_MASTER_HW_OUTPUT:
316 break;
317 case ARM_SPI_SS_MASTER_HW_INPUT:
318 break;
319 default:
320 /* Avoid MISRA 16.4 violations. */
321 break;
322 }
323 }
324 else
325 {
326 /* The SPI slave select is controlled by hardware, the other mode is not supported by current driver. */
327 switch (control & (uint32_t)ARM_SPI_SS_SLAVE_MODE_Msk)
328 {
329 case ARM_SPI_SS_SLAVE_HW:
330 break;
331 case ARM_SPI_SS_SLAVE_SW:
332 break;
333 default:
334 /* Avoid MISRA 16.4 violations. */
335 break;
336 }
337 }
338
339 /* LPSPI Init*/
340 if (isMaster)
341 {
342 if (((*isConfigured) & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
343 {
344 LPSPI_Deinit(resource->base);
345 }
346 LPSPI_MasterInit(resource->base, &masterConfig, resource->GetFreq());
347 *isConfigured |= (uint8_t)SPI_FLAG_CONFIGURED;
348 }
349 else
350 {
351 if (((*isConfigured) & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
352 {
353 LPSPI_Deinit(resource->base);
354 }
355 LPSPI_SlaveInit(resource->base, &slaveConfig);
356 *isConfigured |= (uint8_t)SPI_FLAG_CONFIGURED;
357 }
358
359 return ARM_DRIVER_OK;
360 }
361
LPSPI_SetTransferConfigFlags(bool isMaster,uint32_t instance,lpspi_transfer_t * xfer)362 static void LPSPI_SetTransferConfigFlags(bool isMaster, uint32_t instance, lpspi_transfer_t *xfer)
363 {
364 if (isMaster)
365 {
366 /* Set default config flag */
367 xfer->configFlags = (uint32_t)kLPSPI_MasterPcs0 | (uint32_t)kLPSPI_MasterPcsContinuous;
368 #if (defined(RTE_SPI0_MASTER_PCS_PIN_SEL))
369 if (0U == instance)
370 {
371 xfer->configFlags = (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL | (uint32_t)kLPSPI_MasterPcsContinuous;
372 }
373 #endif /* LPSPI0 PCS pin configuration */
374 #if (defined(RTE_SPI1_MASTER_PCS_PIN_SEL))
375 if (1U == instance)
376 {
377 xfer->configFlags = (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL | (uint32_t)kLPSPI_MasterPcsContinuous;
378 }
379 #endif /* LPSPI1 PCS pin configuration */
380 #if (defined(RTE_SPI2_MASTER_PCS_PIN_SEL))
381 if (2U == instance)
382 {
383 xfer->configFlags = (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL | (uint32_t)kLPSPI_MasterPcsContinuous;
384 }
385 #endif /* LPSPI2 PCS pin configuration */
386 #if (defined(RTE_SPI3_MASTER_PCS_PIN_SEL))
387 if (3U == instance)
388 {
389 xfer->configFlags = (uint32_t)RTE_SPI3_MASTER_PCS_PIN_SEL | (uint32_t)kLPSPI_MasterPcsContinuous;
390 }
391 #endif /* LPSPI3 PCS pin configuration */
392 #if (defined(RTE_SPI4_MASTER_PCS_PIN_SEL))
393 if (4U == instance)
394 {
395 xfer->configFlags = (uint32_t)RTE_SPI4_MASTER_PCS_PIN_SEL | (uint32_t)kLPSPI_MasterPcsContinuous;
396 }
397 #endif /* LPSPI4 PCS pin configuration */
398 #if (defined(RTE_SPI5_MASTER_PCS_PIN_SEL))
399 if (5U == instance)
400 {
401 xfer->configFlags = (uint32_t)RTE_SPI5_MASTER_PCS_PIN_SEL | (uint32_t)kLPSPI_MasterPcsContinuous;
402 }
403 #endif /* LPSPI5 PCS pin configuration */
404 }
405 else
406 {
407 /* Set default config flag */
408 xfer->configFlags = (uint32_t)kLPSPI_SlavePcs0;
409 #if (defined(RTE_SPI0_SLAVE_PCS_PIN_SEL))
410 if (0U == instance)
411 {
412 xfer->configFlags = (uint32_t)RTE_SPI0_SLAVE_PCS_PIN_SEL;
413 }
414 #endif /* LPSPI0 PCS pin configuration */
415 #if (defined(RTE_SPI1_SLAVE_PCS_PIN_SEL))
416 if (1U == instance)
417 {
418 xfer->configFlags = (uint32_t)RTE_SPI1_SLAVE_PCS_PIN_SEL;
419 }
420 #endif /* LPSPI1 PCS pin configuration */
421 #if (defined(RTE_SPI2_SLAVE_PCS_PIN_SEL))
422 if (2U == instance)
423 {
424 xfer->configFlags = (uint32_t)RTE_SPI2_SLAVE_PCS_PIN_SEL;
425 }
426 #endif /* LPSPI2 PCS pin configuration */
427 #if (defined(RTE_SPI3_SLAVE_PCS_PIN_SEL))
428 if (3U == instance)
429 {
430 xfer->configFlags = (uint32_t)RTE_SPI3_SLAVE_PCS_PIN_SEL;
431 }
432 #endif /* LPSPI3 PCS pin configuration */
433 #if (defined(RTE_SPI4_SLAVE_PCS_PIN_SEL))
434 if (4U == instance)
435 {
436 xfer->configFlags = (uint32_t)RTE_SPI4_SLAVE_PCS_PIN_SEL;
437 }
438 #endif /* LPSPI4 PCS pin configuration */
439 #if (defined(RTE_SPI5_SLAVE_PCS_PIN_SEL))
440 if (5U == instance)
441 {
442 xfer->configFlags = (uint32_t)RTE_SPI5_SLAVE_PCS_PIN_SEL;
443 }
444 #endif /* LPSPI5 PCS pin configuration */
445 }
446 }
447
LPSPIx_GetVersion(void)448 static ARM_DRIVER_VERSION LPSPIx_GetVersion(void)
449 {
450 return s_lpspiDriverVersion;
451 }
452
LPSPIx_GetCapabilities(void)453 static ARM_SPI_CAPABILITIES LPSPIx_GetCapabilities(void)
454 {
455 return s_lpspiDriverCapabilities;
456 }
457
458 #endif
459
460 #if ((defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN) || (defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || \
461 (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN) || \
462 (defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN) || (defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN) || \
463 (defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN) || (defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN) || \
464 (defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN) || (defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN) || \
465 (defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN) || (defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN) || \
466 (defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN) || (defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN) || \
467 (defined(RTE_SPI14_DMA_EN) && RTE_SPI14_DMA_EN) || (defined(RTE_SPI15_DMA_EN) && RTE_SPI15_DMA_EN) || \
468 (defined(RTE_SPI16_DMA_EN) && RTE_SPI16_DMA_EN) || (defined(RTE_SPI17_DMA_EN) && RTE_SPI17_DMA_EN) || \
469 (defined(RTE_SPI18_DMA_EN) && RTE_SPI18_DMA_EN) || (defined(RTE_SPI19_DMA_EN) && RTE_SPI19_DMA_EN) || \
470 (defined(RTE_SPI20_DMA_EN) && RTE_SPI20_DMA_EN))
471
472 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
473
KSDK_LPSPI_MasterEdmaCallback(LPSPI_Type * base,lpspi_master_edma_handle_t * handle,status_t status,void * userData)474 static void KSDK_LPSPI_MasterEdmaCallback(LPSPI_Type *base,
475 lpspi_master_edma_handle_t *handle,
476 status_t status,
477 void *userData)
478 {
479 uint32_t event = 0U;
480
481 if (kStatus_Success == status)
482 {
483 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
484 }
485 else if (kStatus_LPSPI_OutOfRange == status)
486 {
487 event = ARM_SPI_EVENT_DATA_LOST;
488 }
489 else
490 {
491 /* Avoid MISRA 15.7 violations. */
492 }
493 /* User data is actually CMSIS driver callback. */
494 if ((0U != event) && (userData != NULL))
495 {
496 ((ARM_SPI_SignalEvent_t)userData)(event);
497 }
498 }
KSDK_LPSPI_SlaveEdmaCallback(LPSPI_Type * base,lpspi_slave_edma_handle_t * handle,status_t status,void * userData)499 static void KSDK_LPSPI_SlaveEdmaCallback(LPSPI_Type *base,
500 lpspi_slave_edma_handle_t *handle,
501 status_t status,
502 void *userData)
503 {
504 uint32_t event = 0U;
505
506 if (kStatus_Success == status)
507 {
508 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
509 }
510 else if (kStatus_LPSPI_OutOfRange == status)
511 {
512 event = ARM_SPI_EVENT_DATA_LOST;
513 }
514 else
515 {
516 /* Avoid MISRA 15.7 violations. */
517 }
518 /* User data is actually CMSIS driver callback. */
519 if ((0U != event) && (userData != NULL))
520 {
521 ((ARM_SPI_SignalEvent_t)userData)(event);
522 }
523 }
524
LPSPI_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_lpspi_edma_driver_state_t * lpspi)525 static int32_t LPSPI_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_lpspi_edma_driver_state_t *lpspi)
526 {
527 if (0U == (lpspi->flags & (uint8_t)SPI_FLAG_INIT))
528 {
529 lpspi->cb_event = cb_event;
530 lpspi->flags = (uint8_t)SPI_FLAG_INIT;
531 }
532 return ARM_DRIVER_OK;
533 }
534
LPSPI_EdmaUninitialize(cmsis_lpspi_edma_driver_state_t * lpspi)535 static int32_t LPSPI_EdmaUninitialize(cmsis_lpspi_edma_driver_state_t *lpspi)
536 {
537 lpspi->flags = (uint8_t)SPI_FLAG_UNINIT;
538 return ARM_DRIVER_OK;
539 }
540
LPSPI_EdmaPowerControl(ARM_POWER_STATE state,cmsis_lpspi_edma_driver_state_t * lpspi)541 static int32_t LPSPI_EdmaPowerControl(ARM_POWER_STATE state, cmsis_lpspi_edma_driver_state_t *lpspi)
542 {
543 cmsis_lpspi_edma_resource_t *dmaResource = lpspi->dmaResource;
544 int32_t result = ARM_DRIVER_OK;
545
546 switch (state)
547 {
548 case ARM_POWER_OFF:
549 if ((lpspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
550 {
551 LPSPI_Deinit(lpspi->resource->base);
552 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
553 DMAMUX_DisableChannel(lpspi->dmaResource->rxDmamuxBase, lpspi->dmaResource->rxEdmaChannel);
554 DMAMUX_DisableChannel(lpspi->dmaResource->txDmamuxBase, lpspi->dmaResource->txEdmaChannel);
555 #endif
556 lpspi->flags = (uint8_t)SPI_FLAG_INIT;
557 }
558 break;
559 case ARM_POWER_LOW:
560 result = ARM_DRIVER_ERROR_UNSUPPORTED;
561 break;
562 case ARM_POWER_FULL:
563 {
564 if (lpspi->flags == (uint8_t)SPI_FLAG_UNINIT)
565 {
566 result = ARM_DRIVER_ERROR;
567 break;
568 }
569
570 if ((lpspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
571 {
572 /* Driver already powered */
573 break;
574 }
575 /* Enable Clock gate */
576 (void)CLOCK_EnableClock(s_lpspiClock[lpspi->resource->instance]);
577
578 (void)memset(lpspi->edmaRxRegToRxDataHandle, 0, sizeof(edma_handle_t));
579 (void)memset(lpspi->edmaTxDataToTxRegHandle, 0, sizeof(edma_handle_t));
580
581 EDMA_CreateHandle(lpspi->edmaRxRegToRxDataHandle, dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel);
582 EDMA_CreateHandle(lpspi->edmaTxDataToTxRegHandle, dmaResource->txEdmaBase, dmaResource->txEdmaChannel);
583 #if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX
584 EDMA_SetChannelMux(dmaResource->txEdmaBase, dmaResource->txEdmaChannel, (int32_t)dmaResource->txDmaRequest);
585 EDMA_SetChannelMux(dmaResource->rxEdmaBase, dmaResource->rxEdmaChannel, (int32_t)dmaResource->rxDmaRequest);
586 #endif
587
588 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
589 DMAMUX_SetSource(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel, (int32_t)dmaResource->rxDmaRequest);
590 DMAMUX_EnableChannel(dmaResource->rxDmamuxBase, dmaResource->rxEdmaChannel);
591
592 DMAMUX_SetSource(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel, (int32_t)dmaResource->txDmaRequest);
593 DMAMUX_EnableChannel(dmaResource->txDmamuxBase, dmaResource->txEdmaChannel);
594 #endif
595 lpspi->flags |= (uint8_t)SPI_FLAG_POWER;
596 break;
597 }
598 default:
599 result = ARM_DRIVER_ERROR_UNSUPPORTED;
600 break;
601 }
602
603 return result;
604 }
605
LPSPI_EdmaSend(const void * data,uint32_t num,cmsis_lpspi_edma_driver_state_t * lpspi)606 static int32_t LPSPI_EdmaSend(const void *data, uint32_t num, cmsis_lpspi_edma_driver_state_t *lpspi)
607 {
608 int32_t ret;
609 status_t status;
610 lpspi_transfer_t xfer = {0};
611 uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
612
613 xfer.rxData = NULL;
614 xfer.txData = (uint8_t *)data;
615 xfer.dataSize = num * ((datawidth + 8U) / 8U);
616
617 LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
618
619 if (LPSPI_IsMaster(lpspi->resource->base))
620 {
621 status = LPSPI_MasterTransferEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer);
622 }
623 else
624 {
625 status = LPSPI_SlaveTransferEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer);
626 }
627
628 switch (status)
629 {
630 case kStatus_Success:
631 ret = ARM_DRIVER_OK;
632 break;
633 case kStatus_InvalidArgument:
634 ret = ARM_DRIVER_ERROR_PARAMETER;
635 break;
636 case kStatus_LPSPI_Busy:
637 ret = ARM_DRIVER_ERROR_BUSY;
638 break;
639 default:
640 ret = ARM_DRIVER_ERROR;
641 break;
642 }
643
644 return ret;
645 }
646
LPSPI_EdmaReceive(void * data,uint32_t num,cmsis_lpspi_edma_driver_state_t * lpspi)647 static int32_t LPSPI_EdmaReceive(void *data, uint32_t num, cmsis_lpspi_edma_driver_state_t *lpspi)
648 {
649 int32_t ret;
650 status_t status;
651 lpspi_transfer_t xfer = {0};
652 uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
653
654 xfer.txData = NULL;
655 xfer.rxData = (uint8_t *)data;
656 xfer.dataSize = num * ((datawidth + 8U) / 8U);
657
658 LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
659
660 if (LPSPI_IsMaster(lpspi->resource->base))
661 {
662 status = LPSPI_MasterTransferEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer);
663 }
664 else
665 {
666 status = LPSPI_SlaveTransferEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer);
667 }
668
669 switch (status)
670 {
671 case kStatus_Success:
672 ret = ARM_DRIVER_OK;
673 break;
674 case kStatus_InvalidArgument:
675 ret = ARM_DRIVER_ERROR_PARAMETER;
676 break;
677 case kStatus_LPSPI_Busy:
678 ret = ARM_DRIVER_ERROR_BUSY;
679 break;
680 default:
681 ret = ARM_DRIVER_ERROR;
682 break;
683 }
684
685 return ret;
686 }
687
LPSPI_EdmaTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_lpspi_edma_driver_state_t * lpspi)688 static int32_t LPSPI_EdmaTransfer(const void *data_out,
689 void *data_in,
690 uint32_t num,
691 cmsis_lpspi_edma_driver_state_t *lpspi)
692 {
693 int32_t ret;
694 status_t status;
695 lpspi_transfer_t xfer = {0};
696 uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
697
698 xfer.txData = (uint8_t *)data_out;
699 xfer.rxData = (uint8_t *)data_in;
700 xfer.dataSize = num * ((datawidth + 8U) / 8U);
701
702 LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
703
704 if (LPSPI_IsMaster(lpspi->resource->base))
705 {
706 status = LPSPI_MasterTransferEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer);
707 }
708 else
709 {
710 status = LPSPI_SlaveTransferEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer);
711 }
712
713 switch (status)
714 {
715 case kStatus_Success:
716 ret = ARM_DRIVER_OK;
717 break;
718 case kStatus_InvalidArgument:
719 ret = ARM_DRIVER_ERROR_PARAMETER;
720 break;
721 case kStatus_LPSPI_Busy:
722 ret = ARM_DRIVER_ERROR_BUSY;
723 break;
724 default:
725 ret = ARM_DRIVER_ERROR;
726 break;
727 }
728
729 return ret;
730 }
LPSPI_EdmaGetCount(cmsis_lpspi_edma_driver_state_t * lpspi)731 static uint32_t LPSPI_EdmaGetCount(cmsis_lpspi_edma_driver_state_t *lpspi)
732 {
733 uint32_t cnt;
734 size_t bytes;
735 uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
736
737 if (LPSPI_IsMaster(lpspi->resource->base))
738 {
739 bytes = (uint32_t)lpspi->handle->masterHandle.nbytes *
740 EDMA_GetRemainingMajorLoopCount(lpspi->dmaResource->rxEdmaBase, lpspi->dmaResource->rxEdmaChannel);
741 cnt = lpspi->handle->masterHandle.totalByteCount - bytes;
742 }
743 else
744 {
745 bytes = (uint32_t)lpspi->handle->masterHandle.nbytes *
746 EDMA_GetRemainingMajorLoopCount(lpspi->dmaResource->rxEdmaBase, lpspi->dmaResource->rxEdmaChannel);
747 cnt = lpspi->handle->slaveHandle.totalByteCount - bytes;
748 }
749 cnt /= ((datawidth + 8U) / 8U);
750 return cnt;
751 }
752
LPSPI_EdmaControl(uint32_t control,uint32_t arg,cmsis_lpspi_edma_driver_state_t * lpspi)753 static int32_t LPSPI_EdmaControl(uint32_t control, uint32_t arg, cmsis_lpspi_edma_driver_state_t *lpspi)
754 {
755 int32_t result = ARM_DRIVER_OK;
756 bool isContinue = false;
757 if (0U == (lpspi->flags & (uint8_t)SPI_FLAG_POWER))
758 {
759 return ARM_DRIVER_ERROR;
760 }
761
762 switch (control & ARM_SPI_CONTROL_Msk)
763 {
764 case ARM_SPI_MODE_INACTIVE:
765 LPSPI_Enable(lpspi->resource->base, false);
766 break;
767 case ARM_SPI_MODE_MASTER: /* SPI Master (Output on SOUT, Input on SIN); arg = Bus Speed in bps */
768 {
769 LPSPI_MasterTransferCreateHandleEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle),
770 KSDK_LPSPI_MasterEdmaCallback, (void *)lpspi->cb_event,
771 lpspi->edmaRxRegToRxDataHandle, lpspi->edmaTxDataToTxRegHandle);
772
773 lpspi->baudRate_Bps = arg;
774 isContinue = true;
775 break;
776 }
777 case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on SOUT, Input on SIN) */
778 {
779 LPSPI_SlaveTransferCreateHandleEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle),
780 KSDK_LPSPI_SlaveEdmaCallback, (void *)lpspi->cb_event,
781 lpspi->edmaRxRegToRxDataHandle, lpspi->edmaTxDataToTxRegHandle);
782 isContinue = true;
783 break;
784 }
785 case ARM_SPI_SET_BUS_SPEED: /* Get Bus Speed in bps */
786 {
787 uint32_t tcrPrescaleValue = 0;
788 LPSPI_Enable(lpspi->resource->base, false);
789
790 if (!LPSPI_IsMaster(lpspi->resource->base))
791 {
792 result = ARM_DRIVER_ERROR_UNSUPPORTED;
793 break;
794 }
795
796 if (0UL ==
797 LPSPI_MasterSetBaudRate(lpspi->resource->base, arg, lpspi->resource->GetFreq(), &tcrPrescaleValue))
798 {
799 result = ARM_DRIVER_ERROR;
800 break;
801 }
802
803 LPSPI_Enable(lpspi->resource->base, true);
804 lpspi->baudRate_Bps = arg;
805 break;
806 }
807
808 case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */
809 if (!LPSPI_IsMaster(lpspi->resource->base))
810 {
811 result = ARM_DRIVER_ERROR_UNSUPPORTED;
812 break;
813 }
814 result = (int32_t)lpspi->baudRate_Bps;
815 break;
816 case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */
817 result = ARM_DRIVER_ERROR_UNSUPPORTED;
818 break;
819
820 case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */
821 if (LPSPI_IsMaster(lpspi->resource->base))
822 {
823 LPSPI_MasterTransferAbortEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle));
824 }
825 else
826 {
827 LPSPI_SlaveTransferAbortEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle));
828 }
829 result = ARM_DRIVER_OK;
830 break;
831
832 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
833 LPSPI_SetDummyData(lpspi->resource->base, (uint8_t)arg);
834 result = ARM_DRIVER_OK;
835 break;
836
837 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on SOUT); arg = Bus Speed in bps */
838 {
839 LPSPI_MasterTransferCreateHandleEDMA(lpspi->resource->base, &(lpspi->handle->masterHandle),
840 KSDK_LPSPI_MasterEdmaCallback, (void *)lpspi->cb_event,
841 lpspi->edmaRxRegToRxDataHandle, lpspi->edmaTxDataToTxRegHandle);
842
843 lpspi->baudRate_Bps = arg;
844 isContinue = true;
845 break;
846 }
847
848 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on SIN) */
849 {
850 LPSPI_SlaveTransferCreateHandleEDMA(lpspi->resource->base, &(lpspi->handle->slaveHandle),
851 KSDK_LPSPI_SlaveEdmaCallback, (void *)lpspi->cb_event,
852 lpspi->edmaRxRegToRxDataHandle, lpspi->edmaTxDataToTxRegHandle);
853 isContinue = true;
854 break;
855 }
856
857 default:
858 isContinue = true;
859 break;
860 }
861 if (isContinue)
862 {
863 result = LPSPI_CommonControl(control, arg, lpspi->resource, &lpspi->flags);
864 }
865
866 return result;
867 }
868
LPSPI_EdmaGetStatus(cmsis_lpspi_edma_driver_state_t * lpspi)869 static ARM_SPI_STATUS LPSPI_EdmaGetStatus(cmsis_lpspi_edma_driver_state_t *lpspi)
870 {
871 ARM_SPI_STATUS stat = {0};
872
873 if (LPSPI_IsMaster(lpspi->resource->base))
874 {
875 stat.busy = ((uint8_t)kLPSPI_Busy == lpspi->handle->masterHandle.state) ? (1U) : (0U);
876 stat.data_lost = ((uint8_t)kLPSPI_Error == lpspi->handle->masterHandle.state) ? (1U) : (0U);
877 }
878 else
879 {
880 stat.busy = ((uint8_t)kLPSPI_Busy == lpspi->handle->slaveHandle.state) ? (1U) : (0U);
881 stat.data_lost = ((uint8_t)kLPSPI_Error == lpspi->handle->slaveHandle.state) ? (1U) : (0U);
882 }
883 stat.mode_fault = 0U;
884 stat.reserved = 0U;
885
886 return stat;
887 }
888 #endif /* defined(FSL_FEATURE_SOC_EDMA_COUNT) */
889
890 #endif
891
892 #if ((defined(RTE_SPI0) && RTE_SPI0 && !RTE_SPI0_DMA_EN) || (defined(RTE_SPI1) && RTE_SPI1 && !RTE_SPI1_DMA_EN) || \
893 (defined(RTE_SPI2) && RTE_SPI2 && !RTE_SPI2_DMA_EN) || (defined(RTE_SPI3) && RTE_SPI3 && !RTE_SPI3_DMA_EN) || \
894 (defined(RTE_SPI4) && RTE_SPI4 && !RTE_SPI4_DMA_EN) || (defined(RTE_SPI5) && RTE_SPI5 && !RTE_SPI5_DMA_EN) || \
895 (defined(RTE_SPI6) && RTE_SPI6 && !RTE_SPI6_DMA_EN) || (defined(RTE_SPI7) && RTE_SPI7 && !RTE_SPI7_DMA_EN) || \
896 (defined(RTE_SPI8) && RTE_SPI8 && !RTE_SPI8_DMA_EN) || (defined(RTE_SPI9) && RTE_SPI9 && !RTE_SPI9_DMA_EN) || \
897 (defined(RTE_SPI10) && RTE_SPI10 && !RTE_SPI10_DMA_EN) || \
898 (defined(RTE_SPI11) && RTE_SPI11 && !RTE_SPI11_DMA_EN) || \
899 (defined(RTE_SPI12) && RTE_SPI12 && !RTE_SPI12_DMA_EN) || \
900 (defined(RTE_SPI13) && RTE_SPI13 && !RTE_SPI13_DMA_EN) || \
901 (defined(RTE_SPI14) && RTE_SPI14 && !RTE_SPI14_DMA_EN) || \
902 (defined(RTE_SPI15) && RTE_SPI15 && !RTE_SPI15_DMA_EN) || \
903 (defined(RTE_SPI16) && RTE_SPI16 && !RTE_SPI16_DMA_EN) || \
904 (defined(RTE_SPI17) && RTE_SPI17 && !RTE_SPI17_DMA_EN) || \
905 (defined(RTE_SPI18) && RTE_SPI18 && !RTE_SPI18_DMA_EN) || \
906 (defined(RTE_SPI19) && RTE_SPI19 && !RTE_SPI19_DMA_EN) || (defined(RTE_SPI20) && RTE_SPI20 && !RTE_SPI20_DMA_EN))
907
KSDK_LPSPI_MasterInterruptCallback(LPSPI_Type * base,lpspi_master_handle_t * handle,status_t status,void * userData)908 static void KSDK_LPSPI_MasterInterruptCallback(LPSPI_Type *base,
909 lpspi_master_handle_t *handle,
910 status_t status,
911 void *userData)
912 {
913 uint32_t event = 0U;
914
915 if (kStatus_Success == status)
916 {
917 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
918 }
919 else if (kStatus_LPSPI_Error == status)
920 {
921 event = ARM_SPI_EVENT_DATA_LOST;
922 }
923 else
924 {
925 /* Avoid MISRA 15.7 violations. */
926 }
927 /* User data is actually CMSIS driver callback. */
928 if ((0U != event) && (userData != NULL))
929 {
930 ((ARM_SPI_SignalEvent_t)userData)(event);
931 }
932 }
933
KSDK_LPSPI_SlaveInterruptCallback(LPSPI_Type * base,lpspi_slave_handle_t * handle,status_t status,void * userData)934 static void KSDK_LPSPI_SlaveInterruptCallback(LPSPI_Type *base,
935 lpspi_slave_handle_t *handle,
936 status_t status,
937 void *userData)
938 {
939 uint32_t event = 0U;
940
941 if (kStatus_Success == status)
942 {
943 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
944 }
945 if (kStatus_LPSPI_Error == status)
946 {
947 event = ARM_SPI_EVENT_DATA_LOST;
948 }
949 else
950 {
951 /* Avoid MISRA 16.4 violations. */
952 }
953 /* User data is actually CMSIS driver callback. */
954 if ((0U != event) && (userData != NULL))
955 {
956 ((ARM_SPI_SignalEvent_t)userData)(event);
957 }
958 }
959
LPSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_lpspi_interrupt_driver_state_t * lpspi)960 static int32_t LPSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_lpspi_interrupt_driver_state_t *lpspi)
961 {
962 if (0U == (lpspi->flags & (uint8_t)SPI_FLAG_INIT))
963 {
964 lpspi->cb_event = cb_event;
965 lpspi->flags = (uint8_t)SPI_FLAG_INIT;
966 }
967
968 return ARM_DRIVER_OK;
969 }
970
LPSPI_InterruptUninitialize(cmsis_lpspi_interrupt_driver_state_t * lpspi)971 static int32_t LPSPI_InterruptUninitialize(cmsis_lpspi_interrupt_driver_state_t *lpspi)
972 {
973 lpspi->flags = (uint8_t)SPI_FLAG_UNINIT;
974 return ARM_DRIVER_OK;
975 }
976
LPSPI_InterruptPowerControl(ARM_POWER_STATE state,cmsis_lpspi_interrupt_driver_state_t * lpspi)977 static int32_t LPSPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_lpspi_interrupt_driver_state_t *lpspi)
978 {
979 int32_t result = ARM_DRIVER_OK;
980 switch (state)
981 {
982 case ARM_POWER_OFF:
983 if ((lpspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
984 {
985 LPSPI_Deinit(lpspi->resource->base);
986 lpspi->flags = (uint8_t)SPI_FLAG_INIT;
987 }
988 break;
989 case ARM_POWER_LOW:
990 result = ARM_DRIVER_ERROR_UNSUPPORTED;
991 break;
992 case ARM_POWER_FULL:
993 if (lpspi->flags == (uint8_t)SPI_FLAG_UNINIT)
994 {
995 result = ARM_DRIVER_ERROR;
996 break;
997 }
998
999 if ((lpspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
1000 {
1001 /* Driver already powered */
1002 break;
1003 }
1004
1005 (void)CLOCK_EnableClock(s_lpspiClock[lpspi->resource->instance]);
1006 lpspi->flags |= (uint8_t)SPI_FLAG_POWER;
1007
1008 break;
1009 default:
1010 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1011 break;
1012 }
1013
1014 return result;
1015 }
1016
LPSPI_InterruptSend(const void * data,uint32_t num,cmsis_lpspi_interrupt_driver_state_t * lpspi)1017 static int32_t LPSPI_InterruptSend(const void *data, uint32_t num, cmsis_lpspi_interrupt_driver_state_t *lpspi)
1018 {
1019 int32_t ret;
1020 status_t status;
1021 lpspi_transfer_t xfer = {0};
1022 uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
1023
1024 xfer.rxData = NULL;
1025 xfer.txData = (uint8_t *)data;
1026 xfer.dataSize = num * ((datawidth + 8U) / 8U);
1027
1028 LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
1029
1030 if (LPSPI_IsMaster(lpspi->resource->base))
1031 {
1032 status = LPSPI_MasterTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer);
1033 }
1034 else
1035 {
1036 status = LPSPI_SlaveTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer);
1037 }
1038
1039 switch (status)
1040 {
1041 case kStatus_Success:
1042 ret = ARM_DRIVER_OK;
1043 break;
1044 case kStatus_InvalidArgument:
1045 ret = ARM_DRIVER_ERROR_PARAMETER;
1046 break;
1047 case kStatus_LPSPI_Busy:
1048 ret = ARM_DRIVER_ERROR_BUSY;
1049 break;
1050 default:
1051 ret = ARM_DRIVER_ERROR;
1052 break;
1053 }
1054
1055 return ret;
1056 }
1057
LPSPI_InterruptReceive(void * data,uint32_t num,cmsis_lpspi_interrupt_driver_state_t * lpspi)1058 static int32_t LPSPI_InterruptReceive(void *data, uint32_t num, cmsis_lpspi_interrupt_driver_state_t *lpspi)
1059 {
1060 int32_t ret;
1061 status_t status;
1062 lpspi_transfer_t xfer = {0};
1063 uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
1064
1065 xfer.txData = NULL;
1066 xfer.rxData = (uint8_t *)data;
1067 xfer.dataSize = num * ((datawidth + 8U) / 8U);
1068
1069 LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
1070
1071 if (LPSPI_IsMaster(lpspi->resource->base))
1072 {
1073 status = LPSPI_MasterTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer);
1074 }
1075 else
1076 {
1077 status = LPSPI_SlaveTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer);
1078 }
1079
1080 switch (status)
1081 {
1082 case kStatus_Success:
1083 ret = ARM_DRIVER_OK;
1084 break;
1085 case kStatus_InvalidArgument:
1086 ret = ARM_DRIVER_ERROR_PARAMETER;
1087 break;
1088 case kStatus_LPSPI_Busy:
1089 ret = ARM_DRIVER_ERROR_BUSY;
1090 break;
1091 default:
1092 ret = ARM_DRIVER_ERROR;
1093 break;
1094 }
1095
1096 return ret;
1097 }
1098
LPSPI_InterruptTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_lpspi_interrupt_driver_state_t * lpspi)1099 static int32_t LPSPI_InterruptTransfer(const void *data_out,
1100 void *data_in,
1101 uint32_t num,
1102 cmsis_lpspi_interrupt_driver_state_t *lpspi)
1103 {
1104 int32_t ret;
1105 status_t status;
1106 lpspi_transfer_t xfer = {0};
1107 uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
1108
1109 xfer.txData = (uint8_t *)data_out;
1110 xfer.rxData = (uint8_t *)data_in;
1111 xfer.dataSize = num * ((datawidth + 8U) / 8U);
1112
1113 LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
1114
1115 if (LPSPI_IsMaster(lpspi->resource->base))
1116 {
1117 status = LPSPI_MasterTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->masterHandle), &xfer);
1118 }
1119 else
1120 {
1121 status = LPSPI_SlaveTransferNonBlocking(lpspi->resource->base, &(lpspi->handle->slaveHandle), &xfer);
1122 }
1123
1124 switch (status)
1125 {
1126 case kStatus_Success:
1127 ret = ARM_DRIVER_OK;
1128 break;
1129 case kStatus_InvalidArgument:
1130 ret = ARM_DRIVER_ERROR_PARAMETER;
1131 break;
1132 case kStatus_LPSPI_Busy:
1133 ret = ARM_DRIVER_ERROR_BUSY;
1134 break;
1135 default:
1136 ret = ARM_DRIVER_ERROR;
1137 break;
1138 }
1139
1140 return ret;
1141 }
1142
LPSPI_InterruptGetCount(cmsis_lpspi_interrupt_driver_state_t * lpspi)1143 static uint32_t LPSPI_InterruptGetCount(cmsis_lpspi_interrupt_driver_state_t *lpspi)
1144 {
1145 uint32_t cnt;
1146 uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
1147 if (LPSPI_IsMaster(lpspi->resource->base))
1148 {
1149 cnt = (uint32_t)lpspi->handle->masterHandle.totalByteCount -
1150 (uint32_t)lpspi->handle->masterHandle.rxRemainingByteCount;
1151 }
1152 else
1153 {
1154 cnt = (uint32_t)lpspi->handle->slaveHandle.totalByteCount -
1155 (uint32_t)lpspi->handle->slaveHandle.rxRemainingByteCount;
1156 }
1157 cnt /= ((datawidth + 8U) / 8U);
1158
1159 return cnt;
1160 }
1161
LPSPI_InterruptControl(uint32_t control,uint32_t arg,cmsis_lpspi_interrupt_driver_state_t * lpspi)1162 static int32_t LPSPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_lpspi_interrupt_driver_state_t *lpspi)
1163 {
1164 int32_t result = ARM_DRIVER_OK;
1165 bool isContinue = false;
1166 if (0U == (lpspi->flags & (uint8_t)SPI_FLAG_POWER))
1167 {
1168 return ARM_DRIVER_ERROR;
1169 }
1170
1171 switch (control & ARM_SPI_CONTROL_Msk)
1172 {
1173 case ARM_SPI_MODE_INACTIVE:
1174 LPSPI_Enable(lpspi->resource->base, false);
1175 break;
1176 case ARM_SPI_MODE_MASTER: /* SPI Master (Output on SOUT, Input on SIN); arg = Bus Speed in bps */
1177 {
1178 LPSPI_MasterTransferCreateHandle(lpspi->resource->base, &(lpspi->handle->masterHandle),
1179 KSDK_LPSPI_MasterInterruptCallback, (void *)lpspi->cb_event);
1180 lpspi->baudRate_Bps = arg;
1181 isContinue = true;
1182 break;
1183 }
1184 case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on SOUT, Input on SIN) */
1185 {
1186 LPSPI_SlaveTransferCreateHandle(lpspi->resource->base, &(lpspi->handle->slaveHandle),
1187 KSDK_LPSPI_SlaveInterruptCallback, (void *)lpspi->cb_event);
1188 isContinue = true;
1189 break;
1190 }
1191 case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */
1192 {
1193 uint32_t tcrPrescaleValue = 0;
1194 LPSPI_Enable(lpspi->resource->base, false);
1195
1196 if (!LPSPI_IsMaster(lpspi->resource->base))
1197 {
1198 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1199 break;
1200 }
1201 if (0UL ==
1202 LPSPI_MasterSetBaudRate(lpspi->resource->base, arg, lpspi->resource->GetFreq(), &tcrPrescaleValue))
1203 {
1204 result = ARM_DRIVER_ERROR;
1205 break;
1206 }
1207
1208 LPSPI_Enable(lpspi->resource->base, true);
1209 lpspi->baudRate_Bps = arg;
1210 break;
1211 }
1212 case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */
1213 if (!LPSPI_IsMaster(lpspi->resource->base))
1214 {
1215 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1216 break;
1217 }
1218 result = (int32_t)(lpspi->baudRate_Bps);
1219 break;
1220 case ARM_SPI_CONTROL_SS: /* Control Slave Select; arg = 0:inactive, 1:active */
1221 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1222 break;
1223 case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */
1224
1225 if (LPSPI_IsMaster(lpspi->resource->base))
1226 {
1227 LPSPI_MasterTransferAbort(lpspi->resource->base, &(lpspi->handle->masterHandle));
1228 }
1229 else
1230 {
1231 LPSPI_SlaveTransferAbort(lpspi->resource->base, &(lpspi->handle->slaveHandle));
1232 }
1233 break;
1234
1235 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
1236 if (LPSPI_IsMaster(lpspi->resource->base))
1237 {
1238 LPSPI_SetDummyData(lpspi->resource->base, (uint8_t)arg);
1239 }
1240 else
1241 {
1242 /* Mode is not supported by current driver.
1243 * In slave mode, if the tx buffer is NULL, the output pin will keep tristated.
1244 */
1245 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1246 }
1247 break;
1248
1249 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on SOUT); arg = Bus Speed in bps */
1250 {
1251 LPSPI_MasterTransferCreateHandle(lpspi->resource->base, &(lpspi->handle->masterHandle),
1252 KSDK_LPSPI_MasterInterruptCallback, (void *)lpspi->cb_event);
1253 lpspi->baudRate_Bps = arg;
1254 isContinue = true;
1255 break;
1256 }
1257 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on SIN) */
1258 {
1259 LPSPI_SlaveTransferCreateHandle(lpspi->resource->base, &(lpspi->handle->slaveHandle),
1260 KSDK_LPSPI_SlaveInterruptCallback, (void *)lpspi->cb_event);
1261 isContinue = true;
1262 break;
1263 }
1264
1265 default:
1266 isContinue = true;
1267 break;
1268 }
1269 if (isContinue)
1270 {
1271 result = LPSPI_CommonControl(control, lpspi->baudRate_Bps, lpspi->resource, &lpspi->flags);
1272 }
1273 return result;
1274 }
1275
LPSPI_InterruptGetStatus(cmsis_lpspi_interrupt_driver_state_t * lpspi)1276 static ARM_SPI_STATUS LPSPI_InterruptGetStatus(cmsis_lpspi_interrupt_driver_state_t *lpspi)
1277 {
1278 ARM_SPI_STATUS stat = {0};
1279
1280 if (LPSPI_IsMaster(lpspi->resource->base))
1281 {
1282 stat.busy = ((uint8_t)kLPSPI_Busy == lpspi->handle->masterHandle.state) ? (1U) : (0U);
1283 stat.data_lost = ((uint8_t)kLPSPI_Error == lpspi->handle->masterHandle.state) ? (1U) : (0U);
1284 }
1285 else
1286 {
1287 stat.busy = ((uint8_t)kLPSPI_Busy == lpspi->handle->slaveHandle.state) ? (1U) : (0U);
1288 stat.data_lost = ((uint8_t)kLPSPI_Error == lpspi->handle->slaveHandle.state) ? (1U) : (0U);
1289 }
1290 stat.mode_fault = 0U;
1291 stat.reserved = 0U;
1292
1293 return stat;
1294 }
1295
1296 #endif
1297
1298 #if defined(LPSPI0) && defined(RTE_SPI0) && RTE_SPI0
1299
1300 /* User needs to provide the implementation for LPSPI0_GetFreq/InitPins/DeinitPins
1301 in the application for enabling according instance. */
1302 extern uint32_t LPSPI0_GetFreq(void);
1303
1304 static cmsis_lpspi_resource_t LPSPI0_Resource = {LPSPI0, 0, LPSPI0_GetFreq};
1305
1306 #if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
1307
1308 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1309 static cmsis_lpspi_edma_resource_t LPSPI0_EdmaResource = {
1310 RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, (uint16_t)RTE_SPI0_DMA_TX_PERI_SEL,
1311 RTE_SPI0_DMA_RX_DMA_BASE, RTE_SPI0_DMA_RX_CH, (uint16_t)RTE_SPI0_DMA_RX_PERI_SEL,
1312 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1313 RTE_SPI0_DMA_TX_DMAMUX_BASE, RTE_SPI0_DMA_RX_DMAMUX_BASE,
1314 #endif
1315 };
1316
1317 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI0_EdmaHandle);
1318 static edma_handle_t LPSPI0_EdmaTxDataToTxRegHandle;
1319 static edma_handle_t LPSPI0_EdmaRxRegToRxDataHandle;
1320
1321 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1322 ARMCC_SECTION("lpspi0_edma_driver_state")
1323 static cmsis_lpspi_edma_driver_state_t LPSPI0_EdmaDriverState = {
1324 #else
1325 static cmsis_lpspi_edma_driver_state_t LPSPI0_EdmaDriverState = {
1326 #endif
1327 &LPSPI0_Resource,
1328 &LPSPI0_EdmaResource,
1329 &LPSPI0_EdmaHandle,
1330 &LPSPI0_EdmaRxRegToRxDataHandle,
1331 &LPSPI0_EdmaTxDataToTxRegHandle,
1332 };
1333
LPSPI0_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)1334 static int32_t LPSPI0_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
1335 {
1336 #ifdef RTE_SPI0_PIN_INIT
1337 RTE_SPI0_PIN_INIT();
1338 #endif
1339 return LPSPI_EdmaInitialize(cb_event, &LPSPI0_EdmaDriverState);
1340 }
1341
LPSPI0_EdmaUninitialize(void)1342 static int32_t LPSPI0_EdmaUninitialize(void)
1343 {
1344 #ifdef RTE_SPI0_PIN_DEINIT
1345 RTE_SPI0_PIN_DEINIT();
1346 #endif
1347 return LPSPI_EdmaUninitialize(&LPSPI0_EdmaDriverState);
1348 }
1349
LPSPI0_EdmaPowerControl(ARM_POWER_STATE state)1350 static int32_t LPSPI0_EdmaPowerControl(ARM_POWER_STATE state)
1351 {
1352 return LPSPI_EdmaPowerControl(state, &LPSPI0_EdmaDriverState);
1353 }
1354
LPSPI0_EdmaSend(const void * data,uint32_t num)1355 static int32_t LPSPI0_EdmaSend(const void *data, uint32_t num)
1356 {
1357 return LPSPI_EdmaSend(data, num, &LPSPI0_EdmaDriverState);
1358 }
1359
LPSPI0_EdmaReceive(void * data,uint32_t num)1360 static int32_t LPSPI0_EdmaReceive(void *data, uint32_t num)
1361 {
1362 return LPSPI_EdmaReceive(data, num, &LPSPI0_EdmaDriverState);
1363 }
1364
LPSPI0_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1365 static int32_t LPSPI0_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1366 {
1367 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI0_EdmaDriverState);
1368 }
1369
LPSPI0_EdmaGetCount(void)1370 static uint32_t LPSPI0_EdmaGetCount(void)
1371 {
1372 return LPSPI_EdmaGetCount(&LPSPI0_EdmaDriverState);
1373 }
1374
LPSPI0_EdmaControl(uint32_t control,uint32_t arg)1375 static int32_t LPSPI0_EdmaControl(uint32_t control, uint32_t arg)
1376 {
1377 return LPSPI_EdmaControl(control, arg, &LPSPI0_EdmaDriverState);
1378 }
1379
LPSPI0_EdmaGetStatus(void)1380 static ARM_SPI_STATUS LPSPI0_EdmaGetStatus(void)
1381 {
1382 return LPSPI_EdmaGetStatus(&LPSPI0_EdmaDriverState);
1383 }
1384
1385 #endif
1386
1387 #else
1388
1389 static cmsis_lpspi_handle_t LPSPI0_Handle;
1390
1391 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1392 ARMCC_SECTION("lpspi0_interrupt_driver_state")
1393 static cmsis_lpspi_interrupt_driver_state_t LPSPI0_InterruptDriverState = {
1394 #else
1395 static cmsis_lpspi_interrupt_driver_state_t LPSPI0_InterruptDriverState = {
1396 #endif
1397 &LPSPI0_Resource,
1398 &LPSPI0_Handle,
1399 };
1400
LPSPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1401 static int32_t LPSPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1402 {
1403 #ifdef RTE_SPI0_PIN_INIT
1404 RTE_SPI0_PIN_INIT();
1405 #endif
1406 return LPSPI_InterruptInitialize(cb_event, &LPSPI0_InterruptDriverState);
1407 }
1408
LPSPI0_InterruptUninitialize(void)1409 static int32_t LPSPI0_InterruptUninitialize(void)
1410 {
1411 #ifdef RTE_SPI0_PIN_DEINIT
1412 RTE_SPI0_PIN_DEINIT();
1413 #endif
1414 return LPSPI_InterruptUninitialize(&LPSPI0_InterruptDriverState);
1415 }
1416
LPSPI0_InterruptPowerControl(ARM_POWER_STATE state)1417 static int32_t LPSPI0_InterruptPowerControl(ARM_POWER_STATE state)
1418 {
1419 return LPSPI_InterruptPowerControl(state, &LPSPI0_InterruptDriverState);
1420 }
1421
LPSPI0_InterruptSend(const void * data,uint32_t num)1422 static int32_t LPSPI0_InterruptSend(const void *data, uint32_t num)
1423 {
1424 return LPSPI_InterruptSend(data, num, &LPSPI0_InterruptDriverState);
1425 }
1426
LPSPI0_InterruptReceive(void * data,uint32_t num)1427 static int32_t LPSPI0_InterruptReceive(void *data, uint32_t num)
1428 {
1429 return LPSPI_InterruptReceive(data, num, &LPSPI0_InterruptDriverState);
1430 }
1431
LPSPI0_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1432 static int32_t LPSPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1433 {
1434 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI0_InterruptDriverState);
1435 }
1436
LPSPI0_InterruptGetCount(void)1437 static uint32_t LPSPI0_InterruptGetCount(void)
1438 {
1439 return LPSPI_InterruptGetCount(&LPSPI0_InterruptDriverState);
1440 }
1441
LPSPI0_InterruptControl(uint32_t control,uint32_t arg)1442 static int32_t LPSPI0_InterruptControl(uint32_t control, uint32_t arg)
1443 {
1444 return LPSPI_InterruptControl(control, arg, &LPSPI0_InterruptDriverState);
1445 }
1446
LPSPI0_InterruptGetStatus(void)1447 static ARM_SPI_STATUS LPSPI0_InterruptGetStatus(void)
1448 {
1449 return LPSPI_InterruptGetStatus(&LPSPI0_InterruptDriverState);
1450 }
1451
1452 #endif
1453
1454 ARM_DRIVER_SPI Driver_SPI0 = {
1455 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
1456 #if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
1457 LPSPI0_EdmaInitialize, LPSPI0_EdmaUninitialize, LPSPI0_EdmaPowerControl, LPSPI0_EdmaSend, LPSPI0_EdmaReceive,
1458 LPSPI0_EdmaTransfer, LPSPI0_EdmaGetCount, LPSPI0_EdmaControl, LPSPI0_EdmaGetStatus
1459 #else
1460 LPSPI0_InterruptInitialize, LPSPI0_InterruptUninitialize, LPSPI0_InterruptPowerControl, LPSPI0_InterruptSend,
1461 LPSPI0_InterruptReceive, LPSPI0_InterruptTransfer, LPSPI0_InterruptGetCount, LPSPI0_InterruptControl,
1462 LPSPI0_InterruptGetStatus
1463 #endif
1464 };
1465
1466 #endif /* LPSPI0 */
1467
1468 #if defined(LPSPI1) && defined(RTE_SPI1) && RTE_SPI1
1469
1470 /* User needs to provide the implementation for LPSPI1_GetFreq/InitPins/DeinitPins
1471 in the application for enabling according instance. */
1472 extern uint32_t LPSPI1_GetFreq(void);
1473
1474 static cmsis_lpspi_resource_t LPSPI1_Resource = {LPSPI1, 1, LPSPI1_GetFreq};
1475
1476 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1477
1478 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1479 static cmsis_lpspi_edma_resource_t LPSPI1_EdmaResource = {
1480 RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, (uint16_t)RTE_SPI1_DMA_TX_PERI_SEL,
1481 RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, (uint16_t)RTE_SPI1_DMA_RX_PERI_SEL,
1482 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1483 RTE_SPI1_DMA_TX_DMAMUX_BASE, RTE_SPI1_DMA_RX_DMAMUX_BASE,
1484 #endif
1485 };
1486
1487 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI1_EdmaHandle);
1488 static edma_handle_t LPSPI1_EdmaTxDataToTxRegHandle;
1489 static edma_handle_t LPSPI1_EdmaRxRegToRxDataHandle;
1490
1491 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1492 ARMCC_SECTION("lpspi1_edma_driver_state")
1493 static cmsis_lpspi_edma_driver_state_t LPSPI1_EdmaDriverState = {
1494 #else
1495 static cmsis_lpspi_edma_driver_state_t LPSPI1_EdmaDriverState = {
1496 #endif
1497 &LPSPI1_Resource,
1498 &LPSPI1_EdmaResource,
1499 &LPSPI1_EdmaHandle,
1500 &LPSPI1_EdmaRxRegToRxDataHandle,
1501 &LPSPI1_EdmaTxDataToTxRegHandle,
1502 };
1503
LPSPI1_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)1504 static int32_t LPSPI1_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
1505 {
1506 #ifdef RTE_SPI1_PIN_INIT
1507 RTE_SPI1_PIN_INIT();
1508 #endif
1509 return LPSPI_EdmaInitialize(cb_event, &LPSPI1_EdmaDriverState);
1510 }
1511
LPSPI1_EdmaUninitialize(void)1512 static int32_t LPSPI1_EdmaUninitialize(void)
1513 {
1514 #ifdef RTE_SPI1_PIN_DEINIT
1515 RTE_SPI1_PIN_DEINIT();
1516 #endif
1517 return LPSPI_EdmaUninitialize(&LPSPI1_EdmaDriverState);
1518 }
1519
LPSPI1_EdmaPowerControl(ARM_POWER_STATE state)1520 static int32_t LPSPI1_EdmaPowerControl(ARM_POWER_STATE state)
1521 {
1522 return LPSPI_EdmaPowerControl(state, &LPSPI1_EdmaDriverState);
1523 }
1524
LPSPI1_EdmaSend(const void * data,uint32_t num)1525 static int32_t LPSPI1_EdmaSend(const void *data, uint32_t num)
1526 {
1527 return LPSPI_EdmaSend(data, num, &LPSPI1_EdmaDriverState);
1528 }
1529
LPSPI1_EdmaReceive(void * data,uint32_t num)1530 static int32_t LPSPI1_EdmaReceive(void *data, uint32_t num)
1531 {
1532 return LPSPI_EdmaReceive(data, num, &LPSPI1_EdmaDriverState);
1533 }
1534
LPSPI1_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1535 static int32_t LPSPI1_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1536 {
1537 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI1_EdmaDriverState);
1538 }
1539
LPSPI1_EdmaGetCount(void)1540 static uint32_t LPSPI1_EdmaGetCount(void)
1541 {
1542 return LPSPI_EdmaGetCount(&LPSPI1_EdmaDriverState);
1543 }
1544
LPSPI1_EdmaControl(uint32_t control,uint32_t arg)1545 static int32_t LPSPI1_EdmaControl(uint32_t control, uint32_t arg)
1546 {
1547 return LPSPI_EdmaControl(control, arg, &LPSPI1_EdmaDriverState);
1548 }
1549
LPSPI1_EdmaGetStatus(void)1550 static ARM_SPI_STATUS LPSPI1_EdmaGetStatus(void)
1551 {
1552 return LPSPI_EdmaGetStatus(&LPSPI1_EdmaDriverState);
1553 }
1554
1555 #endif
1556
1557 #else
1558
1559 static cmsis_lpspi_handle_t LPSPI1_Handle;
1560
1561 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1562 ARMCC_SECTION("lpspi1_interrupt_driver_state")
1563 static cmsis_lpspi_interrupt_driver_state_t LPSPI1_InterruptDriverState = {
1564 #else
1565 static cmsis_lpspi_interrupt_driver_state_t LPSPI1_InterruptDriverState = {
1566 #endif
1567 &LPSPI1_Resource,
1568 &LPSPI1_Handle,
1569 };
1570
LPSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1571 static int32_t LPSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1572 {
1573 #ifdef RTE_SPI1_PIN_INIT
1574 RTE_SPI1_PIN_INIT();
1575 #endif
1576 return LPSPI_InterruptInitialize(cb_event, &LPSPI1_InterruptDriverState);
1577 }
1578
LPSPI1_InterruptUninitialize(void)1579 static int32_t LPSPI1_InterruptUninitialize(void)
1580 {
1581 #ifdef RTE_SPI1_PIN_DEINIT
1582 RTE_SPI1_PIN_DEINIT();
1583 #endif
1584 return LPSPI_InterruptUninitialize(&LPSPI1_InterruptDriverState);
1585 }
1586
LPSPI1_InterruptPowerControl(ARM_POWER_STATE state)1587 static int32_t LPSPI1_InterruptPowerControl(ARM_POWER_STATE state)
1588 {
1589 return LPSPI_InterruptPowerControl(state, &LPSPI1_InterruptDriverState);
1590 }
1591
LPSPI1_InterruptSend(const void * data,uint32_t num)1592 static int32_t LPSPI1_InterruptSend(const void *data, uint32_t num)
1593 {
1594 return LPSPI_InterruptSend(data, num, &LPSPI1_InterruptDriverState);
1595 }
1596
LPSPI1_InterruptReceive(void * data,uint32_t num)1597 static int32_t LPSPI1_InterruptReceive(void *data, uint32_t num)
1598 {
1599 return LPSPI_InterruptReceive(data, num, &LPSPI1_InterruptDriverState);
1600 }
1601
LPSPI1_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1602 static int32_t LPSPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1603 {
1604 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI1_InterruptDriverState);
1605 }
1606
LPSPI1_InterruptGetCount(void)1607 static uint32_t LPSPI1_InterruptGetCount(void)
1608 {
1609 return LPSPI_InterruptGetCount(&LPSPI1_InterruptDriverState);
1610 }
1611
LPSPI1_InterruptControl(uint32_t control,uint32_t arg)1612 static int32_t LPSPI1_InterruptControl(uint32_t control, uint32_t arg)
1613 {
1614 return LPSPI_InterruptControl(control, arg, &LPSPI1_InterruptDriverState);
1615 }
1616
LPSPI1_InterruptGetStatus(void)1617 static ARM_SPI_STATUS LPSPI1_InterruptGetStatus(void)
1618 {
1619 return LPSPI_InterruptGetStatus(&LPSPI1_InterruptDriverState);
1620 }
1621
1622 #endif
1623
1624 ARM_DRIVER_SPI Driver_SPI1 = {
1625 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
1626 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1627 LPSPI1_EdmaInitialize, LPSPI1_EdmaUninitialize, LPSPI1_EdmaPowerControl, LPSPI1_EdmaSend, LPSPI1_EdmaReceive,
1628 LPSPI1_EdmaTransfer, LPSPI1_EdmaGetCount, LPSPI1_EdmaControl, LPSPI1_EdmaGetStatus
1629 #else
1630 LPSPI1_InterruptInitialize, LPSPI1_InterruptUninitialize, LPSPI1_InterruptPowerControl, LPSPI1_InterruptSend,
1631 LPSPI1_InterruptReceive, LPSPI1_InterruptTransfer, LPSPI1_InterruptGetCount, LPSPI1_InterruptControl,
1632 LPSPI1_InterruptGetStatus
1633 #endif
1634 };
1635
1636 #endif /* LPSPI1 */
1637
1638 #if defined(LPSPI2) && defined(RTE_SPI2) && RTE_SPI2
1639
1640 /* User needs to provide the implementation for LPSPI2_GetFreq/InitPins/DeinitPins
1641 in the application for enabling according instance. */
1642 extern uint32_t LPSPI2_GetFreq(void);
1643
1644 static cmsis_lpspi_resource_t LPSPI2_Resource = {LPSPI2, 2, LPSPI2_GetFreq};
1645
1646 #if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
1647
1648 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1649 static cmsis_lpspi_edma_resource_t LPSPI2_EdmaResource = {
1650 RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, (uint16_t)RTE_SPI2_DMA_TX_PERI_SEL,
1651 RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH, (uint16_t)RTE_SPI2_DMA_RX_PERI_SEL,
1652 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1653 RTE_SPI2_DMA_TX_DMAMUX_BASE, RTE_SPI2_DMA_RX_DMAMUX_BASE,
1654 #endif
1655 };
1656
1657 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI2_EdmaHandle);
1658 static edma_handle_t LPSPI2_EdmaTxDataToTxRegHandle;
1659 static edma_handle_t LPSPI2_EdmaRxRegToRxDataHandle;
1660
1661 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1662 ARMCC_SECTION("lpspi2_edma_driver_state")
1663 static cmsis_lpspi_edma_driver_state_t LPSPI2_EdmaDriverState = {
1664 #else
1665 static cmsis_lpspi_edma_driver_state_t LPSPI2_EdmaDriverState = {
1666 #endif
1667 &LPSPI2_Resource,
1668 &LPSPI2_EdmaResource,
1669 &LPSPI2_EdmaHandle,
1670 &LPSPI2_EdmaRxRegToRxDataHandle,
1671 &LPSPI2_EdmaTxDataToTxRegHandle,
1672 };
1673
LPSPI2_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)1674 static int32_t LPSPI2_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
1675 {
1676 #ifdef RTE_SPI2_PIN_INIT
1677 RTE_SPI2_PIN_INIT();
1678 #endif
1679 return LPSPI_EdmaInitialize(cb_event, &LPSPI2_EdmaDriverState);
1680 }
1681
LPSPI2_EdmaUninitialize(void)1682 static int32_t LPSPI2_EdmaUninitialize(void)
1683 {
1684 #ifdef RTE_SPI2_PIN_DEINIT
1685 RTE_SPI2_PIN_DEINIT();
1686 #endif
1687 return LPSPI_EdmaUninitialize(&LPSPI2_EdmaDriverState);
1688 }
1689
LPSPI2_EdmaPowerControl(ARM_POWER_STATE state)1690 static int32_t LPSPI2_EdmaPowerControl(ARM_POWER_STATE state)
1691 {
1692 return LPSPI_EdmaPowerControl(state, &LPSPI2_EdmaDriverState);
1693 }
1694
LPSPI2_EdmaSend(const void * data,uint32_t num)1695 static int32_t LPSPI2_EdmaSend(const void *data, uint32_t num)
1696 {
1697 return LPSPI_EdmaSend(data, num, &LPSPI2_EdmaDriverState);
1698 }
1699
LPSPI2_EdmaReceive(void * data,uint32_t num)1700 static int32_t LPSPI2_EdmaReceive(void *data, uint32_t num)
1701 {
1702 return LPSPI_EdmaReceive(data, num, &LPSPI2_EdmaDriverState);
1703 }
1704
LPSPI2_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1705 static int32_t LPSPI2_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1706 {
1707 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI2_EdmaDriverState);
1708 }
1709
LPSPI2_EdmaGetCount(void)1710 static uint32_t LPSPI2_EdmaGetCount(void)
1711 {
1712 return LPSPI_EdmaGetCount(&LPSPI2_EdmaDriverState);
1713 }
1714
LPSPI2_EdmaControl(uint32_t control,uint32_t arg)1715 static int32_t LPSPI2_EdmaControl(uint32_t control, uint32_t arg)
1716 {
1717 return LPSPI_EdmaControl(control, arg, &LPSPI2_EdmaDriverState);
1718 }
1719
LPSPI2_EdmaGetStatus(void)1720 static ARM_SPI_STATUS LPSPI2_EdmaGetStatus(void)
1721 {
1722 return LPSPI_EdmaGetStatus(&LPSPI2_EdmaDriverState);
1723 }
1724
1725 #endif
1726
1727 #else
1728
1729 static cmsis_lpspi_handle_t LPSPI2_Handle;
1730
1731 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1732 ARMCC_SECTION("lpspi2_interrupt_driver_state")
1733 static cmsis_lpspi_interrupt_driver_state_t LPSPI2_InterruptDriverState = {
1734 #else
1735 static cmsis_lpspi_interrupt_driver_state_t LPSPI2_InterruptDriverState = {
1736 #endif
1737 &LPSPI2_Resource,
1738 &LPSPI2_Handle,
1739 };
1740
LPSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1741 static int32_t LPSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1742 {
1743 #ifdef RTE_SPI2_PIN_INIT
1744 RTE_SPI2_PIN_INIT();
1745 #endif
1746 return LPSPI_InterruptInitialize(cb_event, &LPSPI2_InterruptDriverState);
1747 }
1748
LPSPI2_InterruptUninitialize(void)1749 static int32_t LPSPI2_InterruptUninitialize(void)
1750 {
1751 #ifdef RTE_SPI2_PIN_DEINIT
1752 RTE_SPI2_PIN_DEINIT();
1753 #endif
1754 return LPSPI_InterruptUninitialize(&LPSPI2_InterruptDriverState);
1755 }
1756
LPSPI2_InterruptPowerControl(ARM_POWER_STATE state)1757 static int32_t LPSPI2_InterruptPowerControl(ARM_POWER_STATE state)
1758 {
1759 return LPSPI_InterruptPowerControl(state, &LPSPI2_InterruptDriverState);
1760 }
1761
LPSPI2_InterruptSend(const void * data,uint32_t num)1762 static int32_t LPSPI2_InterruptSend(const void *data, uint32_t num)
1763 {
1764 return LPSPI_InterruptSend(data, num, &LPSPI2_InterruptDriverState);
1765 }
1766
LPSPI2_InterruptReceive(void * data,uint32_t num)1767 static int32_t LPSPI2_InterruptReceive(void *data, uint32_t num)
1768 {
1769 return LPSPI_InterruptReceive(data, num, &LPSPI2_InterruptDriverState);
1770 }
1771
LPSPI2_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1772 static int32_t LPSPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1773 {
1774 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI2_InterruptDriverState);
1775 }
1776
LPSPI2_InterruptGetCount(void)1777 static uint32_t LPSPI2_InterruptGetCount(void)
1778 {
1779 return LPSPI_InterruptGetCount(&LPSPI2_InterruptDriverState);
1780 }
1781
LPSPI2_InterruptControl(uint32_t control,uint32_t arg)1782 static int32_t LPSPI2_InterruptControl(uint32_t control, uint32_t arg)
1783 {
1784 return LPSPI_InterruptControl(control, arg, &LPSPI2_InterruptDriverState);
1785 }
1786
LPSPI2_InterruptGetStatus(void)1787 static ARM_SPI_STATUS LPSPI2_InterruptGetStatus(void)
1788 {
1789 return LPSPI_InterruptGetStatus(&LPSPI2_InterruptDriverState);
1790 }
1791
1792 #endif
1793
1794 ARM_DRIVER_SPI Driver_SPI2 = {
1795 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
1796 #if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
1797 LPSPI2_EdmaInitialize, LPSPI2_EdmaUninitialize, LPSPI2_EdmaPowerControl, LPSPI2_EdmaSend, LPSPI2_EdmaReceive,
1798 LPSPI2_EdmaTransfer, LPSPI2_EdmaGetCount, LPSPI2_EdmaControl, LPSPI2_EdmaGetStatus
1799 #else
1800 LPSPI2_InterruptInitialize, LPSPI2_InterruptUninitialize, LPSPI2_InterruptPowerControl, LPSPI2_InterruptSend,
1801 LPSPI2_InterruptReceive, LPSPI2_InterruptTransfer, LPSPI2_InterruptGetCount, LPSPI2_InterruptControl,
1802 LPSPI2_InterruptGetStatus
1803 #endif
1804 };
1805
1806 #endif /* LPSPI2 */
1807
1808 #if defined(LPSPI3) && defined(RTE_SPI3) && RTE_SPI3
1809
1810 /* User needs to provide the implementation for LPSPI3_GetFreq/InitPins/DeinitPins
1811 in the application for enabling according instance. */
1812 extern uint32_t LPSPI3_GetFreq(void);
1813
1814 static cmsis_lpspi_resource_t LPSPI3_Resource = {LPSPI3, 3, LPSPI3_GetFreq};
1815
1816 #if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN
1817
1818 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1819 static cmsis_lpspi_edma_resource_t LPSPI3_EdmaResource = {
1820 RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, (uint16_t)RTE_SPI3_DMA_TX_PERI_SEL,
1821 RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH, (uint16_t)RTE_SPI3_DMA_RX_PERI_SEL,
1822 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1823 RTE_SPI3_DMA_TX_DMAMUX_BASE, RTE_SPI3_DMA_RX_DMAMUX_BASE,
1824 #endif
1825 };
1826
1827 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI3_EdmaHandle);
1828 static edma_handle_t LPSPI3_EdmaTxDataToTxRegHandle;
1829 static edma_handle_t LPSPI3_EdmaRxRegToRxDataHandle;
1830
1831 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1832 ARMCC_SECTION("lpspi3_edma_driver_state")
1833 static cmsis_lpspi_edma_driver_state_t LPSPI3_EdmaDriverState = {
1834 #else
1835 static cmsis_lpspi_edma_driver_state_t LPSPI3_EdmaDriverState = {
1836 #endif
1837 &LPSPI3_Resource,
1838 &LPSPI3_EdmaResource,
1839 &LPSPI3_EdmaHandle,
1840 &LPSPI3_EdmaRxRegToRxDataHandle,
1841 &LPSPI3_EdmaTxDataToTxRegHandle,
1842 };
1843
LPSPI3_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)1844 static int32_t LPSPI3_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
1845 {
1846 #ifdef RTE_SPI3_PIN_INIT
1847 RTE_SPI3_PIN_INIT();
1848 #endif
1849 return LPSPI_EdmaInitialize(cb_event, &LPSPI3_EdmaDriverState);
1850 }
1851
LPSPI3_EdmaUninitialize(void)1852 static int32_t LPSPI3_EdmaUninitialize(void)
1853 {
1854 #ifdef RTE_SPI3_PIN_DEINIT
1855 RTE_SPI3_PIN_DEINIT();
1856 #endif
1857 return LPSPI_EdmaUninitialize(&LPSPI3_EdmaDriverState);
1858 }
1859
LPSPI3_EdmaPowerControl(ARM_POWER_STATE state)1860 static int32_t LPSPI3_EdmaPowerControl(ARM_POWER_STATE state)
1861 {
1862 return LPSPI_EdmaPowerControl(state, &LPSPI3_EdmaDriverState);
1863 }
1864
LPSPI3_EdmaSend(const void * data,uint32_t num)1865 static int32_t LPSPI3_EdmaSend(const void *data, uint32_t num)
1866 {
1867 return LPSPI_EdmaSend(data, num, &LPSPI3_EdmaDriverState);
1868 }
1869
LPSPI3_EdmaReceive(void * data,uint32_t num)1870 static int32_t LPSPI3_EdmaReceive(void *data, uint32_t num)
1871 {
1872 return LPSPI_EdmaReceive(data, num, &LPSPI3_EdmaDriverState);
1873 }
1874
LPSPI3_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)1875 static int32_t LPSPI3_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
1876 {
1877 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI3_EdmaDriverState);
1878 }
1879
LPSPI3_EdmaGetCount(void)1880 static uint32_t LPSPI3_EdmaGetCount(void)
1881 {
1882 return LPSPI_EdmaGetCount(&LPSPI3_EdmaDriverState);
1883 }
1884
LPSPI3_EdmaControl(uint32_t control,uint32_t arg)1885 static int32_t LPSPI3_EdmaControl(uint32_t control, uint32_t arg)
1886 {
1887 return LPSPI_EdmaControl(control, arg, &LPSPI3_EdmaDriverState);
1888 }
1889
LPSPI3_EdmaGetStatus(void)1890 static ARM_SPI_STATUS LPSPI3_EdmaGetStatus(void)
1891 {
1892 return LPSPI_EdmaGetStatus(&LPSPI3_EdmaDriverState);
1893 }
1894
1895 #endif
1896
1897 #else
1898
1899 static cmsis_lpspi_handle_t LPSPI3_Handle;
1900
1901 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1902 ARMCC_SECTION("lpspi3_interrupt_driver_state")
1903 static cmsis_lpspi_interrupt_driver_state_t LPSPI3_InterruptDriverState = {
1904 #else
1905 static cmsis_lpspi_interrupt_driver_state_t LPSPI3_InterruptDriverState = {
1906 #endif
1907 &LPSPI3_Resource,
1908 &LPSPI3_Handle,
1909 };
1910
LPSPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1911 static int32_t LPSPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1912 {
1913 #ifdef RTE_SPI3_PIN_INIT
1914 RTE_SPI3_PIN_INIT();
1915 #endif
1916 return LPSPI_InterruptInitialize(cb_event, &LPSPI3_InterruptDriverState);
1917 }
1918
LPSPI3_InterruptUninitialize(void)1919 static int32_t LPSPI3_InterruptUninitialize(void)
1920 {
1921 #ifdef RTE_SPI3_PIN_DEINIT
1922 RTE_SPI3_PIN_DEINIT();
1923 #endif
1924 return LPSPI_InterruptUninitialize(&LPSPI3_InterruptDriverState);
1925 }
1926
LPSPI3_InterruptPowerControl(ARM_POWER_STATE state)1927 static int32_t LPSPI3_InterruptPowerControl(ARM_POWER_STATE state)
1928 {
1929 return LPSPI_InterruptPowerControl(state, &LPSPI3_InterruptDriverState);
1930 }
1931
LPSPI3_InterruptSend(const void * data,uint32_t num)1932 static int32_t LPSPI3_InterruptSend(const void *data, uint32_t num)
1933 {
1934 return LPSPI_InterruptSend(data, num, &LPSPI3_InterruptDriverState);
1935 }
1936
LPSPI3_InterruptReceive(void * data,uint32_t num)1937 static int32_t LPSPI3_InterruptReceive(void *data, uint32_t num)
1938 {
1939 return LPSPI_InterruptReceive(data, num, &LPSPI3_InterruptDriverState);
1940 }
1941
LPSPI3_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1942 static int32_t LPSPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1943 {
1944 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI3_InterruptDriverState);
1945 }
1946
LPSPI3_InterruptGetCount(void)1947 static uint32_t LPSPI3_InterruptGetCount(void)
1948 {
1949 return LPSPI_InterruptGetCount(&LPSPI3_InterruptDriverState);
1950 }
1951
LPSPI3_InterruptControl(uint32_t control,uint32_t arg)1952 static int32_t LPSPI3_InterruptControl(uint32_t control, uint32_t arg)
1953 {
1954 return LPSPI_InterruptControl(control, arg, &LPSPI3_InterruptDriverState);
1955 }
1956
LPSPI3_InterruptGetStatus(void)1957 static ARM_SPI_STATUS LPSPI3_InterruptGetStatus(void)
1958 {
1959 return LPSPI_InterruptGetStatus(&LPSPI3_InterruptDriverState);
1960 }
1961
1962 #endif
1963
1964 ARM_DRIVER_SPI Driver_SPI3 = {
1965 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
1966 #if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN
1967 LPSPI3_EdmaInitialize, LPSPI3_EdmaUninitialize, LPSPI3_EdmaPowerControl, LPSPI3_EdmaSend, LPSPI3_EdmaReceive,
1968 LPSPI3_EdmaTransfer, LPSPI3_EdmaGetCount, LPSPI3_EdmaControl, LPSPI3_EdmaGetStatus
1969 #else
1970 LPSPI3_InterruptInitialize, LPSPI3_InterruptUninitialize, LPSPI3_InterruptPowerControl, LPSPI3_InterruptSend,
1971 LPSPI3_InterruptReceive, LPSPI3_InterruptTransfer, LPSPI3_InterruptGetCount, LPSPI3_InterruptControl,
1972 LPSPI3_InterruptGetStatus
1973 #endif
1974 };
1975
1976 #endif /* LPSPI3 */
1977
1978 #if defined(LPSPI4) && defined(RTE_SPI4) && RTE_SPI4
1979
1980 /* User needs to provide the implementation for LPSPI4_GetFreq/InitPins/DeinitPins
1981 in the application for enabling according instance. */
1982 extern uint32_t LPSPI4_GetFreq(void);
1983
1984 static cmsis_lpspi_resource_t LPSPI4_Resource = {LPSPI4, 4, LPSPI4_GetFreq};
1985
1986 #if defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN
1987
1988 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
1989 static cmsis_lpspi_edma_resource_t LPSPI4_EdmaResource = {
1990 RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH, (uint16_t)RTE_SPI4_DMA_TX_PERI_SEL,
1991 RTE_SPI4_DMA_RX_DMA_BASE, RTE_SPI4_DMA_RX_CH, (uint16_t)RTE_SPI4_DMA_RX_PERI_SEL,
1992 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
1993 RTE_SPI4_DMA_TX_DMAMUX_BASE, RTE_SPI4_DMA_RX_DMAMUX_BASE,
1994 #endif
1995 };
1996
1997 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI4_EdmaHandle);
1998 static edma_handle_t LPSPI4_EdmaTxDataToTxRegHandle;
1999 static edma_handle_t LPSPI4_EdmaRxRegToRxDataHandle;
2000
2001 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2002 ARMCC_SECTION("lpspi4_edma_driver_state")
2003 static cmsis_lpspi_edma_driver_state_t LPSPI4_EdmaDriverState = {
2004 #else
2005 static cmsis_lpspi_edma_driver_state_t LPSPI4_EdmaDriverState = {
2006 #endif
2007 &LPSPI4_Resource,
2008 &LPSPI4_EdmaResource,
2009 &LPSPI4_EdmaHandle,
2010 &LPSPI4_EdmaRxRegToRxDataHandle,
2011 &LPSPI4_EdmaTxDataToTxRegHandle,
2012 };
2013
LPSPI4_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)2014 static int32_t LPSPI4_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
2015 {
2016 #ifdef RTE_SPI4_PIN_INIT
2017 RTE_SPI4_PIN_INIT();
2018 #endif
2019 return LPSPI_EdmaInitialize(cb_event, &LPSPI4_EdmaDriverState);
2020 }
2021
LPSPI4_EdmaUninitialize(void)2022 static int32_t LPSPI4_EdmaUninitialize(void)
2023 {
2024 #ifdef RTE_SPI4_PIN_DEINIT
2025 RTE_SPI4_PIN_DEINIT();
2026 #endif
2027 return LPSPI_EdmaUninitialize(&LPSPI4_EdmaDriverState);
2028 }
2029
LPSPI4_EdmaPowerControl(ARM_POWER_STATE state)2030 static int32_t LPSPI4_EdmaPowerControl(ARM_POWER_STATE state)
2031 {
2032 return LPSPI_EdmaPowerControl(state, &LPSPI4_EdmaDriverState);
2033 }
2034
LPSPI4_EdmaSend(const void * data,uint32_t num)2035 static int32_t LPSPI4_EdmaSend(const void *data, uint32_t num)
2036 {
2037 return LPSPI_EdmaSend(data, num, &LPSPI4_EdmaDriverState);
2038 }
2039
LPSPI4_EdmaReceive(void * data,uint32_t num)2040 static int32_t LPSPI4_EdmaReceive(void *data, uint32_t num)
2041 {
2042 return LPSPI_EdmaReceive(data, num, &LPSPI4_EdmaDriverState);
2043 }
2044
LPSPI4_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2045 static int32_t LPSPI4_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2046 {
2047 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI4_EdmaDriverState);
2048 }
2049
LPSPI4_EdmaGetCount(void)2050 static uint32_t LPSPI4_EdmaGetCount(void)
2051 {
2052 return LPSPI_EdmaGetCount(&LPSPI4_EdmaDriverState);
2053 }
2054
LPSPI4_EdmaControl(uint32_t control,uint32_t arg)2055 static int32_t LPSPI4_EdmaControl(uint32_t control, uint32_t arg)
2056 {
2057 return LPSPI_EdmaControl(control, arg, &LPSPI4_EdmaDriverState);
2058 }
2059
LPSPI4_EdmaGetStatus(void)2060 static ARM_SPI_STATUS LPSPI4_EdmaGetStatus(void)
2061 {
2062 return LPSPI_EdmaGetStatus(&LPSPI4_EdmaDriverState);
2063 }
2064
2065 #endif
2066
2067 #else
2068
2069 static cmsis_lpspi_handle_t LPSPI4_Handle;
2070
2071 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2072 ARMCC_SECTION("lpspi4_interrupt_driver_state")
2073 static cmsis_lpspi_interrupt_driver_state_t LPSPI4_InterruptDriverState = {
2074 #else
2075 static cmsis_lpspi_interrupt_driver_state_t LPSPI4_InterruptDriverState = {
2076 #endif
2077 &LPSPI4_Resource,
2078 &LPSPI4_Handle,
2079 };
2080
LPSPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2081 static int32_t LPSPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2082 {
2083 #ifdef RTE_SPI4_PIN_INIT
2084 RTE_SPI4_PIN_INIT();
2085 #endif
2086 return LPSPI_InterruptInitialize(cb_event, &LPSPI4_InterruptDriverState);
2087 }
2088
LPSPI4_InterruptUninitialize(void)2089 static int32_t LPSPI4_InterruptUninitialize(void)
2090 {
2091 #ifdef RTE_SPI4_PIN_DEINIT
2092 RTE_SPI4_PIN_DEINIT();
2093 #endif
2094 return LPSPI_InterruptUninitialize(&LPSPI4_InterruptDriverState);
2095 }
2096
LPSPI4_InterruptPowerControl(ARM_POWER_STATE state)2097 static int32_t LPSPI4_InterruptPowerControl(ARM_POWER_STATE state)
2098 {
2099 return LPSPI_InterruptPowerControl(state, &LPSPI4_InterruptDriverState);
2100 }
2101
LPSPI4_InterruptSend(const void * data,uint32_t num)2102 static int32_t LPSPI4_InterruptSend(const void *data, uint32_t num)
2103 {
2104 return LPSPI_InterruptSend(data, num, &LPSPI4_InterruptDriverState);
2105 }
2106
LPSPI4_InterruptReceive(void * data,uint32_t num)2107 static int32_t LPSPI4_InterruptReceive(void *data, uint32_t num)
2108 {
2109 return LPSPI_InterruptReceive(data, num, &LPSPI4_InterruptDriverState);
2110 }
2111
LPSPI4_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2112 static int32_t LPSPI4_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2113 {
2114 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI4_InterruptDriverState);
2115 }
2116
LPSPI4_InterruptGetCount(void)2117 static uint32_t LPSPI4_InterruptGetCount(void)
2118 {
2119 return LPSPI_InterruptGetCount(&LPSPI4_InterruptDriverState);
2120 }
2121
LPSPI4_InterruptControl(uint32_t control,uint32_t arg)2122 static int32_t LPSPI4_InterruptControl(uint32_t control, uint32_t arg)
2123 {
2124 return LPSPI_InterruptControl(control, arg, &LPSPI4_InterruptDriverState);
2125 }
2126
LPSPI4_InterruptGetStatus(void)2127 static ARM_SPI_STATUS LPSPI4_InterruptGetStatus(void)
2128 {
2129 return LPSPI_InterruptGetStatus(&LPSPI4_InterruptDriverState);
2130 }
2131
2132 #endif
2133
2134 ARM_DRIVER_SPI Driver_SPI4 = {
2135 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
2136 #if defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN
2137 LPSPI4_EdmaInitialize, LPSPI4_EdmaUninitialize, LPSPI4_EdmaPowerControl, LPSPI4_EdmaSend, LPSPI4_EdmaReceive,
2138 LPSPI4_EdmaTransfer, LPSPI4_EdmaGetCount, LPSPI4_EdmaControl, LPSPI4_EdmaGetStatus
2139 #else
2140 LPSPI4_InterruptInitialize, LPSPI4_InterruptUninitialize, LPSPI4_InterruptPowerControl, LPSPI4_InterruptSend,
2141 LPSPI4_InterruptReceive, LPSPI4_InterruptTransfer, LPSPI4_InterruptGetCount, LPSPI4_InterruptControl,
2142 LPSPI4_InterruptGetStatus
2143 #endif
2144 };
2145
2146 #endif /* LPSPI4 */
2147
2148 #if defined(LPSPI5) && defined(RTE_SPI5) && RTE_SPI5
2149
2150 /* User needs to provide the implementation for LPSPI5_GetFreq/InitPins/DeinitPins
2151 in the application for enabling according instance. */
2152 extern uint32_t LPSPI5_GetFreq(void);
2153
2154 static cmsis_lpspi_resource_t LPSPI5_Resource = {LPSPI5, 5, LPSPI5_GetFreq};
2155
2156 #if defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN
2157
2158 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2159 static cmsis_lpspi_edma_resource_t LPSPI5_EdmaResource = {
2160 RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH, (uint16_t)RTE_SPI5_DMA_TX_PERI_SEL,
2161 RTE_SPI5_DMA_RX_DMA_BASE, RTE_SPI5_DMA_RX_CH, (uint16_t)RTE_SPI5_DMA_RX_PERI_SEL,
2162 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2163 RTE_SPI5_DMA_TX_DMAMUX_BASE, RTE_SPI5_DMA_RX_DMAMUX_BASE,
2164 #endif
2165 };
2166
2167 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI5_EdmaHandle);
2168 static edma_handle_t LPSPI5_EdmaTxDataToTxRegHandle;
2169 static edma_handle_t LPSPI5_EdmaRxRegToRxDataHandle;
2170
2171 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2172 ARMCC_SECTION("lpspi5_edma_driver_state")
2173 static cmsis_lpspi_edma_driver_state_t LPSPI5_EdmaDriverState = {
2174 #else
2175 static cmsis_lpspi_edma_driver_state_t LPSPI5_EdmaDriverState = {
2176 #endif
2177 &LPSPI5_Resource,
2178 &LPSPI5_EdmaResource,
2179 &LPSPI5_EdmaHandle,
2180 &LPSPI5_EdmaRxRegToRxDataHandle,
2181 &LPSPI5_EdmaTxDataToTxRegHandle,
2182 };
2183
LPSPI5_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)2184 static int32_t LPSPI5_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
2185 {
2186 #ifdef RTE_SPI5_PIN_INIT
2187 RTE_SPI5_PIN_INIT();
2188 #endif
2189 return LPSPI_EdmaInitialize(cb_event, &LPSPI5_EdmaDriverState);
2190 }
2191
LPSPI5_EdmaUninitialize(void)2192 static int32_t LPSPI5_EdmaUninitialize(void)
2193 {
2194 #ifdef RTE_SPI5_PIN_DEINIT
2195 RTE_SPI5_PIN_DEINIT();
2196 #endif
2197 return LPSPI_EdmaUninitialize(&LPSPI5_EdmaDriverState);
2198 }
2199
LPSPI5_EdmaPowerControl(ARM_POWER_STATE state)2200 static int32_t LPSPI5_EdmaPowerControl(ARM_POWER_STATE state)
2201 {
2202 return LPSPI_EdmaPowerControl(state, &LPSPI5_EdmaDriverState);
2203 }
2204
LPSPI5_EdmaSend(const void * data,uint32_t num)2205 static int32_t LPSPI5_EdmaSend(const void *data, uint32_t num)
2206 {
2207 return LPSPI_EdmaSend(data, num, &LPSPI5_EdmaDriverState);
2208 }
2209
LPSPI5_EdmaReceive(void * data,uint32_t num)2210 static int32_t LPSPI5_EdmaReceive(void *data, uint32_t num)
2211 {
2212 return LPSPI_EdmaReceive(data, num, &LPSPI5_EdmaDriverState);
2213 }
2214
LPSPI5_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2215 static int32_t LPSPI5_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2216 {
2217 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI5_EdmaDriverState);
2218 }
2219
LPSPI5_EdmaGetCount(void)2220 static uint32_t LPSPI5_EdmaGetCount(void)
2221 {
2222 return LPSPI_EdmaGetCount(&LPSPI5_EdmaDriverState);
2223 }
2224
LPSPI5_EdmaControl(uint32_t control,uint32_t arg)2225 static int32_t LPSPI5_EdmaControl(uint32_t control, uint32_t arg)
2226 {
2227 return LPSPI_EdmaControl(control, arg, &LPSPI5_EdmaDriverState);
2228 }
2229
LPSPI5_EdmaGetStatus(void)2230 static ARM_SPI_STATUS LPSPI5_EdmaGetStatus(void)
2231 {
2232 return LPSPI_EdmaGetStatus(&LPSPI5_EdmaDriverState);
2233 }
2234
2235 #endif
2236
2237 #else
2238
2239 static cmsis_lpspi_handle_t LPSPI5_Handle;
2240
2241 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2242 ARMCC_SECTION("lpspi5_interrupt_driver_state")
2243 static cmsis_lpspi_interrupt_driver_state_t LPSPI5_InterruptDriverState = {
2244 #else
2245 static cmsis_lpspi_interrupt_driver_state_t LPSPI5_InterruptDriverState = {
2246 #endif
2247 &LPSPI5_Resource,
2248 &LPSPI5_Handle,
2249 };
2250
LPSPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2251 static int32_t LPSPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2252 {
2253 #ifdef RTE_SPI5_PIN_INIT
2254 RTE_SPI5_PIN_INIT();
2255 #endif
2256 return LPSPI_InterruptInitialize(cb_event, &LPSPI5_InterruptDriverState);
2257 }
2258
LPSPI5_InterruptUninitialize(void)2259 static int32_t LPSPI5_InterruptUninitialize(void)
2260 {
2261 #ifdef RTE_SPI5_PIN_DEINIT
2262 RTE_SPI5_PIN_DEINIT();
2263 #endif
2264 return LPSPI_InterruptUninitialize(&LPSPI5_InterruptDriverState);
2265 }
2266
LPSPI5_InterruptPowerControl(ARM_POWER_STATE state)2267 static int32_t LPSPI5_InterruptPowerControl(ARM_POWER_STATE state)
2268 {
2269 return LPSPI_InterruptPowerControl(state, &LPSPI5_InterruptDriverState);
2270 }
2271
LPSPI5_InterruptSend(const void * data,uint32_t num)2272 static int32_t LPSPI5_InterruptSend(const void *data, uint32_t num)
2273 {
2274 return LPSPI_InterruptSend(data, num, &LPSPI5_InterruptDriverState);
2275 }
2276
LPSPI5_InterruptReceive(void * data,uint32_t num)2277 static int32_t LPSPI5_InterruptReceive(void *data, uint32_t num)
2278 {
2279 return LPSPI_InterruptReceive(data, num, &LPSPI5_InterruptDriverState);
2280 }
2281
LPSPI5_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2282 static int32_t LPSPI5_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2283 {
2284 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI5_InterruptDriverState);
2285 }
2286
LPSPI5_InterruptGetCount(void)2287 static uint32_t LPSPI5_InterruptGetCount(void)
2288 {
2289 return LPSPI_InterruptGetCount(&LPSPI5_InterruptDriverState);
2290 }
2291
LPSPI5_InterruptControl(uint32_t control,uint32_t arg)2292 static int32_t LPSPI5_InterruptControl(uint32_t control, uint32_t arg)
2293 {
2294 return LPSPI_InterruptControl(control, arg, &LPSPI5_InterruptDriverState);
2295 }
2296
LPSPI5_InterruptGetStatus(void)2297 static ARM_SPI_STATUS LPSPI5_InterruptGetStatus(void)
2298 {
2299 return LPSPI_InterruptGetStatus(&LPSPI5_InterruptDriverState);
2300 }
2301
2302 #endif
2303
2304 ARM_DRIVER_SPI Driver_SPI5 = {
2305 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
2306 #if defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN
2307 LPSPI5_EdmaInitialize, LPSPI5_EdmaUninitialize, LPSPI5_EdmaPowerControl, LPSPI5_EdmaSend, LPSPI5_EdmaReceive,
2308 LPSPI5_EdmaTransfer, LPSPI5_EdmaGetCount, LPSPI5_EdmaControl, LPSPI5_EdmaGetStatus
2309 #else
2310 LPSPI5_InterruptInitialize, LPSPI5_InterruptUninitialize, LPSPI5_InterruptPowerControl, LPSPI5_InterruptSend,
2311 LPSPI5_InterruptReceive, LPSPI5_InterruptTransfer, LPSPI5_InterruptGetCount, LPSPI5_InterruptControl,
2312 LPSPI5_InterruptGetStatus
2313 #endif
2314 };
2315
2316 #endif /* LPSPI5 */
2317
2318 #if defined(LPSPI6) && defined(RTE_SPI6) && RTE_SPI6
2319
2320 /* User needs to provide the implementation for LPSPI6_GetFreq/InitPins/DeinitPins
2321 in the application for enabling according instance. */
2322 extern uint32_t LPSPI6_GetFreq(void);
2323
2324 static cmsis_lpspi_resource_t LPSPI6_Resource = {LPSPI6, 6, LPSPI6_GetFreq};
2325
2326 #if defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN
2327
2328 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2329 static cmsis_lpspi_edma_resource_t LPSPI6_EdmaResource = {
2330 RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH, (uint16_t)RTE_SPI6_DMA_TX_PERI_SEL,
2331 RTE_SPI6_DMA_RX_DMA_BASE, RTE_SPI6_DMA_RX_CH, (uint16_t)RTE_SPI6_DMA_RX_PERI_SEL,
2332 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2333 RTE_SPI6_DMA_TX_DMAMUX_BASE, RTE_SPI6_DMA_RX_DMAMUX_BASE,
2334 #endif
2335 };
2336
2337 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI6_EdmaHandle);
2338 static edma_handle_t LPSPI6_EdmaTxDataToTxRegHandle;
2339 static edma_handle_t LPSPI6_EdmaRxRegToRxDataHandle;
2340
2341 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2342 ARMCC_SECTION("lpspi6_edma_driver_state")
2343 static cmsis_lpspi_edma_driver_state_t LPSPI6_EdmaDriverState = {
2344 #else
2345 static cmsis_lpspi_edma_driver_state_t LPSPI6_EdmaDriverState = {
2346 #endif
2347 &LPSPI6_Resource,
2348 &LPSPI6_EdmaResource,
2349 &LPSPI6_EdmaHandle,
2350 &LPSPI6_EdmaRxRegToRxDataHandle,
2351 &LPSPI6_EdmaTxDataToTxRegHandle,
2352 };
2353
LPSPI6_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)2354 static int32_t LPSPI6_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
2355 {
2356 #ifdef RTE_SPI6_PIN_INIT
2357 RTE_SPI6_PIN_INIT();
2358 #endif
2359 return LPSPI_EdmaInitialize(cb_event, &LPSPI6_EdmaDriverState);
2360 }
2361
LPSPI6_EdmaUninitialize(void)2362 static int32_t LPSPI6_EdmaUninitialize(void)
2363 {
2364 #ifdef RTE_SPI6_PIN_DEINIT
2365 RTE_SPI6_PIN_DEINIT();
2366 #endif
2367 return LPSPI_EdmaUninitialize(&LPSPI6_EdmaDriverState);
2368 }
2369
LPSPI6_EdmaPowerControl(ARM_POWER_STATE state)2370 static int32_t LPSPI6_EdmaPowerControl(ARM_POWER_STATE state)
2371 {
2372 return LPSPI_EdmaPowerControl(state, &LPSPI6_EdmaDriverState);
2373 }
2374
LPSPI6_EdmaSend(const void * data,uint32_t num)2375 static int32_t LPSPI6_EdmaSend(const void *data, uint32_t num)
2376 {
2377 return LPSPI_EdmaSend(data, num, &LPSPI6_EdmaDriverState);
2378 }
2379
LPSPI6_EdmaReceive(void * data,uint32_t num)2380 static int32_t LPSPI6_EdmaReceive(void *data, uint32_t num)
2381 {
2382 return LPSPI_EdmaReceive(data, num, &LPSPI6_EdmaDriverState);
2383 }
2384
LPSPI6_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2385 static int32_t LPSPI6_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2386 {
2387 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI6_EdmaDriverState);
2388 }
2389
LPSPI6_EdmaGetCount(void)2390 static uint32_t LPSPI6_EdmaGetCount(void)
2391 {
2392 return LPSPI_EdmaGetCount(&LPSPI6_EdmaDriverState);
2393 }
2394
LPSPI6_EdmaControl(uint32_t control,uint32_t arg)2395 static int32_t LPSPI6_EdmaControl(uint32_t control, uint32_t arg)
2396 {
2397 return LPSPI_EdmaControl(control, arg, &LPSPI6_EdmaDriverState);
2398 }
2399
LPSPI6_EdmaGetStatus(void)2400 static ARM_SPI_STATUS LPSPI6_EdmaGetStatus(void)
2401 {
2402 return LPSPI_EdmaGetStatus(&LPSPI6_EdmaDriverState);
2403 }
2404
2405 #endif
2406
2407 #else
2408
2409 static cmsis_lpspi_handle_t LPSPI6_Handle;
2410
2411 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2412 ARMCC_SECTION("lpspi6_interrupt_driver_state")
2413 static cmsis_lpspi_interrupt_driver_state_t LPSPI6_InterruptDriverState = {
2414 #else
2415 static cmsis_lpspi_interrupt_driver_state_t LPSPI6_InterruptDriverState = {
2416 #endif
2417 &LPSPI6_Resource,
2418 &LPSPI6_Handle,
2419 };
2420
LPSPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2421 static int32_t LPSPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2422 {
2423 #ifdef RTE_SPI6_PIN_INIT
2424 RTE_SPI6_PIN_INIT();
2425 #endif
2426 return LPSPI_InterruptInitialize(cb_event, &LPSPI6_InterruptDriverState);
2427 }
2428
LPSPI6_InterruptUninitialize(void)2429 static int32_t LPSPI6_InterruptUninitialize(void)
2430 {
2431 #ifdef RTE_SPI6_PIN_DEINIT
2432 RTE_SPI6_PIN_DEINIT();
2433 #endif
2434 return LPSPI_InterruptUninitialize(&LPSPI6_InterruptDriverState);
2435 }
2436
LPSPI6_InterruptPowerControl(ARM_POWER_STATE state)2437 static int32_t LPSPI6_InterruptPowerControl(ARM_POWER_STATE state)
2438 {
2439 return LPSPI_InterruptPowerControl(state, &LPSPI6_InterruptDriverState);
2440 }
2441
LPSPI6_InterruptSend(const void * data,uint32_t num)2442 static int32_t LPSPI6_InterruptSend(const void *data, uint32_t num)
2443 {
2444 return LPSPI_InterruptSend(data, num, &LPSPI6_InterruptDriverState);
2445 }
2446
LPSPI6_InterruptReceive(void * data,uint32_t num)2447 static int32_t LPSPI6_InterruptReceive(void *data, uint32_t num)
2448 {
2449 return LPSPI_InterruptReceive(data, num, &LPSPI6_InterruptDriverState);
2450 }
2451
LPSPI6_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2452 static int32_t LPSPI6_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2453 {
2454 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI6_InterruptDriverState);
2455 }
2456
LPSPI6_InterruptGetCount(void)2457 static uint32_t LPSPI6_InterruptGetCount(void)
2458 {
2459 return LPSPI_InterruptGetCount(&LPSPI6_InterruptDriverState);
2460 }
2461
LPSPI6_InterruptControl(uint32_t control,uint32_t arg)2462 static int32_t LPSPI6_InterruptControl(uint32_t control, uint32_t arg)
2463 {
2464 return LPSPI_InterruptControl(control, arg, &LPSPI6_InterruptDriverState);
2465 }
2466
LPSPI6_InterruptGetStatus(void)2467 static ARM_SPI_STATUS LPSPI6_InterruptGetStatus(void)
2468 {
2469 return LPSPI_InterruptGetStatus(&LPSPI6_InterruptDriverState);
2470 }
2471
2472 #endif
2473
2474 ARM_DRIVER_SPI Driver_SPI6 = {
2475 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
2476 #if defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN
2477 LPSPI6_EdmaInitialize, LPSPI6_EdmaUninitialize, LPSPI6_EdmaPowerControl, LPSPI6_EdmaSend, LPSPI6_EdmaReceive,
2478 LPSPI6_EdmaTransfer, LPSPI6_EdmaGetCount, LPSPI6_EdmaControl, LPSPI6_EdmaGetStatus
2479 #else
2480 LPSPI6_InterruptInitialize, LPSPI6_InterruptUninitialize, LPSPI6_InterruptPowerControl, LPSPI6_InterruptSend,
2481 LPSPI6_InterruptReceive, LPSPI6_InterruptTransfer, LPSPI6_InterruptGetCount, LPSPI6_InterruptControl,
2482 LPSPI6_InterruptGetStatus
2483 #endif
2484 };
2485
2486 #endif /* LPSPI6 */
2487
2488 #if defined(LPSPI7) && defined(RTE_SPI7) && RTE_SPI7
2489
2490 /* User needs to provide the implementation for LPSPI7_GetFreq/InitPins/DeinitPins
2491 in the application for enabling according instance. */
2492 extern uint32_t LPSPI7_GetFreq(void);
2493
2494 static cmsis_lpspi_resource_t LPSPI7_Resource = {LPSPI7, 7, LPSPI7_GetFreq};
2495
2496 #if defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN
2497
2498 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2499 static cmsis_lpspi_edma_resource_t LPSPI7_EdmaResource = {
2500 RTE_SPI7_DMA_TX_DMA_BASE, RTE_SPI7_DMA_TX_CH, (uint16_t)RTE_SPI7_DMA_TX_PERI_SEL,
2501 RTE_SPI7_DMA_RX_DMA_BASE, RTE_SPI7_DMA_RX_CH, (uint16_t)RTE_SPI7_DMA_RX_PERI_SEL,
2502 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2503 RTE_SPI7_DMA_TX_DMAMUX_BASE, RTE_SPI7_DMA_RX_DMAMUX_BASE,
2504 #endif
2505 };
2506
2507 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI7_EdmaHandle);
2508 static edma_handle_t LPSPI7_EdmaTxDataToTxRegHandle;
2509 static edma_handle_t LPSPI7_EdmaRxRegToRxDataHandle;
2510
2511 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2512 ARMCC_SECTION("lpspi7_edma_driver_state")
2513 static cmsis_lpspi_edma_driver_state_t LPSPI7_EdmaDriverState = {
2514 #else
2515 static cmsis_lpspi_edma_driver_state_t LPSPI7_EdmaDriverState = {
2516 #endif
2517 &LPSPI7_Resource,
2518 &LPSPI7_EdmaResource,
2519 &LPSPI7_EdmaHandle,
2520 &LPSPI7_EdmaRxRegToRxDataHandle,
2521 &LPSPI7_EdmaTxDataToTxRegHandle,
2522 };
2523
LPSPI7_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)2524 static int32_t LPSPI7_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
2525 {
2526 #ifdef RTE_SPI7_PIN_INIT
2527 RTE_SPI7_PIN_INIT();
2528 #endif
2529 return LPSPI_EdmaInitialize(cb_event, &LPSPI7_EdmaDriverState);
2530 }
2531
LPSPI7_EdmaUninitialize(void)2532 static int32_t LPSPI7_EdmaUninitialize(void)
2533 {
2534 #ifdef RTE_SPI7_PIN_DEINIT
2535 RTE_SPI7_PIN_DEINIT();
2536 #endif
2537 return LPSPI_EdmaUninitialize(&LPSPI7_EdmaDriverState);
2538 }
2539
LPSPI7_EdmaPowerControl(ARM_POWER_STATE state)2540 static int32_t LPSPI7_EdmaPowerControl(ARM_POWER_STATE state)
2541 {
2542 return LPSPI_EdmaPowerControl(state, &LPSPI7_EdmaDriverState);
2543 }
2544
LPSPI7_EdmaSend(const void * data,uint32_t num)2545 static int32_t LPSPI7_EdmaSend(const void *data, uint32_t num)
2546 {
2547 return LPSPI_EdmaSend(data, num, &LPSPI7_EdmaDriverState);
2548 }
2549
LPSPI7_EdmaReceive(void * data,uint32_t num)2550 static int32_t LPSPI7_EdmaReceive(void *data, uint32_t num)
2551 {
2552 return LPSPI_EdmaReceive(data, num, &LPSPI7_EdmaDriverState);
2553 }
2554
LPSPI7_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2555 static int32_t LPSPI7_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2556 {
2557 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI7_EdmaDriverState);
2558 }
2559
LPSPI7_EdmaGetCount(void)2560 static uint32_t LPSPI7_EdmaGetCount(void)
2561 {
2562 return LPSPI_EdmaGetCount(&LPSPI7_EdmaDriverState);
2563 }
2564
LPSPI7_EdmaControl(uint32_t control,uint32_t arg)2565 static int32_t LPSPI7_EdmaControl(uint32_t control, uint32_t arg)
2566 {
2567 return LPSPI_EdmaControl(control, arg, &LPSPI7_EdmaDriverState);
2568 }
2569
LPSPI7_EdmaGetStatus(void)2570 static ARM_SPI_STATUS LPSPI7_EdmaGetStatus(void)
2571 {
2572 return LPSPI_EdmaGetStatus(&LPSPI7_EdmaDriverState);
2573 }
2574
2575 #endif
2576
2577 #else
2578
2579 static cmsis_lpspi_handle_t LPSPI7_Handle;
2580
2581 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2582 ARMCC_SECTION("lpspi7_interrupt_driver_state")
2583 static cmsis_lpspi_interrupt_driver_state_t LPSPI7_InterruptDriverState = {
2584 #else
2585 static cmsis_lpspi_interrupt_driver_state_t LPSPI7_InterruptDriverState = {
2586 #endif
2587 &LPSPI7_Resource,
2588 &LPSPI7_Handle,
2589 };
2590
LPSPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2591 static int32_t LPSPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2592 {
2593 #ifdef RTE_SPI7_PIN_INIT
2594 RTE_SPI7_PIN_INIT();
2595 #endif
2596 return LPSPI_InterruptInitialize(cb_event, &LPSPI7_InterruptDriverState);
2597 }
2598
LPSPI7_InterruptUninitialize(void)2599 static int32_t LPSPI7_InterruptUninitialize(void)
2600 {
2601 #ifdef RTE_SPI7_PIN_DEINIT
2602 RTE_SPI7_PIN_DEINIT();
2603 #endif
2604 return LPSPI_InterruptUninitialize(&LPSPI7_InterruptDriverState);
2605 }
2606
LPSPI7_InterruptPowerControl(ARM_POWER_STATE state)2607 static int32_t LPSPI7_InterruptPowerControl(ARM_POWER_STATE state)
2608 {
2609 return LPSPI_InterruptPowerControl(state, &LPSPI7_InterruptDriverState);
2610 }
2611
LPSPI7_InterruptSend(const void * data,uint32_t num)2612 static int32_t LPSPI7_InterruptSend(const void *data, uint32_t num)
2613 {
2614 return LPSPI_InterruptSend(data, num, &LPSPI7_InterruptDriverState);
2615 }
2616
LPSPI7_InterruptReceive(void * data,uint32_t num)2617 static int32_t LPSPI7_InterruptReceive(void *data, uint32_t num)
2618 {
2619 return LPSPI_InterruptReceive(data, num, &LPSPI7_InterruptDriverState);
2620 }
2621
LPSPI7_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2622 static int32_t LPSPI7_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2623 {
2624 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI7_InterruptDriverState);
2625 }
2626
LPSPI7_InterruptGetCount(void)2627 static uint32_t LPSPI7_InterruptGetCount(void)
2628 {
2629 return LPSPI_InterruptGetCount(&LPSPI7_InterruptDriverState);
2630 }
2631
LPSPI7_InterruptControl(uint32_t control,uint32_t arg)2632 static int32_t LPSPI7_InterruptControl(uint32_t control, uint32_t arg)
2633 {
2634 return LPSPI_InterruptControl(control, arg, &LPSPI7_InterruptDriverState);
2635 }
2636
LPSPI7_InterruptGetStatus(void)2637 static ARM_SPI_STATUS LPSPI7_InterruptGetStatus(void)
2638 {
2639 return LPSPI_InterruptGetStatus(&LPSPI7_InterruptDriverState);
2640 }
2641
2642 #endif
2643
2644 ARM_DRIVER_SPI Driver_SPI7 = {
2645 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
2646 #if defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN
2647 LPSPI7_EdmaInitialize, LPSPI7_EdmaUninitialize, LPSPI7_EdmaPowerControl, LPSPI7_EdmaSend, LPSPI7_EdmaReceive,
2648 LPSPI7_EdmaTransfer, LPSPI7_EdmaGetCount, LPSPI7_EdmaControl, LPSPI7_EdmaGetStatus
2649 #else
2650 LPSPI7_InterruptInitialize, LPSPI7_InterruptUninitialize, LPSPI7_InterruptPowerControl, LPSPI7_InterruptSend,
2651 LPSPI7_InterruptReceive, LPSPI7_InterruptTransfer, LPSPI7_InterruptGetCount, LPSPI7_InterruptControl,
2652 LPSPI7_InterruptGetStatus
2653 #endif
2654 };
2655
2656 #endif /* LPSPI7 */
2657
2658 #if defined(LPSPI8) && defined(RTE_SPI8) && RTE_SPI8
2659
2660 /* User needs to provide the implementation for LPSPI8_GetFreq/InitPins/DeinitPins
2661 in the application for enabling according instance. */
2662 extern uint32_t LPSPI8_GetFreq(void);
2663
2664 static cmsis_lpspi_resource_t LPSPI8_Resource = {LPSPI8, 8, LPSPI8_GetFreq};
2665
2666 #if defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN
2667
2668 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2669 static cmsis_lpspi_edma_resource_t LPSPI8_EdmaResource = {
2670 RTE_SPI8_DMA_TX_DMA_BASE, RTE_SPI8_DMA_TX_CH, (uint16_t)RTE_SPI8_DMA_TX_PERI_SEL,
2671 RTE_SPI8_DMA_RX_DMA_BASE, RTE_SPI8_DMA_RX_CH, (uint16_t)RTE_SPI8_DMA_RX_PERI_SEL,
2672 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2673 RTE_SPI8_DMA_TX_DMAMUX_BASE, RTE_SPI8_DMA_RX_DMAMUX_BASE,
2674 #endif
2675 };
2676
2677 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI8_EdmaHandle);
2678 static edma_handle_t LPSPI8_EdmaTxDataToTxRegHandle;
2679 static edma_handle_t LPSPI8_EdmaRxRegToRxDataHandle;
2680
2681 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2682 ARMCC_SECTION("lpspi8_edma_driver_state")
2683 static cmsis_lpspi_edma_driver_state_t LPSPI8_EdmaDriverState = {
2684 #else
2685 static cmsis_lpspi_edma_driver_state_t LPSPI8_EdmaDriverState = {
2686 #endif
2687 &LPSPI8_Resource,
2688 &LPSPI8_EdmaResource,
2689 &LPSPI8_EdmaHandle,
2690 &LPSPI8_EdmaRxRegToRxDataHandle,
2691 &LPSPI8_EdmaTxDataToTxRegHandle,
2692 };
2693
LPSPI8_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)2694 static int32_t LPSPI8_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
2695 {
2696 #ifdef RTE_SPI8_PIN_INIT
2697 RTE_SPI8_PIN_INIT();
2698 #endif
2699 return LPSPI_EdmaInitialize(cb_event, &LPSPI8_EdmaDriverState);
2700 }
2701
LPSPI8_EdmaUninitialize(void)2702 static int32_t LPSPI8_EdmaUninitialize(void)
2703 {
2704 #ifdef RTE_SPI8_PIN_DEINIT
2705 RTE_SPI8_PIN_DEINIT();
2706 #endif
2707 return LPSPI_EdmaUninitialize(&LPSPI8_EdmaDriverState);
2708 }
2709
LPSPI8_EdmaPowerControl(ARM_POWER_STATE state)2710 static int32_t LPSPI8_EdmaPowerControl(ARM_POWER_STATE state)
2711 {
2712 return LPSPI_EdmaPowerControl(state, &LPSPI8_EdmaDriverState);
2713 }
2714
LPSPI8_EdmaSend(const void * data,uint32_t num)2715 static int32_t LPSPI8_EdmaSend(const void *data, uint32_t num)
2716 {
2717 return LPSPI_EdmaSend(data, num, &LPSPI8_EdmaDriverState);
2718 }
2719
LPSPI8_EdmaReceive(void * data,uint32_t num)2720 static int32_t LPSPI8_EdmaReceive(void *data, uint32_t num)
2721 {
2722 return LPSPI_EdmaReceive(data, num, &LPSPI8_EdmaDriverState);
2723 }
2724
LPSPI8_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2725 static int32_t LPSPI8_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2726 {
2727 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI8_EdmaDriverState);
2728 }
2729
LPSPI8_EdmaGetCount(void)2730 static uint32_t LPSPI8_EdmaGetCount(void)
2731 {
2732 return LPSPI_EdmaGetCount(&LPSPI8_EdmaDriverState);
2733 }
2734
LPSPI8_EdmaControl(uint32_t control,uint32_t arg)2735 static int32_t LPSPI8_EdmaControl(uint32_t control, uint32_t arg)
2736 {
2737 return LPSPI_EdmaControl(control, arg, &LPSPI8_EdmaDriverState);
2738 }
2739
LPSPI8_EdmaGetStatus(void)2740 static ARM_SPI_STATUS LPSPI8_EdmaGetStatus(void)
2741 {
2742 return LPSPI_EdmaGetStatus(&LPSPI8_EdmaDriverState);
2743 }
2744
2745 #endif
2746
2747 #else
2748
2749 static cmsis_lpspi_handle_t LPSPI8_Handle;
2750
2751 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2752 ARMCC_SECTION("lpspi8_interrupt_driver_state")
2753 static cmsis_lpspi_interrupt_driver_state_t LPSPI8_InterruptDriverState = {
2754 #else
2755 static cmsis_lpspi_interrupt_driver_state_t LPSPI8_InterruptDriverState = {
2756 #endif
2757 &LPSPI8_Resource,
2758 &LPSPI8_Handle,
2759 };
2760
LPSPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2761 static int32_t LPSPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2762 {
2763 #ifdef RTE_SPI8_PIN_INIT
2764 RTE_SPI8_PIN_INIT();
2765 #endif
2766 return LPSPI_InterruptInitialize(cb_event, &LPSPI8_InterruptDriverState);
2767 }
2768
LPSPI8_InterruptUninitialize(void)2769 static int32_t LPSPI8_InterruptUninitialize(void)
2770 {
2771 #ifdef RTE_SPI8_PIN_DEINIT
2772 RTE_SPI8_PIN_DEINIT();
2773 #endif
2774 return LPSPI_InterruptUninitialize(&LPSPI8_InterruptDriverState);
2775 }
2776
LPSPI8_InterruptPowerControl(ARM_POWER_STATE state)2777 static int32_t LPSPI8_InterruptPowerControl(ARM_POWER_STATE state)
2778 {
2779 return LPSPI_InterruptPowerControl(state, &LPSPI8_InterruptDriverState);
2780 }
2781
LPSPI8_InterruptSend(const void * data,uint32_t num)2782 static int32_t LPSPI8_InterruptSend(const void *data, uint32_t num)
2783 {
2784 return LPSPI_InterruptSend(data, num, &LPSPI8_InterruptDriverState);
2785 }
2786
LPSPI8_InterruptReceive(void * data,uint32_t num)2787 static int32_t LPSPI8_InterruptReceive(void *data, uint32_t num)
2788 {
2789 return LPSPI_InterruptReceive(data, num, &LPSPI8_InterruptDriverState);
2790 }
2791
LPSPI8_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2792 static int32_t LPSPI8_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2793 {
2794 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI8_InterruptDriverState);
2795 }
2796
LPSPI8_InterruptGetCount(void)2797 static uint32_t LPSPI8_InterruptGetCount(void)
2798 {
2799 return LPSPI_InterruptGetCount(&LPSPI8_InterruptDriverState);
2800 }
2801
LPSPI8_InterruptControl(uint32_t control,uint32_t arg)2802 static int32_t LPSPI8_InterruptControl(uint32_t control, uint32_t arg)
2803 {
2804 return LPSPI_InterruptControl(control, arg, &LPSPI8_InterruptDriverState);
2805 }
2806
LPSPI8_InterruptGetStatus(void)2807 static ARM_SPI_STATUS LPSPI8_InterruptGetStatus(void)
2808 {
2809 return LPSPI_InterruptGetStatus(&LPSPI8_InterruptDriverState);
2810 }
2811
2812 #endif
2813
2814 ARM_DRIVER_SPI Driver_SPI8 = {
2815 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
2816 #if defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN
2817 LPSPI8_EdmaInitialize, LPSPI8_EdmaUninitialize, LPSPI8_EdmaPowerControl, LPSPI8_EdmaSend, LPSPI8_EdmaReceive,
2818 LPSPI8_EdmaTransfer, LPSPI8_EdmaGetCount, LPSPI8_EdmaControl, LPSPI8_EdmaGetStatus
2819 #else
2820 LPSPI8_InterruptInitialize, LPSPI8_InterruptUninitialize, LPSPI8_InterruptPowerControl, LPSPI8_InterruptSend,
2821 LPSPI8_InterruptReceive, LPSPI8_InterruptTransfer, LPSPI8_InterruptGetCount, LPSPI8_InterruptControl,
2822 LPSPI8_InterruptGetStatus
2823 #endif
2824 };
2825
2826 #endif /* LPSPI8 */
2827
2828 #if defined(LPSPI9) && defined(RTE_SPI9) && RTE_SPI9
2829
2830 /* User needs to provide the implementation for LPSPI9_GetFreq/InitPins/DeinitPins
2831 in the application for enabling according instance. */
2832 extern uint32_t LPSPI9_GetFreq(void);
2833
2834 static cmsis_lpspi_resource_t LPSPI9_Resource = {LPSPI9, 9, LPSPI9_GetFreq};
2835
2836 #if defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN
2837
2838 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
2839 static cmsis_lpspi_edma_resource_t LPSPI9_EdmaResource = {
2840 RTE_SPI9_DMA_TX_DMA_BASE, RTE_SPI9_DMA_TX_CH, (uint16_t)RTE_SPI9_DMA_TX_PERI_SEL,
2841 RTE_SPI9_DMA_RX_DMA_BASE, RTE_SPI9_DMA_RX_CH, (uint16_t)RTE_SPI9_DMA_RX_PERI_SEL,
2842 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
2843 RTE_SPI9_DMA_TX_DMAMUX_BASE, RTE_SPI9_DMA_RX_DMAMUX_BASE,
2844 #endif
2845 };
2846
2847 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI9_EdmaHandle);
2848 static edma_handle_t LPSPI9_EdmaTxDataToTxRegHandle;
2849 static edma_handle_t LPSPI9_EdmaRxRegToRxDataHandle;
2850
2851 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2852 ARMCC_SECTION("lpspi9_edma_driver_state")
2853 static cmsis_lpspi_edma_driver_state_t LPSPI9_EdmaDriverState = {
2854 #else
2855 static cmsis_lpspi_edma_driver_state_t LPSPI9_EdmaDriverState = {
2856 #endif
2857 &LPSPI9_Resource,
2858 &LPSPI9_EdmaResource,
2859 &LPSPI9_EdmaHandle,
2860 &LPSPI9_EdmaRxRegToRxDataHandle,
2861 &LPSPI9_EdmaTxDataToTxRegHandle,
2862 };
2863
LPSPI9_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)2864 static int32_t LPSPI9_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
2865 {
2866 #ifdef RTE_SPI9_PIN_INIT
2867 RTE_SPI9_PIN_INIT();
2868 #endif
2869 return LPSPI_EdmaInitialize(cb_event, &LPSPI9_EdmaDriverState);
2870 }
2871
LPSPI9_EdmaUninitialize(void)2872 static int32_t LPSPI9_EdmaUninitialize(void)
2873 {
2874 #ifdef RTE_SPI9_PIN_DEINIT
2875 RTE_SPI9_PIN_DEINIT();
2876 #endif
2877 return LPSPI_EdmaUninitialize(&LPSPI9_EdmaDriverState);
2878 }
2879
LPSPI9_EdmaPowerControl(ARM_POWER_STATE state)2880 static int32_t LPSPI9_EdmaPowerControl(ARM_POWER_STATE state)
2881 {
2882 return LPSPI_EdmaPowerControl(state, &LPSPI9_EdmaDriverState);
2883 }
2884
LPSPI9_EdmaSend(const void * data,uint32_t num)2885 static int32_t LPSPI9_EdmaSend(const void *data, uint32_t num)
2886 {
2887 return LPSPI_EdmaSend(data, num, &LPSPI9_EdmaDriverState);
2888 }
2889
LPSPI9_EdmaReceive(void * data,uint32_t num)2890 static int32_t LPSPI9_EdmaReceive(void *data, uint32_t num)
2891 {
2892 return LPSPI_EdmaReceive(data, num, &LPSPI9_EdmaDriverState);
2893 }
2894
LPSPI9_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)2895 static int32_t LPSPI9_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
2896 {
2897 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI9_EdmaDriverState);
2898 }
2899
LPSPI9_EdmaGetCount(void)2900 static uint32_t LPSPI9_EdmaGetCount(void)
2901 {
2902 return LPSPI_EdmaGetCount(&LPSPI9_EdmaDriverState);
2903 }
2904
LPSPI9_EdmaControl(uint32_t control,uint32_t arg)2905 static int32_t LPSPI9_EdmaControl(uint32_t control, uint32_t arg)
2906 {
2907 return LPSPI_EdmaControl(control, arg, &LPSPI9_EdmaDriverState);
2908 }
2909
LPSPI9_EdmaGetStatus(void)2910 static ARM_SPI_STATUS LPSPI9_EdmaGetStatus(void)
2911 {
2912 return LPSPI_EdmaGetStatus(&LPSPI9_EdmaDriverState);
2913 }
2914
2915 #endif
2916
2917 #else
2918
2919 static cmsis_lpspi_handle_t LPSPI9_Handle;
2920
2921 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2922 ARMCC_SECTION("lpspi9_interrupt_driver_state")
2923 static cmsis_lpspi_interrupt_driver_state_t LPSPI9_InterruptDriverState = {
2924 #else
2925 static cmsis_lpspi_interrupt_driver_state_t LPSPI9_InterruptDriverState = {
2926 #endif
2927 &LPSPI9_Resource,
2928 &LPSPI9_Handle,
2929 };
2930
LPSPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2931 static int32_t LPSPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2932 {
2933 #ifdef RTE_SPI9_PIN_INIT
2934 RTE_SPI9_PIN_INIT();
2935 #endif
2936 return LPSPI_InterruptInitialize(cb_event, &LPSPI9_InterruptDriverState);
2937 }
2938
LPSPI9_InterruptUninitialize(void)2939 static int32_t LPSPI9_InterruptUninitialize(void)
2940 {
2941 #ifdef RTE_SPI9_PIN_DEINIT
2942 RTE_SPI9_PIN_DEINIT();
2943 #endif
2944 return LPSPI_InterruptUninitialize(&LPSPI9_InterruptDriverState);
2945 }
2946
LPSPI9_InterruptPowerControl(ARM_POWER_STATE state)2947 static int32_t LPSPI9_InterruptPowerControl(ARM_POWER_STATE state)
2948 {
2949 return LPSPI_InterruptPowerControl(state, &LPSPI9_InterruptDriverState);
2950 }
2951
LPSPI9_InterruptSend(const void * data,uint32_t num)2952 static int32_t LPSPI9_InterruptSend(const void *data, uint32_t num)
2953 {
2954 return LPSPI_InterruptSend(data, num, &LPSPI9_InterruptDriverState);
2955 }
2956
LPSPI9_InterruptReceive(void * data,uint32_t num)2957 static int32_t LPSPI9_InterruptReceive(void *data, uint32_t num)
2958 {
2959 return LPSPI_InterruptReceive(data, num, &LPSPI9_InterruptDriverState);
2960 }
2961
LPSPI9_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2962 static int32_t LPSPI9_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2963 {
2964 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI9_InterruptDriverState);
2965 }
2966
LPSPI9_InterruptGetCount(void)2967 static uint32_t LPSPI9_InterruptGetCount(void)
2968 {
2969 return LPSPI_InterruptGetCount(&LPSPI9_InterruptDriverState);
2970 }
2971
LPSPI9_InterruptControl(uint32_t control,uint32_t arg)2972 static int32_t LPSPI9_InterruptControl(uint32_t control, uint32_t arg)
2973 {
2974 return LPSPI_InterruptControl(control, arg, &LPSPI9_InterruptDriverState);
2975 }
2976
LPSPI9_InterruptGetStatus(void)2977 static ARM_SPI_STATUS LPSPI9_InterruptGetStatus(void)
2978 {
2979 return LPSPI_InterruptGetStatus(&LPSPI9_InterruptDriverState);
2980 }
2981
2982 #endif
2983
2984 ARM_DRIVER_SPI Driver_SPI9 = {
2985 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
2986 #if defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN
2987 LPSPI9_EdmaInitialize, LPSPI9_EdmaUninitialize, LPSPI9_EdmaPowerControl, LPSPI9_EdmaSend, LPSPI9_EdmaReceive,
2988 LPSPI9_EdmaTransfer, LPSPI9_EdmaGetCount, LPSPI9_EdmaControl, LPSPI9_EdmaGetStatus
2989 #else
2990 LPSPI9_InterruptInitialize, LPSPI9_InterruptUninitialize, LPSPI9_InterruptPowerControl, LPSPI9_InterruptSend,
2991 LPSPI9_InterruptReceive, LPSPI9_InterruptTransfer, LPSPI9_InterruptGetCount, LPSPI9_InterruptControl,
2992 LPSPI9_InterruptGetStatus
2993 #endif
2994 };
2995
2996 #endif /* LPSPI9 */
2997
2998 #if defined(LPSPI10) && defined(RTE_SPI10) && RTE_SPI10
2999
3000 /* User needs to provide the implementation for LPSPI10_GetFreq/InitPins/DeinitPins
3001 in the application for enabling according instance. */
3002 extern uint32_t LPSPI10_GetFreq(void);
3003
3004 static cmsis_lpspi_resource_t LPSPI10_Resource = {LPSPI10, 10, LPSPI10_GetFreq};
3005
3006 #if defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN
3007
3008 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3009 static cmsis_lpspi_edma_resource_t LPSPI10_EdmaResource = {
3010 RTE_SPI10_DMA_TX_DMA_BASE, RTE_SPI10_DMA_TX_CH, (uint16_t)RTE_SPI10_DMA_TX_PERI_SEL,
3011 RTE_SPI10_DMA_RX_DMA_BASE, RTE_SPI10_DMA_RX_CH, (uint16_t)RTE_SPI10_DMA_RX_PERI_SEL,
3012 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3013 RTE_SPI10_DMA_TX_DMAMUX_BASE, RTE_SPI10_DMA_RX_DMAMUX_BASE,
3014 #endif
3015 };
3016
3017 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI10_EdmaHandle);
3018 static edma_handle_t LPSPI10_EdmaTxDataToTxRegHandle;
3019 static edma_handle_t LPSPI10_EdmaRxRegToRxDataHandle;
3020
3021 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3022 ARMCC_SECTION("lpspi10_edma_driver_state")
3023 static cmsis_lpspi_edma_driver_state_t LPSPI10_EdmaDriverState = {
3024 #else
3025 static cmsis_lpspi_edma_driver_state_t LPSPI10_EdmaDriverState = {
3026 #endif
3027 &LPSPI10_Resource,
3028 &LPSPI10_EdmaResource,
3029 &LPSPI10_EdmaHandle,
3030 &LPSPI10_EdmaRxRegToRxDataHandle,
3031 &LPSPI10_EdmaTxDataToTxRegHandle,
3032 };
3033
LPSPI10_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)3034 static int32_t LPSPI10_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
3035 {
3036 #ifdef RTE_SPI10_PIN_INIT
3037 RTE_SPI10_PIN_INIT();
3038 #endif
3039 return LPSPI_EdmaInitialize(cb_event, &LPSPI10_EdmaDriverState);
3040 }
3041
LPSPI10_EdmaUninitialize(void)3042 static int32_t LPSPI10_EdmaUninitialize(void)
3043 {
3044 #ifdef RTE_SPI10_PIN_DEINIT
3045 RTE_SPI10_PIN_DEINIT();
3046 #endif
3047 return LPSPI_EdmaUninitialize(&LPSPI10_EdmaDriverState);
3048 }
3049
LPSPI10_EdmaPowerControl(ARM_POWER_STATE state)3050 static int32_t LPSPI10_EdmaPowerControl(ARM_POWER_STATE state)
3051 {
3052 return LPSPI_EdmaPowerControl(state, &LPSPI10_EdmaDriverState);
3053 }
3054
LPSPI10_EdmaSend(const void * data,uint32_t num)3055 static int32_t LPSPI10_EdmaSend(const void *data, uint32_t num)
3056 {
3057 return LPSPI_EdmaSend(data, num, &LPSPI10_EdmaDriverState);
3058 }
3059
LPSPI10_EdmaReceive(void * data,uint32_t num)3060 static int32_t LPSPI10_EdmaReceive(void *data, uint32_t num)
3061 {
3062 return LPSPI_EdmaReceive(data, num, &LPSPI10_EdmaDriverState);
3063 }
3064
LPSPI10_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3065 static int32_t LPSPI10_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3066 {
3067 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI10_EdmaDriverState);
3068 }
3069
LPSPI10_EdmaGetCount(void)3070 static uint32_t LPSPI10_EdmaGetCount(void)
3071 {
3072 return LPSPI_EdmaGetCount(&LPSPI10_EdmaDriverState);
3073 }
3074
LPSPI10_EdmaControl(uint32_t control,uint32_t arg)3075 static int32_t LPSPI10_EdmaControl(uint32_t control, uint32_t arg)
3076 {
3077 return LPSPI_EdmaControl(control, arg, &LPSPI10_EdmaDriverState);
3078 }
3079
LPSPI10_EdmaGetStatus(void)3080 static ARM_SPI_STATUS LPSPI10_EdmaGetStatus(void)
3081 {
3082 return LPSPI_EdmaGetStatus(&LPSPI10_EdmaDriverState);
3083 }
3084
3085 #endif
3086
3087 #else
3088
3089 static cmsis_lpspi_handle_t LPSPI10_Handle;
3090
3091 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3092 ARMCC_SECTION("lpspi10_interrupt_driver_state")
3093 static cmsis_lpspi_interrupt_driver_state_t LPSPI10_InterruptDriverState = {
3094 #else
3095 static cmsis_lpspi_interrupt_driver_state_t LPSPI10_InterruptDriverState = {
3096 #endif
3097 &LPSPI10_Resource,
3098 &LPSPI10_Handle,
3099 };
3100
LPSPI10_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3101 static int32_t LPSPI10_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3102 {
3103 #ifdef RTE_SPI10_PIN_INIT
3104 RTE_SPI10_PIN_INIT();
3105 #endif
3106 return LPSPI_InterruptInitialize(cb_event, &LPSPI10_InterruptDriverState);
3107 }
3108
LPSPI10_InterruptUninitialize(void)3109 static int32_t LPSPI10_InterruptUninitialize(void)
3110 {
3111 #ifdef RTE_SPI10_PIN_DEINIT
3112 RTE_SPI10_PIN_DEINIT();
3113 #endif
3114 return LPSPI_InterruptUninitialize(&LPSPI10_InterruptDriverState);
3115 }
3116
LPSPI10_InterruptPowerControl(ARM_POWER_STATE state)3117 static int32_t LPSPI10_InterruptPowerControl(ARM_POWER_STATE state)
3118 {
3119 return LPSPI_InterruptPowerControl(state, &LPSPI10_InterruptDriverState);
3120 }
3121
LPSPI10_InterruptSend(const void * data,uint32_t num)3122 static int32_t LPSPI10_InterruptSend(const void *data, uint32_t num)
3123 {
3124 return LPSPI_InterruptSend(data, num, &LPSPI10_InterruptDriverState);
3125 }
3126
LPSPI10_InterruptReceive(void * data,uint32_t num)3127 static int32_t LPSPI10_InterruptReceive(void *data, uint32_t num)
3128 {
3129 return LPSPI_InterruptReceive(data, num, &LPSPI10_InterruptDriverState);
3130 }
3131
LPSPI10_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3132 static int32_t LPSPI10_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3133 {
3134 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI10_InterruptDriverState);
3135 }
3136
LPSPI10_InterruptGetCount(void)3137 static uint32_t LPSPI10_InterruptGetCount(void)
3138 {
3139 return LPSPI_InterruptGetCount(&LPSPI10_InterruptDriverState);
3140 }
3141
LPSPI10_InterruptControl(uint32_t control,uint32_t arg)3142 static int32_t LPSPI10_InterruptControl(uint32_t control, uint32_t arg)
3143 {
3144 return LPSPI_InterruptControl(control, arg, &LPSPI10_InterruptDriverState);
3145 }
3146
LPSPI10_InterruptGetStatus(void)3147 static ARM_SPI_STATUS LPSPI10_InterruptGetStatus(void)
3148 {
3149 return LPSPI_InterruptGetStatus(&LPSPI10_InterruptDriverState);
3150 }
3151
3152 #endif
3153
3154 ARM_DRIVER_SPI Driver_SPI10 = {
3155 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
3156 #if defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN
3157 LPSPI10_EdmaInitialize, LPSPI10_EdmaUninitialize, LPSPI10_EdmaPowerControl, LPSPI10_EdmaSend,
3158 LPSPI10_EdmaReceive, LPSPI10_EdmaTransfer, LPSPI10_EdmaGetCount, LPSPI10_EdmaControl,
3159 LPSPI10_EdmaGetStatus
3160 #else
3161 LPSPI10_InterruptInitialize, LPSPI10_InterruptUninitialize, LPSPI10_InterruptPowerControl, LPSPI10_InterruptSend,
3162 LPSPI10_InterruptReceive, LPSPI10_InterruptTransfer, LPSPI10_InterruptGetCount, LPSPI10_InterruptControl,
3163 LPSPI10_InterruptGetStatus
3164 #endif
3165 };
3166
3167 #endif /* LPSPI10 */
3168
3169 #if defined(LPSPI11) && defined(RTE_SPI11) && RTE_SPI11
3170
3171 /* User needs to provide the implementation for LPSPI11_GetFreq/InitPins/DeinitPins
3172 in the application for enabling according instance. */
3173 extern uint32_t LPSPI11_GetFreq(void);
3174
3175 static cmsis_lpspi_resource_t LPSPI11_Resource = {LPSPI11, 11, LPSPI11_GetFreq};
3176
3177 #if defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN
3178
3179 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3180 static cmsis_lpspi_edma_resource_t LPSPI11_EdmaResource = {
3181 RTE_SPI11_DMA_TX_DMA_BASE, RTE_SPI11_DMA_TX_CH, (uint16_t)RTE_SPI11_DMA_TX_PERI_SEL,
3182 RTE_SPI11_DMA_RX_DMA_BASE, RTE_SPI11_DMA_RX_CH, (uint16_t)RTE_SPI11_DMA_RX_PERI_SEL,
3183 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3184 RTE_SPI11_DMA_TX_DMAMUX_BASE, RTE_SPI11_DMA_RX_DMAMUX_BASE,
3185 #endif
3186 };
3187
3188 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI11_EdmaHandle);
3189 static edma_handle_t LPSPI11_EdmaTxDataToTxRegHandle;
3190 static edma_handle_t LPSPI11_EdmaRxRegToRxDataHandle;
3191
3192 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3193 ARMCC_SECTION("lpspi11_edma_driver_state")
3194 static cmsis_lpspi_edma_driver_state_t LPSPI11_EdmaDriverState = {
3195 #else
3196 static cmsis_lpspi_edma_driver_state_t LPSPI11_EdmaDriverState = {
3197 #endif
3198 &LPSPI11_Resource,
3199 &LPSPI11_EdmaResource,
3200 &LPSPI11_EdmaHandle,
3201 &LPSPI11_EdmaRxRegToRxDataHandle,
3202 &LPSPI11_EdmaTxDataToTxRegHandle,
3203 };
3204
LPSPI11_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)3205 static int32_t LPSPI11_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
3206 {
3207 #ifdef RTE_SPI11_PIN_INIT
3208 RTE_SPI11_PIN_INIT();
3209 #endif
3210 return LPSPI_EdmaInitialize(cb_event, &LPSPI11_EdmaDriverState);
3211 }
3212
LPSPI11_EdmaUninitialize(void)3213 static int32_t LPSPI11_EdmaUninitialize(void)
3214 {
3215 #ifdef RTE_SPI11_PIN_DEINIT
3216 RTE_SPI11_PIN_DEINIT();
3217 #endif
3218 return LPSPI_EdmaUninitialize(&LPSPI11_EdmaDriverState);
3219 }
3220
LPSPI11_EdmaPowerControl(ARM_POWER_STATE state)3221 static int32_t LPSPI11_EdmaPowerControl(ARM_POWER_STATE state)
3222 {
3223 return LPSPI_EdmaPowerControl(state, &LPSPI11_EdmaDriverState);
3224 }
3225
LPSPI11_EdmaSend(const void * data,uint32_t num)3226 static int32_t LPSPI11_EdmaSend(const void *data, uint32_t num)
3227 {
3228 return LPSPI_EdmaSend(data, num, &LPSPI11_EdmaDriverState);
3229 }
3230
LPSPI11_EdmaReceive(void * data,uint32_t num)3231 static int32_t LPSPI11_EdmaReceive(void *data, uint32_t num)
3232 {
3233 return LPSPI_EdmaReceive(data, num, &LPSPI11_EdmaDriverState);
3234 }
3235
LPSPI11_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3236 static int32_t LPSPI11_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3237 {
3238 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI11_EdmaDriverState);
3239 }
3240
LPSPI11_EdmaGetCount(void)3241 static uint32_t LPSPI11_EdmaGetCount(void)
3242 {
3243 return LPSPI_EdmaGetCount(&LPSPI11_EdmaDriverState);
3244 }
3245
LPSPI11_EdmaControl(uint32_t control,uint32_t arg)3246 static int32_t LPSPI11_EdmaControl(uint32_t control, uint32_t arg)
3247 {
3248 return LPSPI_EdmaControl(control, arg, &LPSPI11_EdmaDriverState);
3249 }
3250
LPSPI11_EdmaGetStatus(void)3251 static ARM_SPI_STATUS LPSPI11_EdmaGetStatus(void)
3252 {
3253 return LPSPI_EdmaGetStatus(&LPSPI11_EdmaDriverState);
3254 }
3255
3256 #endif
3257
3258 #else
3259
3260 static cmsis_lpspi_handle_t LPSPI11_Handle;
3261
3262 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3263 ARMCC_SECTION("lpspi11_interrupt_driver_state")
3264 static cmsis_lpspi_interrupt_driver_state_t LPSPI11_InterruptDriverState = {
3265 #else
3266 static cmsis_lpspi_interrupt_driver_state_t LPSPI11_InterruptDriverState = {
3267 #endif
3268 &LPSPI11_Resource,
3269 &LPSPI11_Handle,
3270 };
3271
LPSPI11_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3272 static int32_t LPSPI11_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3273 {
3274 #ifdef RTE_SPI11_PIN_INIT
3275 RTE_SPI11_PIN_INIT();
3276 #endif
3277 return LPSPI_InterruptInitialize(cb_event, &LPSPI11_InterruptDriverState);
3278 }
3279
LPSPI11_InterruptUninitialize(void)3280 static int32_t LPSPI11_InterruptUninitialize(void)
3281 {
3282 #ifdef RTE_SPI11_PIN_DEINIT
3283 RTE_SPI11_PIN_DEINIT();
3284 #endif
3285 return LPSPI_InterruptUninitialize(&LPSPI11_InterruptDriverState);
3286 }
3287
LPSPI11_InterruptPowerControl(ARM_POWER_STATE state)3288 static int32_t LPSPI11_InterruptPowerControl(ARM_POWER_STATE state)
3289 {
3290 return LPSPI_InterruptPowerControl(state, &LPSPI11_InterruptDriverState);
3291 }
3292
LPSPI11_InterruptSend(const void * data,uint32_t num)3293 static int32_t LPSPI11_InterruptSend(const void *data, uint32_t num)
3294 {
3295 return LPSPI_InterruptSend(data, num, &LPSPI11_InterruptDriverState);
3296 }
3297
LPSPI11_InterruptReceive(void * data,uint32_t num)3298 static int32_t LPSPI11_InterruptReceive(void *data, uint32_t num)
3299 {
3300 return LPSPI_InterruptReceive(data, num, &LPSPI11_InterruptDriverState);
3301 }
3302
LPSPI11_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3303 static int32_t LPSPI11_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3304 {
3305 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI11_InterruptDriverState);
3306 }
3307
LPSPI11_InterruptGetCount(void)3308 static uint32_t LPSPI11_InterruptGetCount(void)
3309 {
3310 return LPSPI_InterruptGetCount(&LPSPI11_InterruptDriverState);
3311 }
3312
LPSPI11_InterruptControl(uint32_t control,uint32_t arg)3313 static int32_t LPSPI11_InterruptControl(uint32_t control, uint32_t arg)
3314 {
3315 return LPSPI_InterruptControl(control, arg, &LPSPI11_InterruptDriverState);
3316 }
3317
LPSPI11_InterruptGetStatus(void)3318 static ARM_SPI_STATUS LPSPI11_InterruptGetStatus(void)
3319 {
3320 return LPSPI_InterruptGetStatus(&LPSPI11_InterruptDriverState);
3321 }
3322
3323 #endif
3324
3325 ARM_DRIVER_SPI Driver_SPI11 = {
3326 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
3327 #if defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN
3328 LPSPI11_EdmaInitialize, LPSPI11_EdmaUninitialize, LPSPI11_EdmaPowerControl, LPSPI11_EdmaSend,
3329 LPSPI11_EdmaReceive, LPSPI11_EdmaTransfer, LPSPI11_EdmaGetCount, LPSPI11_EdmaControl,
3330 LPSPI11_EdmaGetStatus
3331 #else
3332 LPSPI11_InterruptInitialize, LPSPI11_InterruptUninitialize, LPSPI11_InterruptPowerControl, LPSPI11_InterruptSend,
3333 LPSPI11_InterruptReceive, LPSPI11_InterruptTransfer, LPSPI11_InterruptGetCount, LPSPI11_InterruptControl,
3334 LPSPI11_InterruptGetStatus
3335 #endif
3336 };
3337
3338 #endif /* LPSPI11 */
3339
3340 #if defined(LPSPI12) && defined(RTE_SPI12) && RTE_SPI12
3341
3342 /* User needs to provide the implementation for LPSPI12_GetFreq/InitPins/DeinitPins
3343 in the application for enabling according instance. */
3344 extern uint32_t LPSPI12_GetFreq(void);
3345
3346 static cmsis_lpspi_resource_t LPSPI12_Resource = {LPSPI12, 12, LPSPI12_GetFreq};
3347
3348 #if defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN
3349
3350 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3351 static cmsis_lpspi_edma_resource_t LPSPI12_EdmaResource = {
3352 RTE_SPI12_DMA_TX_DMA_BASE, RTE_SPI12_DMA_TX_CH, (uint16_t)RTE_SPI12_DMA_TX_PERI_SEL,
3353 RTE_SPI12_DMA_RX_DMA_BASE, RTE_SPI12_DMA_RX_CH, (uint16_t)RTE_SPI12_DMA_RX_PERI_SEL,
3354 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3355 RTE_SPI12_DMA_TX_DMAMUX_BASE, RTE_SPI12_DMA_RX_DMAMUX_BASE,
3356 #endif
3357 };
3358
3359 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI12_EdmaHandle);
3360 static edma_handle_t LPSPI12_EdmaTxDataToTxRegHandle;
3361 static edma_handle_t LPSPI12_EdmaRxRegToRxDataHandle;
3362
3363 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3364 ARMCC_SECTION("lpspi12_edma_driver_state")
3365 static cmsis_lpspi_edma_driver_state_t LPSPI12_EdmaDriverState = {
3366 #else
3367 static cmsis_lpspi_edma_driver_state_t LPSPI12_EdmaDriverState = {
3368 #endif
3369 &LPSPI12_Resource,
3370 &LPSPI12_EdmaResource,
3371 &LPSPI12_EdmaHandle,
3372 &LPSPI12_EdmaRxRegToRxDataHandle,
3373 &LPSPI12_EdmaTxDataToTxRegHandle,
3374 };
3375
LPSPI12_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)3376 static int32_t LPSPI12_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
3377 {
3378 #ifdef RTE_SPI12_PIN_INIT
3379 RTE_SPI12_PIN_INIT();
3380 #endif
3381 return LPSPI_EdmaInitialize(cb_event, &LPSPI12_EdmaDriverState);
3382 }
3383
LPSPI12_EdmaUninitialize(void)3384 static int32_t LPSPI12_EdmaUninitialize(void)
3385 {
3386 #ifdef RTE_SPI12_PIN_DEINIT
3387 RTE_SPI12_PIN_DEINIT();
3388 #endif
3389 return LPSPI_EdmaUninitialize(&LPSPI12_EdmaDriverState);
3390 }
3391
LPSPI12_EdmaPowerControl(ARM_POWER_STATE state)3392 static int32_t LPSPI12_EdmaPowerControl(ARM_POWER_STATE state)
3393 {
3394 return LPSPI_EdmaPowerControl(state, &LPSPI12_EdmaDriverState);
3395 }
3396
LPSPI12_EdmaSend(const void * data,uint32_t num)3397 static int32_t LPSPI12_EdmaSend(const void *data, uint32_t num)
3398 {
3399 return LPSPI_EdmaSend(data, num, &LPSPI12_EdmaDriverState);
3400 }
3401
LPSPI12_EdmaReceive(void * data,uint32_t num)3402 static int32_t LPSPI12_EdmaReceive(void *data, uint32_t num)
3403 {
3404 return LPSPI_EdmaReceive(data, num, &LPSPI12_EdmaDriverState);
3405 }
3406
LPSPI12_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3407 static int32_t LPSPI12_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3408 {
3409 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI12_EdmaDriverState);
3410 }
3411
LPSPI12_EdmaGetCount(void)3412 static uint32_t LPSPI12_EdmaGetCount(void)
3413 {
3414 return LPSPI_EdmaGetCount(&LPSPI12_EdmaDriverState);
3415 }
3416
LPSPI12_EdmaControl(uint32_t control,uint32_t arg)3417 static int32_t LPSPI12_EdmaControl(uint32_t control, uint32_t arg)
3418 {
3419 return LPSPI_EdmaControl(control, arg, &LPSPI12_EdmaDriverState);
3420 }
3421
LPSPI12_EdmaGetStatus(void)3422 static ARM_SPI_STATUS LPSPI12_EdmaGetStatus(void)
3423 {
3424 return LPSPI_EdmaGetStatus(&LPSPI12_EdmaDriverState);
3425 }
3426
3427 #endif
3428
3429 #else
3430
3431 static cmsis_lpspi_handle_t LPSPI12_Handle;
3432
3433 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3434 ARMCC_SECTION("lpspi12_interrupt_driver_state")
3435 static cmsis_lpspi_interrupt_driver_state_t LPSPI12_InterruptDriverState = {
3436 #else
3437 static cmsis_lpspi_interrupt_driver_state_t LPSPI12_InterruptDriverState = {
3438 #endif
3439 &LPSPI12_Resource,
3440 &LPSPI12_Handle,
3441 };
3442
LPSPI12_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3443 static int32_t LPSPI12_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3444 {
3445 #ifdef RTE_SPI12_PIN_INIT
3446 RTE_SPI12_PIN_INIT();
3447 #endif
3448 return LPSPI_InterruptInitialize(cb_event, &LPSPI12_InterruptDriverState);
3449 }
3450
LPSPI12_InterruptUninitialize(void)3451 static int32_t LPSPI12_InterruptUninitialize(void)
3452 {
3453 #ifdef RTE_SPI12_PIN_DEINIT
3454 RTE_SPI12_PIN_DEINIT();
3455 #endif
3456 return LPSPI_InterruptUninitialize(&LPSPI12_InterruptDriverState);
3457 }
3458
LPSPI12_InterruptPowerControl(ARM_POWER_STATE state)3459 static int32_t LPSPI12_InterruptPowerControl(ARM_POWER_STATE state)
3460 {
3461 return LPSPI_InterruptPowerControl(state, &LPSPI12_InterruptDriverState);
3462 }
3463
LPSPI12_InterruptSend(const void * data,uint32_t num)3464 static int32_t LPSPI12_InterruptSend(const void *data, uint32_t num)
3465 {
3466 return LPSPI_InterruptSend(data, num, &LPSPI12_InterruptDriverState);
3467 }
3468
LPSPI12_InterruptReceive(void * data,uint32_t num)3469 static int32_t LPSPI12_InterruptReceive(void *data, uint32_t num)
3470 {
3471 return LPSPI_InterruptReceive(data, num, &LPSPI12_InterruptDriverState);
3472 }
3473
LPSPI12_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3474 static int32_t LPSPI12_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3475 {
3476 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI12_InterruptDriverState);
3477 }
3478
LPSPI12_InterruptGetCount(void)3479 static uint32_t LPSPI12_InterruptGetCount(void)
3480 {
3481 return LPSPI_InterruptGetCount(&LPSPI12_InterruptDriverState);
3482 }
3483
LPSPI12_InterruptControl(uint32_t control,uint32_t arg)3484 static int32_t LPSPI12_InterruptControl(uint32_t control, uint32_t arg)
3485 {
3486 return LPSPI_InterruptControl(control, arg, &LPSPI12_InterruptDriverState);
3487 }
3488
LPSPI12_InterruptGetStatus(void)3489 static ARM_SPI_STATUS LPSPI12_InterruptGetStatus(void)
3490 {
3491 return LPSPI_InterruptGetStatus(&LPSPI12_InterruptDriverState);
3492 }
3493
3494 #endif
3495
3496 ARM_DRIVER_SPI Driver_SPI12 = {
3497 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
3498 #if defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN
3499 LPSPI12_EdmaInitialize, LPSPI12_EdmaUninitialize, LPSPI12_EdmaPowerControl, LPSPI12_EdmaSend,
3500 LPSPI12_EdmaReceive, LPSPI12_EdmaTransfer, LPSPI12_EdmaGetCount, LPSPI12_EdmaControl,
3501 LPSPI12_EdmaGetStatus
3502 #else
3503 LPSPI12_InterruptInitialize, LPSPI12_InterruptUninitialize, LPSPI12_InterruptPowerControl, LPSPI12_InterruptSend,
3504 LPSPI12_InterruptReceive, LPSPI12_InterruptTransfer, LPSPI12_InterruptGetCount, LPSPI12_InterruptControl,
3505 LPSPI12_InterruptGetStatus
3506 #endif
3507 };
3508
3509 #endif /* LPSPI12 */
3510
3511 #if defined(LPSPI13) && defined(RTE_SPI13) && RTE_SPI13
3512
3513 /* User needs to provide the implementation for LPSPI13_GetFreq/InitPins/DeinitPins
3514 in the application for enabling according instance. */
3515 extern uint32_t LPSPI13_GetFreq(void);
3516
3517 static cmsis_lpspi_resource_t LPSPI13_Resource = {LPSPI13, 13, LPSPI13_GetFreq};
3518
3519 #if defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN
3520
3521 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3522 static cmsis_lpspi_edma_resource_t LPSPI13_EdmaResource = {
3523 RTE_SPI13_DMA_TX_DMA_BASE, RTE_SPI13_DMA_TX_CH, (uint16_t)RTE_SPI13_DMA_TX_PERI_SEL,
3524 RTE_SPI13_DMA_RX_DMA_BASE, RTE_SPI13_DMA_RX_CH, (uint16_t)RTE_SPI13_DMA_RX_PERI_SEL,
3525 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3526 RTE_SPI13_DMA_TX_DMAMUX_BASE, RTE_SPI13_DMA_RX_DMAMUX_BASE,
3527 #endif
3528 };
3529
3530 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI13_EdmaHandle);
3531 static edma_handle_t LPSPI13_EdmaTxDataToTxRegHandle;
3532 static edma_handle_t LPSPI13_EdmaRxRegToRxDataHandle;
3533
3534 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3535 ARMCC_SECTION("lpspi13_edma_driver_state")
3536 static cmsis_lpspi_edma_driver_state_t LPSPI13_EdmaDriverState = {
3537 #else
3538 static cmsis_lpspi_edma_driver_state_t LPSPI13_EdmaDriverState = {
3539 #endif
3540 &LPSPI13_Resource,
3541 &LPSPI13_EdmaResource,
3542 &LPSPI13_EdmaHandle,
3543 &LPSPI13_EdmaRxRegToRxDataHandle,
3544 &LPSPI13_EdmaTxDataToTxRegHandle,
3545 };
3546
LPSPI13_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)3547 static int32_t LPSPI13_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
3548 {
3549 #ifdef RTE_SPI13_PIN_INIT
3550 RTE_SPI13_PIN_INIT();
3551 #endif
3552 return LPSPI_EdmaInitialize(cb_event, &LPSPI13_EdmaDriverState);
3553 }
3554
LPSPI13_EdmaUninitialize(void)3555 static int32_t LPSPI13_EdmaUninitialize(void)
3556 {
3557 #ifdef RTE_SPI13_PIN_DEINIT
3558 RTE_SPI13_PIN_DEINIT();
3559 #endif
3560 return LPSPI_EdmaUninitialize(&LPSPI13_EdmaDriverState);
3561 }
3562
LPSPI13_EdmaPowerControl(ARM_POWER_STATE state)3563 static int32_t LPSPI13_EdmaPowerControl(ARM_POWER_STATE state)
3564 {
3565 return LPSPI_EdmaPowerControl(state, &LPSPI13_EdmaDriverState);
3566 }
3567
LPSPI13_EdmaSend(const void * data,uint32_t num)3568 static int32_t LPSPI13_EdmaSend(const void *data, uint32_t num)
3569 {
3570 return LPSPI_EdmaSend(data, num, &LPSPI13_EdmaDriverState);
3571 }
3572
LPSPI13_EdmaReceive(void * data,uint32_t num)3573 static int32_t LPSPI13_EdmaReceive(void *data, uint32_t num)
3574 {
3575 return LPSPI_EdmaReceive(data, num, &LPSPI13_EdmaDriverState);
3576 }
3577
LPSPI13_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3578 static int32_t LPSPI13_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3579 {
3580 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI13_EdmaDriverState);
3581 }
3582
LPSPI13_EdmaGetCount(void)3583 static uint32_t LPSPI13_EdmaGetCount(void)
3584 {
3585 return LPSPI_EdmaGetCount(&LPSPI13_EdmaDriverState);
3586 }
3587
LPSPI13_EdmaControl(uint32_t control,uint32_t arg)3588 static int32_t LPSPI13_EdmaControl(uint32_t control, uint32_t arg)
3589 {
3590 return LPSPI_EdmaControl(control, arg, &LPSPI13_EdmaDriverState);
3591 }
3592
LPSPI13_EdmaGetStatus(void)3593 static ARM_SPI_STATUS LPSPI13_EdmaGetStatus(void)
3594 {
3595 return LPSPI_EdmaGetStatus(&LPSPI13_EdmaDriverState);
3596 }
3597
3598 #endif
3599
3600 #else
3601
3602 static cmsis_lpspi_handle_t LPSPI13_Handle;
3603
3604 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3605 ARMCC_SECTION("lpspi13_interrupt_driver_state")
3606 static cmsis_lpspi_interrupt_driver_state_t LPSPI13_InterruptDriverState = {
3607 #else
3608 static cmsis_lpspi_interrupt_driver_state_t LPSPI13_InterruptDriverState = {
3609 #endif
3610 &LPSPI13_Resource,
3611 &LPSPI13_Handle,
3612 };
3613
LPSPI13_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3614 static int32_t LPSPI13_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3615 {
3616 #ifdef RTE_SPI13_PIN_INIT
3617 RTE_SPI13_PIN_INIT();
3618 #endif
3619 return LPSPI_InterruptInitialize(cb_event, &LPSPI13_InterruptDriverState);
3620 }
3621
LPSPI13_InterruptUninitialize(void)3622 static int32_t LPSPI13_InterruptUninitialize(void)
3623 {
3624 #ifdef RTE_SPI13_PIN_DEINIT
3625 RTE_SPI13_PIN_DEINIT();
3626 #endif
3627 return LPSPI_InterruptUninitialize(&LPSPI13_InterruptDriverState);
3628 }
3629
LPSPI13_InterruptPowerControl(ARM_POWER_STATE state)3630 static int32_t LPSPI13_InterruptPowerControl(ARM_POWER_STATE state)
3631 {
3632 return LPSPI_InterruptPowerControl(state, &LPSPI13_InterruptDriverState);
3633 }
3634
LPSPI13_InterruptSend(const void * data,uint32_t num)3635 static int32_t LPSPI13_InterruptSend(const void *data, uint32_t num)
3636 {
3637 return LPSPI_InterruptSend(data, num, &LPSPI13_InterruptDriverState);
3638 }
3639
LPSPI13_InterruptReceive(void * data,uint32_t num)3640 static int32_t LPSPI13_InterruptReceive(void *data, uint32_t num)
3641 {
3642 return LPSPI_InterruptReceive(data, num, &LPSPI13_InterruptDriverState);
3643 }
3644
LPSPI13_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3645 static int32_t LPSPI13_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3646 {
3647 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI13_InterruptDriverState);
3648 }
3649
LPSPI13_InterruptGetCount(void)3650 static uint32_t LPSPI13_InterruptGetCount(void)
3651 {
3652 return LPSPI_InterruptGetCount(&LPSPI13_InterruptDriverState);
3653 }
3654
LPSPI13_InterruptControl(uint32_t control,uint32_t arg)3655 static int32_t LPSPI13_InterruptControl(uint32_t control, uint32_t arg)
3656 {
3657 return LPSPI_InterruptControl(control, arg, &LPSPI13_InterruptDriverState);
3658 }
3659
LPSPI13_InterruptGetStatus(void)3660 static ARM_SPI_STATUS LPSPI13_InterruptGetStatus(void)
3661 {
3662 return LPSPI_InterruptGetStatus(&LPSPI13_InterruptDriverState);
3663 }
3664
3665 #endif
3666
3667 ARM_DRIVER_SPI Driver_SPI13 = {
3668 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
3669 #if defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN
3670 LPSPI13_EdmaInitialize, LPSPI13_EdmaUninitialize, LPSPI13_EdmaPowerControl, LPSPI13_EdmaSend,
3671 LPSPI13_EdmaReceive, LPSPI13_EdmaTransfer, LPSPI13_EdmaGetCount, LPSPI13_EdmaControl,
3672 LPSPI13_EdmaGetStatus
3673 #else
3674 LPSPI13_InterruptInitialize, LPSPI13_InterruptUninitialize, LPSPI13_InterruptPowerControl, LPSPI13_InterruptSend,
3675 LPSPI13_InterruptReceive, LPSPI13_InterruptTransfer, LPSPI13_InterruptGetCount, LPSPI13_InterruptControl,
3676 LPSPI13_InterruptGetStatus
3677 #endif
3678 };
3679
3680 #endif /* LPSPI13 */
3681
3682 #if defined(LPSPI14) && defined(RTE_SPI14) && RTE_SPI14
3683
3684 /* User needs to provide the implementation for LPSPI14_GetFreq/InitPins/DeinitPins
3685 in the application for enabling according instance. */
3686 extern uint32_t LPSPI14_GetFreq(void);
3687
3688 static cmsis_lpspi_resource_t LPSPI14_Resource = {LPSPI14, 14, LPSPI14_GetFreq};
3689
3690 #if defined(RTE_SPI14_DMA_EN) && RTE_SPI14_DMA_EN
3691
3692 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3693 static cmsis_lpspi_edma_resource_t LPSPI14_EdmaResource = {
3694 RTE_SPI14_DMA_TX_DMA_BASE, RTE_SPI14_DMA_TX_CH, (uint16_t)RTE_SPI14_DMA_TX_PERI_SEL,
3695 RTE_SPI14_DMA_RX_DMA_BASE, RTE_SPI14_DMA_RX_CH, (uint16_t)RTE_SPI14_DMA_RX_PERI_SEL,
3696 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3697 RTE_SPI14_DMA_TX_DMAMUX_BASE, RTE_SPI14_DMA_RX_DMAMUX_BASE,
3698 #endif
3699 };
3700
3701 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI14_EdmaHandle);
3702 static edma_handle_t LPSPI14_EdmaTxDataToTxRegHandle;
3703 static edma_handle_t LPSPI14_EdmaRxRegToRxDataHandle;
3704
3705 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3706 ARMCC_SECTION("lpspi14_edma_driver_state")
3707 static cmsis_lpspi_edma_driver_state_t LPSPI14_EdmaDriverState = {
3708 #else
3709 static cmsis_lpspi_edma_driver_state_t LPSPI14_EdmaDriverState = {
3710 #endif
3711 &LPSPI14_Resource,
3712 &LPSPI14_EdmaResource,
3713 &LPSPI14_EdmaHandle,
3714 &LPSPI14_EdmaRxRegToRxDataHandle,
3715 &LPSPI14_EdmaTxDataToTxRegHandle,
3716 };
3717
LPSPI14_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)3718 static int32_t LPSPI14_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
3719 {
3720 #ifdef RTE_SPI14_PIN_INIT
3721 RTE_SPI14_PIN_INIT();
3722 #endif
3723 return LPSPI_EdmaInitialize(cb_event, &LPSPI14_EdmaDriverState);
3724 }
3725
LPSPI14_EdmaUninitialize(void)3726 static int32_t LPSPI14_EdmaUninitialize(void)
3727 {
3728 #ifdef RTE_SPI14_PIN_DEINIT
3729 RTE_SPI14_PIN_DEINIT();
3730 #endif
3731 return LPSPI_EdmaUninitialize(&LPSPI14_EdmaDriverState);
3732 }
3733
LPSPI14_EdmaPowerControl(ARM_POWER_STATE state)3734 static int32_t LPSPI14_EdmaPowerControl(ARM_POWER_STATE state)
3735 {
3736 return LPSPI_EdmaPowerControl(state, &LPSPI14_EdmaDriverState);
3737 }
3738
LPSPI14_EdmaSend(const void * data,uint32_t num)3739 static int32_t LPSPI14_EdmaSend(const void *data, uint32_t num)
3740 {
3741 return LPSPI_EdmaSend(data, num, &LPSPI14_EdmaDriverState);
3742 }
3743
LPSPI14_EdmaReceive(void * data,uint32_t num)3744 static int32_t LPSPI14_EdmaReceive(void *data, uint32_t num)
3745 {
3746 return LPSPI_EdmaReceive(data, num, &LPSPI14_EdmaDriverState);
3747 }
3748
LPSPI14_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3749 static int32_t LPSPI14_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3750 {
3751 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI14_EdmaDriverState);
3752 }
3753
LPSPI14_EdmaGetCount(void)3754 static uint32_t LPSPI14_EdmaGetCount(void)
3755 {
3756 return LPSPI_EdmaGetCount(&LPSPI14_EdmaDriverState);
3757 }
3758
LPSPI14_EdmaControl(uint32_t control,uint32_t arg)3759 static int32_t LPSPI14_EdmaControl(uint32_t control, uint32_t arg)
3760 {
3761 return LPSPI_EdmaControl(control, arg, &LPSPI14_EdmaDriverState);
3762 }
3763
LPSPI14_EdmaGetStatus(void)3764 static ARM_SPI_STATUS LPSPI14_EdmaGetStatus(void)
3765 {
3766 return LPSPI_EdmaGetStatus(&LPSPI14_EdmaDriverState);
3767 }
3768
3769 #endif
3770
3771 #else
3772
3773 static cmsis_lpspi_handle_t LPSPI14_Handle;
3774
3775 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3776 ARMCC_SECTION("lpspi14_interrupt_driver_state")
3777 static cmsis_lpspi_interrupt_driver_state_t LPSPI14_InterruptDriverState = {
3778 #else
3779 static cmsis_lpspi_interrupt_driver_state_t LPSPI14_InterruptDriverState = {
3780 #endif
3781 &LPSPI14_Resource,
3782 &LPSPI14_Handle,
3783 };
3784
LPSPI14_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3785 static int32_t LPSPI14_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3786 {
3787 #ifdef RTE_SPI14_PIN_INIT
3788 RTE_SPI14_PIN_INIT();
3789 #endif
3790 return LPSPI_InterruptInitialize(cb_event, &LPSPI14_InterruptDriverState);
3791 }
3792
LPSPI14_InterruptUninitialize(void)3793 static int32_t LPSPI14_InterruptUninitialize(void)
3794 {
3795 #ifdef RTE_SPI14_PIN_DEINIT
3796 RTE_SPI14_PIN_DEINIT();
3797 #endif
3798 return LPSPI_InterruptUninitialize(&LPSPI14_InterruptDriverState);
3799 }
3800
LPSPI14_InterruptPowerControl(ARM_POWER_STATE state)3801 static int32_t LPSPI14_InterruptPowerControl(ARM_POWER_STATE state)
3802 {
3803 return LPSPI_InterruptPowerControl(state, &LPSPI14_InterruptDriverState);
3804 }
3805
LPSPI14_InterruptSend(const void * data,uint32_t num)3806 static int32_t LPSPI14_InterruptSend(const void *data, uint32_t num)
3807 {
3808 return LPSPI_InterruptSend(data, num, &LPSPI14_InterruptDriverState);
3809 }
3810
LPSPI14_InterruptReceive(void * data,uint32_t num)3811 static int32_t LPSPI14_InterruptReceive(void *data, uint32_t num)
3812 {
3813 return LPSPI_InterruptReceive(data, num, &LPSPI14_InterruptDriverState);
3814 }
3815
LPSPI14_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3816 static int32_t LPSPI14_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3817 {
3818 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI14_InterruptDriverState);
3819 }
3820
LPSPI14_InterruptGetCount(void)3821 static uint32_t LPSPI14_InterruptGetCount(void)
3822 {
3823 return LPSPI_InterruptGetCount(&LPSPI14_InterruptDriverState);
3824 }
3825
LPSPI14_InterruptControl(uint32_t control,uint32_t arg)3826 static int32_t LPSPI14_InterruptControl(uint32_t control, uint32_t arg)
3827 {
3828 return LPSPI_InterruptControl(control, arg, &LPSPI14_InterruptDriverState);
3829 }
3830
LPSPI14_InterruptGetStatus(void)3831 static ARM_SPI_STATUS LPSPI14_InterruptGetStatus(void)
3832 {
3833 return LPSPI_InterruptGetStatus(&LPSPI14_InterruptDriverState);
3834 }
3835
3836 #endif
3837
3838 ARM_DRIVER_SPI Driver_SPI14 = {
3839 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
3840 #if defined(RTE_SPI14_DMA_EN) && RTE_SPI14_DMA_EN
3841 LPSPI14_EdmaInitialize, LPSPI14_EdmaUninitialize, LPSPI14_EdmaPowerControl, LPSPI14_EdmaSend,
3842 LPSPI14_EdmaReceive, LPSPI14_EdmaTransfer, LPSPI14_EdmaGetCount, LPSPI14_EdmaControl,
3843 LPSPI14_EdmaGetStatus
3844 #else
3845 LPSPI14_InterruptInitialize, LPSPI14_InterruptUninitialize, LPSPI14_InterruptPowerControl, LPSPI14_InterruptSend,
3846 LPSPI14_InterruptReceive, LPSPI14_InterruptTransfer, LPSPI14_InterruptGetCount, LPSPI14_InterruptControl,
3847 LPSPI14_InterruptGetStatus
3848 #endif
3849 };
3850
3851 #endif /* LPSPI14 */
3852
3853 #if defined(LPSPI15) && defined(RTE_SPI15) && RTE_SPI15
3854
3855 /* User needs to provide the implementation for LPSPI15_GetFreq/InitPins/DeinitPins
3856 in the application for enabling according instance. */
3857 extern uint32_t LPSPI15_GetFreq(void);
3858
3859 static cmsis_lpspi_resource_t LPSPI15_Resource = {LPSPI15, 15, LPSPI15_GetFreq};
3860
3861 #if defined(RTE_SPI15_DMA_EN) && RTE_SPI15_DMA_EN
3862
3863 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
3864 static cmsis_lpspi_edma_resource_t LPSPI15_EdmaResource = {
3865 RTE_SPI15_DMA_TX_DMA_BASE, RTE_SPI15_DMA_TX_CH, (uint16_t)RTE_SPI15_DMA_TX_PERI_SEL,
3866 RTE_SPI15_DMA_RX_DMA_BASE, RTE_SPI15_DMA_RX_CH, (uint16_t)RTE_SPI15_DMA_RX_PERI_SEL,
3867 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
3868 RTE_SPI15_DMA_TX_DMAMUX_BASE, RTE_SPI15_DMA_RX_DMAMUX_BASE,
3869 #endif
3870 };
3871
3872 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI15_EdmaHandle);
3873 static edma_handle_t LPSPI15_EdmaTxDataToTxRegHandle;
3874 static edma_handle_t LPSPI15_EdmaRxRegToRxDataHandle;
3875
3876 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3877 ARMCC_SECTION("lpspi15_edma_driver_state")
3878 static cmsis_lpspi_edma_driver_state_t LPSPI15_EdmaDriverState = {
3879 #else
3880 static cmsis_lpspi_edma_driver_state_t LPSPI15_EdmaDriverState = {
3881 #endif
3882 &LPSPI15_Resource,
3883 &LPSPI15_EdmaResource,
3884 &LPSPI15_EdmaHandle,
3885 &LPSPI15_EdmaRxRegToRxDataHandle,
3886 &LPSPI15_EdmaTxDataToTxRegHandle,
3887 };
3888
LPSPI15_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)3889 static int32_t LPSPI15_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
3890 {
3891 #ifdef RTE_SPI15_PIN_INIT
3892 RTE_SPI15_PIN_INIT();
3893 #endif
3894 return LPSPI_EdmaInitialize(cb_event, &LPSPI15_EdmaDriverState);
3895 }
3896
LPSPI15_EdmaUninitialize(void)3897 static int32_t LPSPI15_EdmaUninitialize(void)
3898 {
3899 #ifdef RTE_SPI15_PIN_DEINIT
3900 RTE_SPI15_PIN_DEINIT();
3901 #endif
3902 return LPSPI_EdmaUninitialize(&LPSPI15_EdmaDriverState);
3903 }
3904
LPSPI15_EdmaPowerControl(ARM_POWER_STATE state)3905 static int32_t LPSPI15_EdmaPowerControl(ARM_POWER_STATE state)
3906 {
3907 return LPSPI_EdmaPowerControl(state, &LPSPI15_EdmaDriverState);
3908 }
3909
LPSPI15_EdmaSend(const void * data,uint32_t num)3910 static int32_t LPSPI15_EdmaSend(const void *data, uint32_t num)
3911 {
3912 return LPSPI_EdmaSend(data, num, &LPSPI15_EdmaDriverState);
3913 }
3914
LPSPI15_EdmaReceive(void * data,uint32_t num)3915 static int32_t LPSPI15_EdmaReceive(void *data, uint32_t num)
3916 {
3917 return LPSPI_EdmaReceive(data, num, &LPSPI15_EdmaDriverState);
3918 }
3919
LPSPI15_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)3920 static int32_t LPSPI15_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
3921 {
3922 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI15_EdmaDriverState);
3923 }
3924
LPSPI15_EdmaGetCount(void)3925 static uint32_t LPSPI15_EdmaGetCount(void)
3926 {
3927 return LPSPI_EdmaGetCount(&LPSPI15_EdmaDriverState);
3928 }
3929
LPSPI15_EdmaControl(uint32_t control,uint32_t arg)3930 static int32_t LPSPI15_EdmaControl(uint32_t control, uint32_t arg)
3931 {
3932 return LPSPI_EdmaControl(control, arg, &LPSPI15_EdmaDriverState);
3933 }
3934
LPSPI15_EdmaGetStatus(void)3935 static ARM_SPI_STATUS LPSPI15_EdmaGetStatus(void)
3936 {
3937 return LPSPI_EdmaGetStatus(&LPSPI15_EdmaDriverState);
3938 }
3939
3940 #endif
3941
3942 #else
3943
3944 static cmsis_lpspi_handle_t LPSPI15_Handle;
3945
3946 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3947 ARMCC_SECTION("lpspi15_interrupt_driver_state")
3948 static cmsis_lpspi_interrupt_driver_state_t LPSPI15_InterruptDriverState = {
3949 #else
3950 static cmsis_lpspi_interrupt_driver_state_t LPSPI15_InterruptDriverState = {
3951 #endif
3952 &LPSPI15_Resource,
3953 &LPSPI15_Handle,
3954 };
3955
LPSPI15_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3956 static int32_t LPSPI15_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3957 {
3958 #ifdef RTE_SPI15_PIN_INIT
3959 RTE_SPI15_PIN_INIT();
3960 #endif
3961 return LPSPI_InterruptInitialize(cb_event, &LPSPI15_InterruptDriverState);
3962 }
3963
LPSPI15_InterruptUninitialize(void)3964 static int32_t LPSPI15_InterruptUninitialize(void)
3965 {
3966 #ifdef RTE_SPI15_PIN_DEINIT
3967 RTE_SPI15_PIN_DEINIT();
3968 #endif
3969 return LPSPI_InterruptUninitialize(&LPSPI15_InterruptDriverState);
3970 }
3971
LPSPI15_InterruptPowerControl(ARM_POWER_STATE state)3972 static int32_t LPSPI15_InterruptPowerControl(ARM_POWER_STATE state)
3973 {
3974 return LPSPI_InterruptPowerControl(state, &LPSPI15_InterruptDriverState);
3975 }
3976
LPSPI15_InterruptSend(const void * data,uint32_t num)3977 static int32_t LPSPI15_InterruptSend(const void *data, uint32_t num)
3978 {
3979 return LPSPI_InterruptSend(data, num, &LPSPI15_InterruptDriverState);
3980 }
3981
LPSPI15_InterruptReceive(void * data,uint32_t num)3982 static int32_t LPSPI15_InterruptReceive(void *data, uint32_t num)
3983 {
3984 return LPSPI_InterruptReceive(data, num, &LPSPI15_InterruptDriverState);
3985 }
3986
LPSPI15_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3987 static int32_t LPSPI15_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3988 {
3989 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI15_InterruptDriverState);
3990 }
3991
LPSPI15_InterruptGetCount(void)3992 static uint32_t LPSPI15_InterruptGetCount(void)
3993 {
3994 return LPSPI_InterruptGetCount(&LPSPI15_InterruptDriverState);
3995 }
3996
LPSPI15_InterruptControl(uint32_t control,uint32_t arg)3997 static int32_t LPSPI15_InterruptControl(uint32_t control, uint32_t arg)
3998 {
3999 return LPSPI_InterruptControl(control, arg, &LPSPI15_InterruptDriverState);
4000 }
4001
LPSPI15_InterruptGetStatus(void)4002 static ARM_SPI_STATUS LPSPI15_InterruptGetStatus(void)
4003 {
4004 return LPSPI_InterruptGetStatus(&LPSPI15_InterruptDriverState);
4005 }
4006
4007 #endif
4008
4009 ARM_DRIVER_SPI Driver_SPI15 = {
4010 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
4011 #if defined(RTE_SPI15_DMA_EN) && RTE_SPI15_DMA_EN
4012 LPSPI15_EdmaInitialize, LPSPI15_EdmaUninitialize, LPSPI15_EdmaPowerControl, LPSPI15_EdmaSend,
4013 LPSPI15_EdmaReceive, LPSPI15_EdmaTransfer, LPSPI15_EdmaGetCount, LPSPI15_EdmaControl,
4014 LPSPI15_EdmaGetStatus
4015 #else
4016 LPSPI15_InterruptInitialize, LPSPI15_InterruptUninitialize, LPSPI15_InterruptPowerControl, LPSPI15_InterruptSend,
4017 LPSPI15_InterruptReceive, LPSPI15_InterruptTransfer, LPSPI15_InterruptGetCount, LPSPI15_InterruptControl,
4018 LPSPI15_InterruptGetStatus
4019 #endif
4020 };
4021
4022 #endif /* LPSPI15 */
4023
4024 #if defined(LPSPI16) && defined(RTE_SPI16) && RTE_SPI16
4025
4026 /* User needs to provide the implementation for LPSPI16_GetFreq/InitPins/DeinitPins
4027 in the application for enabling according instance. */
4028 extern uint32_t LPSPI16_GetFreq(void);
4029
4030 static cmsis_lpspi_resource_t LPSPI16_Resource = {LPSPI16, 16, LPSPI16_GetFreq};
4031
4032 #if defined(RTE_SPI16_DMA_EN) && RTE_SPI16_DMA_EN
4033
4034 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4035 static cmsis_lpspi_edma_resource_t LPSPI16_EdmaResource = {
4036 RTE_SPI16_DMA_TX_DMA_BASE, RTE_SPI16_DMA_TX_CH, (uint16_t)RTE_SPI16_DMA_TX_PERI_SEL,
4037 RTE_SPI16_DMA_RX_DMA_BASE, RTE_SPI16_DMA_RX_CH, (uint16_t)RTE_SPI16_DMA_RX_PERI_SEL,
4038 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4039 RTE_SPI16_DMA_TX_DMAMUX_BASE, RTE_SPI16_DMA_RX_DMAMUX_BASE,
4040 #endif
4041 };
4042
4043 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI16_EdmaHandle);
4044 static edma_handle_t LPSPI16_EdmaTxDataToTxRegHandle;
4045 static edma_handle_t LPSPI16_EdmaRxRegToRxDataHandle;
4046
4047 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4048 ARMCC_SECTION("lpspi16_edma_driver_state")
4049 static cmsis_lpspi_edma_driver_state_t LPSPI16_EdmaDriverState = {
4050 #else
4051 static cmsis_lpspi_edma_driver_state_t LPSPI16_EdmaDriverState = {
4052 #endif
4053 &LPSPI16_Resource,
4054 &LPSPI16_EdmaResource,
4055 &LPSPI16_EdmaHandle,
4056 &LPSPI16_EdmaRxRegToRxDataHandle,
4057 &LPSPI16_EdmaTxDataToTxRegHandle,
4058 };
4059
LPSPI16_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)4060 static int32_t LPSPI16_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
4061 {
4062 #ifdef RTE_SPI16_PIN_INIT
4063 RTE_SPI16_PIN_INIT();
4064 #endif
4065 return LPSPI_EdmaInitialize(cb_event, &LPSPI16_EdmaDriverState);
4066 }
4067
LPSPI16_EdmaUninitialize(void)4068 static int32_t LPSPI16_EdmaUninitialize(void)
4069 {
4070 #ifdef RTE_SPI16_PIN_DEINIT
4071 RTE_SPI16_PIN_DEINIT();
4072 #endif
4073 return LPSPI_EdmaUninitialize(&LPSPI16_EdmaDriverState);
4074 }
4075
LPSPI16_EdmaPowerControl(ARM_POWER_STATE state)4076 static int32_t LPSPI16_EdmaPowerControl(ARM_POWER_STATE state)
4077 {
4078 return LPSPI_EdmaPowerControl(state, &LPSPI16_EdmaDriverState);
4079 }
4080
LPSPI16_EdmaSend(const void * data,uint32_t num)4081 static int32_t LPSPI16_EdmaSend(const void *data, uint32_t num)
4082 {
4083 return LPSPI_EdmaSend(data, num, &LPSPI16_EdmaDriverState);
4084 }
4085
LPSPI16_EdmaReceive(void * data,uint32_t num)4086 static int32_t LPSPI16_EdmaReceive(void *data, uint32_t num)
4087 {
4088 return LPSPI_EdmaReceive(data, num, &LPSPI16_EdmaDriverState);
4089 }
4090
LPSPI16_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4091 static int32_t LPSPI16_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4092 {
4093 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI16_EdmaDriverState);
4094 }
4095
LPSPI16_EdmaGetCount(void)4096 static uint32_t LPSPI16_EdmaGetCount(void)
4097 {
4098 return LPSPI_EdmaGetCount(&LPSPI16_EdmaDriverState);
4099 }
4100
LPSPI16_EdmaControl(uint32_t control,uint32_t arg)4101 static int32_t LPSPI16_EdmaControl(uint32_t control, uint32_t arg)
4102 {
4103 return LPSPI_EdmaControl(control, arg, &LPSPI16_EdmaDriverState);
4104 }
4105
LPSPI16_EdmaGetStatus(void)4106 static ARM_SPI_STATUS LPSPI16_EdmaGetStatus(void)
4107 {
4108 return LPSPI_EdmaGetStatus(&LPSPI16_EdmaDriverState);
4109 }
4110
4111 #endif
4112
4113 #else
4114
4115 static cmsis_lpspi_handle_t LPSPI16_Handle;
4116
4117 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4118 ARMCC_SECTION("lpspi16_interrupt_driver_state")
4119 static cmsis_lpspi_interrupt_driver_state_t LPSPI16_InterruptDriverState = {
4120 #else
4121 static cmsis_lpspi_interrupt_driver_state_t LPSPI16_InterruptDriverState = {
4122 #endif
4123 &LPSPI16_Resource,
4124 &LPSPI16_Handle,
4125 };
4126
LPSPI16_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)4127 static int32_t LPSPI16_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
4128 {
4129 #ifdef RTE_SPI16_PIN_INIT
4130 RTE_SPI16_PIN_INIT();
4131 #endif
4132 return LPSPI_InterruptInitialize(cb_event, &LPSPI16_InterruptDriverState);
4133 }
4134
LPSPI16_InterruptUninitialize(void)4135 static int32_t LPSPI16_InterruptUninitialize(void)
4136 {
4137 #ifdef RTE_SPI16_PIN_DEINIT
4138 RTE_SPI16_PIN_DEINIT();
4139 #endif
4140 return LPSPI_InterruptUninitialize(&LPSPI16_InterruptDriverState);
4141 }
4142
LPSPI16_InterruptPowerControl(ARM_POWER_STATE state)4143 static int32_t LPSPI16_InterruptPowerControl(ARM_POWER_STATE state)
4144 {
4145 return LPSPI_InterruptPowerControl(state, &LPSPI16_InterruptDriverState);
4146 }
4147
LPSPI16_InterruptSend(const void * data,uint32_t num)4148 static int32_t LPSPI16_InterruptSend(const void *data, uint32_t num)
4149 {
4150 return LPSPI_InterruptSend(data, num, &LPSPI16_InterruptDriverState);
4151 }
4152
LPSPI16_InterruptReceive(void * data,uint32_t num)4153 static int32_t LPSPI16_InterruptReceive(void *data, uint32_t num)
4154 {
4155 return LPSPI_InterruptReceive(data, num, &LPSPI16_InterruptDriverState);
4156 }
4157
LPSPI16_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)4158 static int32_t LPSPI16_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
4159 {
4160 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI16_InterruptDriverState);
4161 }
4162
LPSPI16_InterruptGetCount(void)4163 static uint32_t LPSPI16_InterruptGetCount(void)
4164 {
4165 return LPSPI_InterruptGetCount(&LPSPI16_InterruptDriverState);
4166 }
4167
LPSPI16_InterruptControl(uint32_t control,uint32_t arg)4168 static int32_t LPSPI16_InterruptControl(uint32_t control, uint32_t arg)
4169 {
4170 return LPSPI_InterruptControl(control, arg, &LPSPI16_InterruptDriverState);
4171 }
4172
LPSPI16_InterruptGetStatus(void)4173 static ARM_SPI_STATUS LPSPI16_InterruptGetStatus(void)
4174 {
4175 return LPSPI_InterruptGetStatus(&LPSPI16_InterruptDriverState);
4176 }
4177
4178 #endif
4179
4180 ARM_DRIVER_SPI Driver_SPI16 = {
4181 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
4182 #if defined(RTE_SPI16_DMA_EN) && RTE_SPI16_DMA_EN
4183 LPSPI16_EdmaInitialize, LPSPI16_EdmaUninitialize, LPSPI16_EdmaPowerControl, LPSPI16_EdmaSend,
4184 LPSPI16_EdmaReceive, LPSPI16_EdmaTransfer, LPSPI16_EdmaGetCount, LPSPI16_EdmaControl,
4185 LPSPI16_EdmaGetStatus
4186 #else
4187 LPSPI16_InterruptInitialize, LPSPI16_InterruptUninitialize, LPSPI16_InterruptPowerControl, LPSPI16_InterruptSend,
4188 LPSPI16_InterruptReceive, LPSPI16_InterruptTransfer, LPSPI16_InterruptGetCount, LPSPI16_InterruptControl,
4189 LPSPI16_InterruptGetStatus
4190 #endif
4191 };
4192
4193 #endif /* LPSPI16 */
4194
4195 #if defined(LPSPI17) && defined(RTE_SPI17) && RTE_SPI17
4196
4197 /* User needs to provide the implementation for LPSPI17_GetFreq/InitPins/DeinitPins
4198 in the application for enabling according instance. */
4199 extern uint32_t LPSPI17_GetFreq(void);
4200
4201 static cmsis_lpspi_resource_t LPSPI17_Resource = {LPSPI17, 17, LPSPI17_GetFreq};
4202
4203 #if defined(RTE_SPI17_DMA_EN) && RTE_SPI17_DMA_EN
4204
4205 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4206 static cmsis_lpspi_edma_resource_t LPSPI17_EdmaResource = {
4207 RTE_SPI17_DMA_TX_DMA_BASE, RTE_SPI17_DMA_TX_CH, (uint16_t)RTE_SPI17_DMA_TX_PERI_SEL,
4208 RTE_SPI17_DMA_RX_DMA_BASE, RTE_SPI17_DMA_RX_CH, (uint16_t)RTE_SPI17_DMA_RX_PERI_SEL,
4209 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4210 RTE_SPI17_DMA_TX_DMAMUX_BASE, RTE_SPI17_DMA_RX_DMAMUX_BASE,
4211 #endif
4212 };
4213
4214 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI17_EdmaHandle);
4215 static edma_handle_t LPSPI17_EdmaTxDataToTxRegHandle;
4216 static edma_handle_t LPSPI17_EdmaRxRegToRxDataHandle;
4217
4218 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4219 ARMCC_SECTION("lpspi17_edma_driver_state")
4220 static cmsis_lpspi_edma_driver_state_t LPSPI17_EdmaDriverState = {
4221 #else
4222 static cmsis_lpspi_edma_driver_state_t LPSPI17_EdmaDriverState = {
4223 #endif
4224 &LPSPI17_Resource,
4225 &LPSPI17_EdmaResource,
4226 &LPSPI17_EdmaHandle,
4227 &LPSPI17_EdmaRxRegToRxDataHandle,
4228 &LPSPI17_EdmaTxDataToTxRegHandle,
4229 };
4230
LPSPI17_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)4231 static int32_t LPSPI17_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
4232 {
4233 #ifdef RTE_SPI17_PIN_INIT
4234 RTE_SPI17_PIN_INIT();
4235 #endif
4236 return LPSPI_EdmaInitialize(cb_event, &LPSPI17_EdmaDriverState);
4237 }
4238
LPSPI17_EdmaUninitialize(void)4239 static int32_t LPSPI17_EdmaUninitialize(void)
4240 {
4241 #ifdef RTE_SPI17_PIN_DEINIT
4242 RTE_SPI17_PIN_DEINIT();
4243 #endif
4244 return LPSPI_EdmaUninitialize(&LPSPI17_EdmaDriverState);
4245 }
4246
LPSPI17_EdmaPowerControl(ARM_POWER_STATE state)4247 static int32_t LPSPI17_EdmaPowerControl(ARM_POWER_STATE state)
4248 {
4249 return LPSPI_EdmaPowerControl(state, &LPSPI17_EdmaDriverState);
4250 }
4251
LPSPI17_EdmaSend(const void * data,uint32_t num)4252 static int32_t LPSPI17_EdmaSend(const void *data, uint32_t num)
4253 {
4254 return LPSPI_EdmaSend(data, num, &LPSPI17_EdmaDriverState);
4255 }
4256
LPSPI17_EdmaReceive(void * data,uint32_t num)4257 static int32_t LPSPI17_EdmaReceive(void *data, uint32_t num)
4258 {
4259 return LPSPI_EdmaReceive(data, num, &LPSPI17_EdmaDriverState);
4260 }
4261
LPSPI17_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4262 static int32_t LPSPI17_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4263 {
4264 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI17_EdmaDriverState);
4265 }
4266
LPSPI17_EdmaGetCount(void)4267 static uint32_t LPSPI17_EdmaGetCount(void)
4268 {
4269 return LPSPI_EdmaGetCount(&LPSPI17_EdmaDriverState);
4270 }
4271
LPSPI17_EdmaControl(uint32_t control,uint32_t arg)4272 static int32_t LPSPI17_EdmaControl(uint32_t control, uint32_t arg)
4273 {
4274 return LPSPI_EdmaControl(control, arg, &LPSPI17_EdmaDriverState);
4275 }
4276
LPSPI17_EdmaGetStatus(void)4277 static ARM_SPI_STATUS LPSPI17_EdmaGetStatus(void)
4278 {
4279 return LPSPI_EdmaGetStatus(&LPSPI17_EdmaDriverState);
4280 }
4281
4282 #endif
4283
4284 #else
4285
4286 static cmsis_lpspi_handle_t LPSPI17_Handle;
4287
4288 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4289 ARMCC_SECTION("lpspi17_interrupt_driver_state")
4290 static cmsis_lpspi_interrupt_driver_state_t LPSPI17_InterruptDriverState = {
4291 #else
4292 static cmsis_lpspi_interrupt_driver_state_t LPSPI17_InterruptDriverState = {
4293 #endif
4294 &LPSPI17_Resource,
4295 &LPSPI17_Handle,
4296 };
4297
LPSPI17_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)4298 static int32_t LPSPI17_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
4299 {
4300 #ifdef RTE_SPI17_PIN_INIT
4301 RTE_SPI17_PIN_INIT();
4302 #endif
4303 return LPSPI_InterruptInitialize(cb_event, &LPSPI17_InterruptDriverState);
4304 }
4305
LPSPI17_InterruptUninitialize(void)4306 static int32_t LPSPI17_InterruptUninitialize(void)
4307 {
4308 #ifdef RTE_SPI17_PIN_DEINIT
4309 RTE_SPI17_PIN_DEINIT();
4310 #endif
4311 return LPSPI_InterruptUninitialize(&LPSPI17_InterruptDriverState);
4312 }
4313
LPSPI17_InterruptPowerControl(ARM_POWER_STATE state)4314 static int32_t LPSPI17_InterruptPowerControl(ARM_POWER_STATE state)
4315 {
4316 return LPSPI_InterruptPowerControl(state, &LPSPI17_InterruptDriverState);
4317 }
4318
LPSPI17_InterruptSend(const void * data,uint32_t num)4319 static int32_t LPSPI17_InterruptSend(const void *data, uint32_t num)
4320 {
4321 return LPSPI_InterruptSend(data, num, &LPSPI17_InterruptDriverState);
4322 }
4323
LPSPI17_InterruptReceive(void * data,uint32_t num)4324 static int32_t LPSPI17_InterruptReceive(void *data, uint32_t num)
4325 {
4326 return LPSPI_InterruptReceive(data, num, &LPSPI17_InterruptDriverState);
4327 }
4328
LPSPI17_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)4329 static int32_t LPSPI17_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
4330 {
4331 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI17_InterruptDriverState);
4332 }
4333
LPSPI17_InterruptGetCount(void)4334 static uint32_t LPSPI17_InterruptGetCount(void)
4335 {
4336 return LPSPI_InterruptGetCount(&LPSPI17_InterruptDriverState);
4337 }
4338
LPSPI17_InterruptControl(uint32_t control,uint32_t arg)4339 static int32_t LPSPI17_InterruptControl(uint32_t control, uint32_t arg)
4340 {
4341 return LPSPI_InterruptControl(control, arg, &LPSPI17_InterruptDriverState);
4342 }
4343
LPSPI17_InterruptGetStatus(void)4344 static ARM_SPI_STATUS LPSPI17_InterruptGetStatus(void)
4345 {
4346 return LPSPI_InterruptGetStatus(&LPSPI17_InterruptDriverState);
4347 }
4348
4349 #endif
4350
4351 ARM_DRIVER_SPI Driver_SPI17 = {
4352 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
4353 #if defined(RTE_SPI17_DMA_EN) && RTE_SPI17_DMA_EN
4354 LPSPI17_EdmaInitialize, LPSPI17_EdmaUninitialize, LPSPI17_EdmaPowerControl, LPSPI17_EdmaSend,
4355 LPSPI17_EdmaReceive, LPSPI17_EdmaTransfer, LPSPI17_EdmaGetCount, LPSPI17_EdmaControl,
4356 LPSPI17_EdmaGetStatus
4357 #else
4358 LPSPI17_InterruptInitialize, LPSPI17_InterruptUninitialize, LPSPI17_InterruptPowerControl, LPSPI17_InterruptSend,
4359 LPSPI17_InterruptReceive, LPSPI17_InterruptTransfer, LPSPI17_InterruptGetCount, LPSPI17_InterruptControl,
4360 LPSPI17_InterruptGetStatus
4361 #endif
4362 };
4363
4364 #endif /* LPSPI17 */
4365
4366 #if defined(LPSPI18) && defined(RTE_SPI18) && RTE_SPI18
4367
4368 /* User needs to provide the implementation for LPSPI18_GetFreq/InitPins/DeinitPins
4369 in the application for enabling according instance. */
4370 extern uint32_t LPSPI18_GetFreq(void);
4371
4372 static cmsis_lpspi_resource_t LPSPI18_Resource = {LPSPI18, 18, LPSPI18_GetFreq};
4373
4374 #if defined(RTE_SPI18_DMA_EN) && RTE_SPI18_DMA_EN
4375
4376 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4377 static cmsis_lpspi_edma_resource_t LPSPI18_EdmaResource = {
4378 RTE_SPI18_DMA_TX_DMA_BASE, RTE_SPI18_DMA_TX_CH, (uint16_t)RTE_SPI18_DMA_TX_PERI_SEL,
4379 RTE_SPI18_DMA_RX_DMA_BASE, RTE_SPI18_DMA_RX_CH, (uint16_t)RTE_SPI18_DMA_RX_PERI_SEL,
4380 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4381 RTE_SPI18_DMA_TX_DMAMUX_BASE, RTE_SPI18_DMA_RX_DMAMUX_BASE,
4382 #endif
4383 };
4384
4385 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI18_EdmaHandle);
4386 static edma_handle_t LPSPI18_EdmaTxDataToTxRegHandle;
4387 static edma_handle_t LPSPI18_EdmaRxRegToRxDataHandle;
4388
4389 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4390 ARMCC_SECTION("lpspi18_edma_driver_state")
4391 static cmsis_lpspi_edma_driver_state_t LPSPI18_EdmaDriverState = {
4392 #else
4393 static cmsis_lpspi_edma_driver_state_t LPSPI18_EdmaDriverState = {
4394 #endif
4395 &LPSPI18_Resource,
4396 &LPSPI18_EdmaResource,
4397 &LPSPI18_EdmaHandle,
4398 &LPSPI18_EdmaRxRegToRxDataHandle,
4399 &LPSPI18_EdmaTxDataToTxRegHandle,
4400 };
4401
LPSPI18_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)4402 static int32_t LPSPI18_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
4403 {
4404 #ifdef RTE_SPI18_PIN_INIT
4405 RTE_SPI18_PIN_INIT();
4406 #endif
4407 return LPSPI_EdmaInitialize(cb_event, &LPSPI18_EdmaDriverState);
4408 }
4409
LPSPI18_EdmaUninitialize(void)4410 static int32_t LPSPI18_EdmaUninitialize(void)
4411 {
4412 #ifdef RTE_SPI18_PIN_DEINIT
4413 RTE_SPI18_PIN_DEINIT();
4414 #endif
4415 return LPSPI_EdmaUninitialize(&LPSPI18_EdmaDriverState);
4416 }
4417
LPSPI18_EdmaPowerControl(ARM_POWER_STATE state)4418 static int32_t LPSPI18_EdmaPowerControl(ARM_POWER_STATE state)
4419 {
4420 return LPSPI_EdmaPowerControl(state, &LPSPI18_EdmaDriverState);
4421 }
4422
LPSPI18_EdmaSend(const void * data,uint32_t num)4423 static int32_t LPSPI18_EdmaSend(const void *data, uint32_t num)
4424 {
4425 return LPSPI_EdmaSend(data, num, &LPSPI18_EdmaDriverState);
4426 }
4427
LPSPI18_EdmaReceive(void * data,uint32_t num)4428 static int32_t LPSPI18_EdmaReceive(void *data, uint32_t num)
4429 {
4430 return LPSPI_EdmaReceive(data, num, &LPSPI18_EdmaDriverState);
4431 }
4432
LPSPI18_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4433 static int32_t LPSPI18_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4434 {
4435 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI18_EdmaDriverState);
4436 }
4437
LPSPI18_EdmaGetCount(void)4438 static uint32_t LPSPI18_EdmaGetCount(void)
4439 {
4440 return LPSPI_EdmaGetCount(&LPSPI18_EdmaDriverState);
4441 }
4442
LPSPI18_EdmaControl(uint32_t control,uint32_t arg)4443 static int32_t LPSPI18_EdmaControl(uint32_t control, uint32_t arg)
4444 {
4445 return LPSPI_EdmaControl(control, arg, &LPSPI18_EdmaDriverState);
4446 }
4447
LPSPI18_EdmaGetStatus(void)4448 static ARM_SPI_STATUS LPSPI18_EdmaGetStatus(void)
4449 {
4450 return LPSPI_EdmaGetStatus(&LPSPI18_EdmaDriverState);
4451 }
4452
4453 #endif
4454
4455 #else
4456
4457 static cmsis_lpspi_handle_t LPSPI18_Handle;
4458
4459 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4460 ARMCC_SECTION("lpspi18_interrupt_driver_state")
4461 static cmsis_lpspi_interrupt_driver_state_t LPSPI18_InterruptDriverState = {
4462 #else
4463 static cmsis_lpspi_interrupt_driver_state_t LPSPI18_InterruptDriverState = {
4464 #endif
4465 &LPSPI18_Resource,
4466 &LPSPI18_Handle,
4467 };
4468
LPSPI18_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)4469 static int32_t LPSPI18_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
4470 {
4471 #ifdef RTE_SPI18_PIN_INIT
4472 RTE_SPI18_PIN_INIT();
4473 #endif
4474 return LPSPI_InterruptInitialize(cb_event, &LPSPI18_InterruptDriverState);
4475 }
4476
LPSPI18_InterruptUninitialize(void)4477 static int32_t LPSPI18_InterruptUninitialize(void)
4478 {
4479 #ifdef RTE_SPI18_PIN_DEINIT
4480 RTE_SPI18_PIN_DEINIT();
4481 #endif
4482 return LPSPI_InterruptUninitialize(&LPSPI18_InterruptDriverState);
4483 }
4484
LPSPI18_InterruptPowerControl(ARM_POWER_STATE state)4485 static int32_t LPSPI18_InterruptPowerControl(ARM_POWER_STATE state)
4486 {
4487 return LPSPI_InterruptPowerControl(state, &LPSPI18_InterruptDriverState);
4488 }
4489
LPSPI18_InterruptSend(const void * data,uint32_t num)4490 static int32_t LPSPI18_InterruptSend(const void *data, uint32_t num)
4491 {
4492 return LPSPI_InterruptSend(data, num, &LPSPI18_InterruptDriverState);
4493 }
4494
LPSPI18_InterruptReceive(void * data,uint32_t num)4495 static int32_t LPSPI18_InterruptReceive(void *data, uint32_t num)
4496 {
4497 return LPSPI_InterruptReceive(data, num, &LPSPI18_InterruptDriverState);
4498 }
4499
LPSPI18_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)4500 static int32_t LPSPI18_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
4501 {
4502 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI18_InterruptDriverState);
4503 }
4504
LPSPI18_InterruptGetCount(void)4505 static uint32_t LPSPI18_InterruptGetCount(void)
4506 {
4507 return LPSPI_InterruptGetCount(&LPSPI18_InterruptDriverState);
4508 }
4509
LPSPI18_InterruptControl(uint32_t control,uint32_t arg)4510 static int32_t LPSPI18_InterruptControl(uint32_t control, uint32_t arg)
4511 {
4512 return LPSPI_InterruptControl(control, arg, &LPSPI18_InterruptDriverState);
4513 }
4514
LPSPI18_InterruptGetStatus(void)4515 static ARM_SPI_STATUS LPSPI18_InterruptGetStatus(void)
4516 {
4517 return LPSPI_InterruptGetStatus(&LPSPI18_InterruptDriverState);
4518 }
4519
4520 #endif
4521
4522 ARM_DRIVER_SPI Driver_SPI18 = {
4523 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
4524 #if defined(RTE_SPI18_DMA_EN) && RTE_SPI18_DMA_EN
4525 LPSPI18_EdmaInitialize, LPSPI18_EdmaUninitialize, LPSPI18_EdmaPowerControl, LPSPI18_EdmaSend,
4526 LPSPI18_EdmaReceive, LPSPI18_EdmaTransfer, LPSPI18_EdmaGetCount, LPSPI18_EdmaControl,
4527 LPSPI18_EdmaGetStatus
4528 #else
4529 LPSPI18_InterruptInitialize, LPSPI18_InterruptUninitialize, LPSPI18_InterruptPowerControl, LPSPI18_InterruptSend,
4530 LPSPI18_InterruptReceive, LPSPI18_InterruptTransfer, LPSPI18_InterruptGetCount, LPSPI18_InterruptControl,
4531 LPSPI18_InterruptGetStatus
4532 #endif
4533 };
4534
4535 #endif /* LPSPI18 */
4536
4537 #if defined(LPSPI19) && defined(RTE_SPI19) && RTE_SPI19
4538
4539 /* User needs to provide the implementation for LPSPI19_GetFreq/InitPins/DeinitPins
4540 in the application for enabling according instance. */
4541 extern uint32_t LPSPI19_GetFreq(void);
4542
4543 static cmsis_lpspi_resource_t LPSPI19_Resource = {LPSPI19, 19, LPSPI19_GetFreq};
4544
4545 #if defined(RTE_SPI19_DMA_EN) && RTE_SPI19_DMA_EN
4546
4547 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4548 static cmsis_lpspi_edma_resource_t LPSPI19_EdmaResource = {
4549 RTE_SPI19_DMA_TX_DMA_BASE, RTE_SPI19_DMA_TX_CH, (uint16_t)RTE_SPI19_DMA_TX_PERI_SEL,
4550 RTE_SPI19_DMA_RX_DMA_BASE, RTE_SPI19_DMA_RX_CH, (uint16_t)RTE_SPI19_DMA_RX_PERI_SEL,
4551 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4552 RTE_SPI19_DMA_TX_DMAMUX_BASE, RTE_SPI19_DMA_RX_DMAMUX_BASE,
4553 #endif
4554 };
4555
4556 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI19_EdmaHandle);
4557 static edma_handle_t LPSPI19_EdmaTxDataToTxRegHandle;
4558 static edma_handle_t LPSPI19_EdmaRxRegToRxDataHandle;
4559
4560 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4561 ARMCC_SECTION("lpspi19_edma_driver_state")
4562 static cmsis_lpspi_edma_driver_state_t LPSPI19_EdmaDriverState = {
4563 #else
4564 static cmsis_lpspi_edma_driver_state_t LPSPI19_EdmaDriverState = {
4565 #endif
4566 &LPSPI19_Resource,
4567 &LPSPI19_EdmaResource,
4568 &LPSPI19_EdmaHandle,
4569 &LPSPI19_EdmaRxRegToRxDataHandle,
4570 &LPSPI19_EdmaTxDataToTxRegHandle,
4571 };
4572
LPSPI19_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)4573 static int32_t LPSPI19_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
4574 {
4575 #ifdef RTE_SPI19_PIN_INIT
4576 RTE_SPI19_PIN_INIT();
4577 #endif
4578 return LPSPI_EdmaInitialize(cb_event, &LPSPI19_EdmaDriverState);
4579 }
4580
LPSPI19_EdmaUninitialize(void)4581 static int32_t LPSPI19_EdmaUninitialize(void)
4582 {
4583 #ifdef RTE_SPI19_PIN_DEINIT
4584 RTE_SPI19_PIN_DEINIT();
4585 #endif
4586 return LPSPI_EdmaUninitialize(&LPSPI19_EdmaDriverState);
4587 }
4588
LPSPI19_EdmaPowerControl(ARM_POWER_STATE state)4589 static int32_t LPSPI19_EdmaPowerControl(ARM_POWER_STATE state)
4590 {
4591 return LPSPI_EdmaPowerControl(state, &LPSPI19_EdmaDriverState);
4592 }
4593
LPSPI19_EdmaSend(const void * data,uint32_t num)4594 static int32_t LPSPI19_EdmaSend(const void *data, uint32_t num)
4595 {
4596 return LPSPI_EdmaSend(data, num, &LPSPI19_EdmaDriverState);
4597 }
4598
LPSPI19_EdmaReceive(void * data,uint32_t num)4599 static int32_t LPSPI19_EdmaReceive(void *data, uint32_t num)
4600 {
4601 return LPSPI_EdmaReceive(data, num, &LPSPI19_EdmaDriverState);
4602 }
4603
LPSPI19_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4604 static int32_t LPSPI19_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4605 {
4606 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI19_EdmaDriverState);
4607 }
4608
LPSPI19_EdmaGetCount(void)4609 static uint32_t LPSPI19_EdmaGetCount(void)
4610 {
4611 return LPSPI_EdmaGetCount(&LPSPI19_EdmaDriverState);
4612 }
4613
LPSPI19_EdmaControl(uint32_t control,uint32_t arg)4614 static int32_t LPSPI19_EdmaControl(uint32_t control, uint32_t arg)
4615 {
4616 return LPSPI_EdmaControl(control, arg, &LPSPI19_EdmaDriverState);
4617 }
4618
LPSPI19_EdmaGetStatus(void)4619 static ARM_SPI_STATUS LPSPI19_EdmaGetStatus(void)
4620 {
4621 return LPSPI_EdmaGetStatus(&LPSPI19_EdmaDriverState);
4622 }
4623
4624 #endif
4625
4626 #else
4627
4628 static cmsis_lpspi_handle_t LPSPI19_Handle;
4629
4630 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4631 ARMCC_SECTION("lpspi19_interrupt_driver_state")
4632 static cmsis_lpspi_interrupt_driver_state_t LPSPI19_InterruptDriverState = {
4633 #else
4634 static cmsis_lpspi_interrupt_driver_state_t LPSPI19_InterruptDriverState = {
4635 #endif
4636 &LPSPI19_Resource,
4637 &LPSPI19_Handle,
4638 };
4639
LPSPI19_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)4640 static int32_t LPSPI19_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
4641 {
4642 #ifdef RTE_SPI19_PIN_INIT
4643 RTE_SPI19_PIN_INIT();
4644 #endif
4645 return LPSPI_InterruptInitialize(cb_event, &LPSPI19_InterruptDriverState);
4646 }
4647
LPSPI19_InterruptUninitialize(void)4648 static int32_t LPSPI19_InterruptUninitialize(void)
4649 {
4650 #ifdef RTE_SPI19_PIN_DEINIT
4651 RTE_SPI19_PIN_DEINIT();
4652 #endif
4653 return LPSPI_InterruptUninitialize(&LPSPI19_InterruptDriverState);
4654 }
4655
LPSPI19_InterruptPowerControl(ARM_POWER_STATE state)4656 static int32_t LPSPI19_InterruptPowerControl(ARM_POWER_STATE state)
4657 {
4658 return LPSPI_InterruptPowerControl(state, &LPSPI19_InterruptDriverState);
4659 }
4660
LPSPI19_InterruptSend(const void * data,uint32_t num)4661 static int32_t LPSPI19_InterruptSend(const void *data, uint32_t num)
4662 {
4663 return LPSPI_InterruptSend(data, num, &LPSPI19_InterruptDriverState);
4664 }
4665
LPSPI19_InterruptReceive(void * data,uint32_t num)4666 static int32_t LPSPI19_InterruptReceive(void *data, uint32_t num)
4667 {
4668 return LPSPI_InterruptReceive(data, num, &LPSPI19_InterruptDriverState);
4669 }
4670
LPSPI19_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)4671 static int32_t LPSPI19_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
4672 {
4673 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI19_InterruptDriverState);
4674 }
4675
LPSPI19_InterruptGetCount(void)4676 static uint32_t LPSPI19_InterruptGetCount(void)
4677 {
4678 return LPSPI_InterruptGetCount(&LPSPI19_InterruptDriverState);
4679 }
4680
LPSPI19_InterruptControl(uint32_t control,uint32_t arg)4681 static int32_t LPSPI19_InterruptControl(uint32_t control, uint32_t arg)
4682 {
4683 return LPSPI_InterruptControl(control, arg, &LPSPI19_InterruptDriverState);
4684 }
4685
LPSPI19_InterruptGetStatus(void)4686 static ARM_SPI_STATUS LPSPI19_InterruptGetStatus(void)
4687 {
4688 return LPSPI_InterruptGetStatus(&LPSPI19_InterruptDriverState);
4689 }
4690
4691 #endif
4692
4693 ARM_DRIVER_SPI Driver_SPI19 = {
4694 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
4695 #if defined(RTE_SPI19_DMA_EN) && RTE_SPI19_DMA_EN
4696 LPSPI19_EdmaInitialize, LPSPI19_EdmaUninitialize, LPSPI19_EdmaPowerControl, LPSPI19_EdmaSend,
4697 LPSPI19_EdmaReceive, LPSPI19_EdmaTransfer, LPSPI19_EdmaGetCount, LPSPI19_EdmaControl,
4698 LPSPI19_EdmaGetStatus
4699 #else
4700 LPSPI19_InterruptInitialize, LPSPI19_InterruptUninitialize, LPSPI19_InterruptPowerControl, LPSPI19_InterruptSend,
4701 LPSPI19_InterruptReceive, LPSPI19_InterruptTransfer, LPSPI19_InterruptGetCount, LPSPI19_InterruptControl,
4702 LPSPI19_InterruptGetStatus
4703 #endif
4704 };
4705
4706 #endif /* LPSPI19 */
4707
4708 #if defined(LPSPI20) && defined(RTE_SPI20) && RTE_SPI20
4709
4710 /* User needs to provide the implementation for LPSPI20_GetFreq/InitPins/DeinitPins
4711 in the application for enabling according instance. */
4712 extern uint32_t LPSPI20_GetFreq(void);
4713
4714 static cmsis_lpspi_resource_t LPSPI20_Resource = {LPSPI20, 20, LPSPI20_GetFreq};
4715
4716 #if defined(RTE_SPI20_DMA_EN) && RTE_SPI20_DMA_EN
4717
4718 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
4719 static cmsis_lpspi_edma_resource_t LPSPI20_EdmaResource = {
4720 RTE_SPI20_DMA_TX_DMA_BASE, RTE_SPI20_DMA_TX_CH, (uint16_t)RTE_SPI20_DMA_TX_PERI_SEL,
4721 RTE_SPI20_DMA_RX_DMA_BASE, RTE_SPI20_DMA_RX_CH, (uint16_t)RTE_SPI20_DMA_RX_PERI_SEL,
4722 #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
4723 RTE_SPI20_DMA_TX_DMAMUX_BASE, RTE_SPI20_DMA_RX_DMAMUX_BASE,
4724 #endif
4725 };
4726
4727 AT_NONCACHEABLE_SECTION(static cmsis_lpspi_edma_handle_t LPSPI20_EdmaHandle);
4728 static edma_handle_t LPSPI20_EdmaTxDataToTxRegHandle;
4729 static edma_handle_t LPSPI20_EdmaRxRegToRxDataHandle;
4730
4731 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4732 ARMCC_SECTION("lpspi20_edma_driver_state")
4733 static cmsis_lpspi_edma_driver_state_t LPSPI20_EdmaDriverState = {
4734 #else
4735 static cmsis_lpspi_edma_driver_state_t LPSPI20_EdmaDriverState = {
4736 #endif
4737 &LPSPI20_Resource,
4738 &LPSPI20_EdmaResource,
4739 &LPSPI20_EdmaHandle,
4740 &LPSPI20_EdmaRxRegToRxDataHandle,
4741 &LPSPI20_EdmaTxDataToTxRegHandle,
4742 };
4743
LPSPI20_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)4744 static int32_t LPSPI20_EdmaInitialize(ARM_SPI_SignalEvent_t cb_event)
4745 {
4746 #ifdef RTE_SPI20_PIN_INIT
4747 RTE_SPI20_PIN_INIT();
4748 #endif
4749 return LPSPI_EdmaInitialize(cb_event, &LPSPI20_EdmaDriverState);
4750 }
4751
LPSPI20_EdmaUninitialize(void)4752 static int32_t LPSPI20_EdmaUninitialize(void)
4753 {
4754 #ifdef RTE_SPI20_PIN_DEINIT
4755 RTE_SPI20_PIN_DEINIT();
4756 #endif
4757 return LPSPI_EdmaUninitialize(&LPSPI20_EdmaDriverState);
4758 }
4759
LPSPI20_EdmaPowerControl(ARM_POWER_STATE state)4760 static int32_t LPSPI20_EdmaPowerControl(ARM_POWER_STATE state)
4761 {
4762 return LPSPI_EdmaPowerControl(state, &LPSPI20_EdmaDriverState);
4763 }
4764
LPSPI20_EdmaSend(const void * data,uint32_t num)4765 static int32_t LPSPI20_EdmaSend(const void *data, uint32_t num)
4766 {
4767 return LPSPI_EdmaSend(data, num, &LPSPI20_EdmaDriverState);
4768 }
4769
LPSPI20_EdmaReceive(void * data,uint32_t num)4770 static int32_t LPSPI20_EdmaReceive(void *data, uint32_t num)
4771 {
4772 return LPSPI_EdmaReceive(data, num, &LPSPI20_EdmaDriverState);
4773 }
4774
LPSPI20_EdmaTransfer(const void * data_out,void * data_in,uint32_t num)4775 static int32_t LPSPI20_EdmaTransfer(const void *data_out, void *data_in, uint32_t num)
4776 {
4777 return LPSPI_EdmaTransfer(data_out, data_in, num, &LPSPI20_EdmaDriverState);
4778 }
4779
LPSPI20_EdmaGetCount(void)4780 static uint32_t LPSPI20_EdmaGetCount(void)
4781 {
4782 return LPSPI_EdmaGetCount(&LPSPI20_EdmaDriverState);
4783 }
4784
LPSPI20_EdmaControl(uint32_t control,uint32_t arg)4785 static int32_t LPSPI20_EdmaControl(uint32_t control, uint32_t arg)
4786 {
4787 return LPSPI_EdmaControl(control, arg, &LPSPI20_EdmaDriverState);
4788 }
4789
LPSPI20_EdmaGetStatus(void)4790 static ARM_SPI_STATUS LPSPI20_EdmaGetStatus(void)
4791 {
4792 return LPSPI_EdmaGetStatus(&LPSPI20_EdmaDriverState);
4793 }
4794
4795 #endif
4796
4797 #else
4798
4799 static cmsis_lpspi_handle_t LPSPI20_Handle;
4800
4801 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
4802 ARMCC_SECTION("lpspi20_interrupt_driver_state")
4803 static cmsis_lpspi_interrupt_driver_state_t LPSPI20_InterruptDriverState = {
4804 #else
4805 static cmsis_lpspi_interrupt_driver_state_t LPSPI20_InterruptDriverState = {
4806 #endif
4807 &LPSPI20_Resource,
4808 &LPSPI20_Handle,
4809 };
4810
LPSPI20_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)4811 static int32_t LPSPI20_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
4812 {
4813 #ifdef RTE_SPI20_PIN_INIT
4814 RTE_SPI20_PIN_INIT();
4815 #endif
4816 return LPSPI_InterruptInitialize(cb_event, &LPSPI20_InterruptDriverState);
4817 }
4818
LPSPI20_InterruptUninitialize(void)4819 static int32_t LPSPI20_InterruptUninitialize(void)
4820 {
4821 #ifdef RTE_SPI20_PIN_DEINIT
4822 RTE_SPI20_PIN_DEINIT();
4823 #endif
4824 return LPSPI_InterruptUninitialize(&LPSPI20_InterruptDriverState);
4825 }
4826
LPSPI20_InterruptPowerControl(ARM_POWER_STATE state)4827 static int32_t LPSPI20_InterruptPowerControl(ARM_POWER_STATE state)
4828 {
4829 return LPSPI_InterruptPowerControl(state, &LPSPI20_InterruptDriverState);
4830 }
4831
LPSPI20_InterruptSend(const void * data,uint32_t num)4832 static int32_t LPSPI20_InterruptSend(const void *data, uint32_t num)
4833 {
4834 return LPSPI_InterruptSend(data, num, &LPSPI20_InterruptDriverState);
4835 }
4836
LPSPI20_InterruptReceive(void * data,uint32_t num)4837 static int32_t LPSPI20_InterruptReceive(void *data, uint32_t num)
4838 {
4839 return LPSPI_InterruptReceive(data, num, &LPSPI20_InterruptDriverState);
4840 }
4841
LPSPI20_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)4842 static int32_t LPSPI20_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
4843 {
4844 return LPSPI_InterruptTransfer(data_out, data_in, num, &LPSPI20_InterruptDriverState);
4845 }
4846
LPSPI20_InterruptGetCount(void)4847 static uint32_t LPSPI20_InterruptGetCount(void)
4848 {
4849 return LPSPI_InterruptGetCount(&LPSPI20_InterruptDriverState);
4850 }
4851
LPSPI20_InterruptControl(uint32_t control,uint32_t arg)4852 static int32_t LPSPI20_InterruptControl(uint32_t control, uint32_t arg)
4853 {
4854 return LPSPI_InterruptControl(control, arg, &LPSPI20_InterruptDriverState);
4855 }
4856
LPSPI20_InterruptGetStatus(void)4857 static ARM_SPI_STATUS LPSPI20_InterruptGetStatus(void)
4858 {
4859 return LPSPI_InterruptGetStatus(&LPSPI20_InterruptDriverState);
4860 }
4861
4862 #endif
4863
4864 ARM_DRIVER_SPI Driver_SPI20 = {
4865 LPSPIx_GetVersion, LPSPIx_GetCapabilities,
4866 #if defined(RTE_SPI20_DMA_EN) && RTE_SPI20_DMA_EN
4867 LPSPI20_EdmaInitialize, LPSPI20_EdmaUninitialize, LPSPI20_EdmaPowerControl, LPSPI20_EdmaSend,
4868 LPSPI20_EdmaReceive, LPSPI20_EdmaTransfer, LPSPI20_EdmaGetCount, LPSPI20_EdmaControl,
4869 LPSPI20_EdmaGetStatus
4870 #else
4871 LPSPI20_InterruptInitialize, LPSPI20_InterruptUninitialize, LPSPI20_InterruptPowerControl, LPSPI20_InterruptSend,
4872 LPSPI20_InterruptReceive, LPSPI20_InterruptTransfer, LPSPI20_InterruptGetCount, LPSPI20_InterruptControl,
4873 LPSPI20_InterruptGetStatus
4874 #endif
4875 };
4876
4877 #endif /* LPSPI20 */
4878
