1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2020 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_i2c_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.ii2c_cmsis"
26 #endif
27
28 #if ((defined(RTE_I2C0) && RTE_I2C0 && defined(I2C0)) || (defined(RTE_I2C1) && RTE_I2C1 && defined(I2C1)) || \
29 (defined(RTE_I2C2) && RTE_I2C2 && defined(I2C2)) || (defined(RTE_I2C3) && RTE_I2C3 && defined(I2C3)) || \
30 (defined(RTE_I2C4) && RTE_I2C4 && defined(I2C4)))
31
32 #define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (2))
33
34 /*
35 * ARMCC does not support split the data section automatically, so the driver
36 * needs to split the data to separate sections explicitly, to reduce codesize.
37 */
38 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
39 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
40 #endif
41
42 typedef const struct _cmsis_i2c_resource
43 {
44 I2C_Type *base; /*!< I2C peripheral base address. */
45 uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */
46
47 } cmsis_i2c_resource_t;
48
49 typedef union _cmsis_i2c_handle
50 {
51 i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */
52 i2c_slave_handle_t slave_handle; /*!< slave Interupt transfer handle. */
53 } cmsis_i2c_handle_t;
54
55 typedef struct _cmsis_i2c_interrupt_driver_state
56 {
57 cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */
58 cmsis_i2c_handle_t *handle;
59 ARM_I2C_SignalEvent_t cb_event; /*!< Callback function. */
60 uint8_t flags; /*!< Control and state flags. */
61 } cmsis_i2c_interrupt_driver_state_t;
62
63 static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION};
64 static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = {
65 0, /*< supports 10-bit addressing */
66 };
67
I2Cx_GetVersion(void)68 static ARM_DRIVER_VERSION I2Cx_GetVersion(void)
69 {
70 return s_i2cDriverVersion;
71 }
72
I2Cx_GetCapabilities(void)73 static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void)
74 {
75 return s_i2cDriverCapabilities;
76 }
77
78 #endif
79
80 #if ((defined(RTE_I2C0) && RTE_I2C0 && !(defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN)) || \
81 (defined(RTE_I2C1) && RTE_I2C1 && !(defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN)) || \
82 (defined(RTE_I2C2) && RTE_I2C2 && !(defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN)) || \
83 (defined(RTE_I2C3) && RTE_I2C3 && !(defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN)) || \
84 (defined(RTE_I2C4) && RTE_I2C4 && !(defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN)))
85
KSDK_I2C_SLAVE_InterruptCallback(I2C_Type * base,i2c_slave_transfer_t * xfer,void * userData)86 static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData)
87 {
88 uint32_t event = 0;
89
90 switch (xfer->event)
91 {
92 case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */
93 event = ARM_I2C_EVENT_TRANSFER_DONE;
94 break;
95
96 default:
97 event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
98 break;
99 }
100
101 if (userData != NULL)
102 {
103 ((ARM_I2C_SignalEvent_t)userData)(event);
104 }
105 }
106
KSDK_I2C_MASTER_InterruptCallback(I2C_Type * base,i2c_master_handle_t * handle,status_t status,void * userData)107 static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base,
108 i2c_master_handle_t *handle,
109 status_t status,
110 void *userData)
111 {
112 uint32_t event = 0;
113
114 switch (status)
115 {
116 case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */
117 event = ARM_I2C_EVENT_TRANSFER_DONE;
118 break;
119
120 case kStatus_I2C_Addr_Nak: /* Occurs in master mode when address is not acknowledged from slave.*/
121 event = ARM_I2C_EVENT_ADDRESS_NACK;
122 break;
123
124 case kStatus_I2C_ArbitrationLost: /* Occurs in master mode when arbitration is lost.*/
125 event = ARM_I2C_EVENT_ARBITRATION_LOST;
126 break;
127
128 default:
129 event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
130 break;
131 }
132
133 /* User data is actually CMSIS driver callback. */
134 if (userData != NULL)
135 {
136 ((ARM_I2C_SignalEvent_t)userData)(event);
137 }
138 }
139
I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event,cmsis_i2c_interrupt_driver_state_t * i2c)140 static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c)
141 {
142 if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT))
143 {
144 i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */
145 i2c->flags = (uint8_t)I2C_FLAG_INIT;
146 }
147
148 return ARM_DRIVER_OK;
149 }
150
I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t * i2c)151 static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c)
152 {
153 i2c->flags = (uint8_t)I2C_FLAG_UNINIT;
154 return ARM_DRIVER_OK;
155 }
156
I2C_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending,cmsis_i2c_interrupt_driver_state_t * i2c)157 static int32_t I2C_Master_InterruptTransmit(
158 uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c)
159 {
160 int32_t status;
161 int32_t ret;
162 i2c_master_transfer_t masterXfer;
163
164 /* Check if the I2C bus is idle - if not return busy status. */
165 if (i2c->handle->master_handle.state != 0U)
166 {
167 return ARM_DRIVER_ERROR_BUSY;
168 }
169
170 /* Create master_handle */
171 I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle),
172 KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event);
173
174 masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/
175 masterXfer.direction = kI2C_Write; /* Transfer direction.*/
176 masterXfer.subaddress = 0U; /* Sub address */
177 masterXfer.subaddressSize = 0U; /* Size of command buffer.*/
178 masterXfer.data = (uint8_t *)data; /* Transfer buffer.*/
179 masterXfer.dataSize = num; /* Transfer size.*/
180 masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/
181
182 if ((i2c->resource->base->I2SR & 0x20U) != 0U)
183 {
184 masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag;
185 }
186
187 if (xfer_pending)
188 {
189 masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
190 }
191
192 status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer);
193
194 switch (status)
195 {
196 case kStatus_Success:
197 ret = ARM_DRIVER_OK;
198 break;
199
200 case kStatus_I2C_Busy:
201 ret = ARM_DRIVER_ERROR_BUSY;
202 break;
203
204 case kStatus_I2C_Timeout:
205 ret = ARM_DRIVER_ERROR_TIMEOUT;
206 break;
207
208 default:
209 ret = ARM_DRIVER_ERROR;
210 break;
211 }
212
213 return ret;
214 }
215
I2C_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending,cmsis_i2c_interrupt_driver_state_t * i2c)216 static int32_t I2C_Master_InterruptReceive(
217 uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c)
218 {
219 int32_t status;
220 int32_t ret;
221 i2c_master_transfer_t masterXfer;
222
223 /* Check if the I2C bus is idle - if not return busy status. */
224 if (i2c->handle->master_handle.state != 0U)
225 {
226 return ARM_DRIVER_ERROR_BUSY;
227 }
228
229 /* Create master_handle */
230 I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle),
231 KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event);
232
233 masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/
234 masterXfer.direction = kI2C_Read; /* Transfer direction.*/
235 masterXfer.subaddress = 0U; /* Sub address */
236 masterXfer.subaddressSize = 0U; /* Size of command buffer.*/
237 masterXfer.data = data; /* Transfer buffer.*/
238 masterXfer.dataSize = num; /* Transfer size.*/
239 masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /* Transfer flag which controls the transfer.*/
240
241 if ((i2c->resource->base->I2SR & 0x20U) != 0U)
242 {
243 masterXfer.flags |= (uint32_t)kI2C_TransferRepeatedStartFlag;
244 }
245
246 if (xfer_pending)
247 {
248 masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag;
249 }
250
251 status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer);
252
253 switch (status)
254 {
255 case kStatus_Success:
256 ret = ARM_DRIVER_OK;
257 break;
258
259 case kStatus_I2C_Busy:
260 ret = ARM_DRIVER_ERROR_BUSY;
261 break;
262
263 case kStatus_I2C_Timeout:
264 ret = ARM_DRIVER_ERROR_TIMEOUT;
265 break;
266
267 default:
268 ret = ARM_DRIVER_ERROR;
269 break;
270 }
271
272 return ret;
273 }
274
I2C_Slave_InterruptTransmit(const uint8_t * data,uint32_t num,cmsis_i2c_interrupt_driver_state_t * i2c)275 static int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c)
276 {
277 int32_t status;
278 int32_t ret;
279
280 /* Create slave_handle */
281 I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback,
282 (void *)i2c->cb_event);
283
284 status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle),
285 (uint32_t)kI2C_SlaveCompletionEvent);
286
287 i2c->handle->slave_handle.transfer.data =
288 (uint8_t *)data; /* Pointer to buffer with data to transmit to I2C Master */
289 i2c->handle->slave_handle.transfer.dataSize = num; /* Number of data bytes to transmit */
290 i2c->handle->slave_handle.transfer.transferredCount =
291 0; /* Number of bytes actually transferred since start or last repeated start. */
292
293 switch (status)
294 {
295 case kStatus_Success:
296 ret = ARM_DRIVER_OK;
297 break;
298
299 case kStatus_I2C_Busy:
300 ret = ARM_DRIVER_ERROR_BUSY;
301 break;
302
303 default:
304 ret = ARM_DRIVER_ERROR;
305 break;
306 }
307
308 return ret;
309 }
310
I2C_Slave_InterruptReceive(uint8_t * data,uint32_t num,cmsis_i2c_interrupt_driver_state_t * i2c)311 static int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c)
312 {
313 int32_t status;
314 int32_t ret;
315
316 /* Create slave_handle */
317 I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback,
318 (void *)i2c->cb_event);
319
320 status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle),
321 (uint32_t)kI2C_SlaveCompletionEvent);
322
323 i2c->handle->slave_handle.transfer.data = data; /* Pointer to buffer with data to transmit to I2C Master */
324 i2c->handle->slave_handle.transfer.dataSize = num; /* Number of data bytes to transmit */
325 i2c->handle->slave_handle.transfer.transferredCount =
326 0; /* Number of bytes actually transferred since start or last repeated start. */
327
328 switch (status)
329 {
330 case kStatus_Success:
331 ret = ARM_DRIVER_OK;
332 break;
333
334 case kStatus_I2C_Busy:
335 ret = ARM_DRIVER_ERROR_BUSY;
336 break;
337
338 default:
339 ret = ARM_DRIVER_ERROR;
340 break;
341 }
342
343 return ret;
344 }
345
I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t * i2c)346 static int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c)
347 {
348 uint32_t cnt; /* The number of currently transferred data bytes */
349
350 if (i2c->handle->slave_handle.transfer.transferredCount != 0U)
351 {
352 cnt = i2c->handle->slave_handle.transfer.transferredCount;
353 }
354 else
355 {
356 cnt = (uint32_t) & (i2c->handle->master_handle).transferSize - (uint32_t) &
357 (i2c->handle->master_handle).transfer.dataSize;
358 }
359
360 return (int32_t)cnt;
361 }
362
I2C_InterruptControl(uint32_t control,uint32_t arg,cmsis_i2c_interrupt_driver_state_t * i2c)363 static int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c)
364 {
365 uint32_t baudRate_Bps = 0;
366 int32_t result = ARM_DRIVER_OK;
367 switch (control)
368 {
369 /* Set Own Slave Address; arg = slave address */
370 case ARM_I2C_OWN_ADDRESS:
371 i2c->resource->base->IADR = (uint16_t)(arg << 1U);
372 break;
373
374 /* Set Bus Speed; arg = bus speed */
375 case ARM_I2C_BUS_SPEED:
376 switch (arg)
377 {
378 case ARM_I2C_BUS_SPEED_STANDARD:
379 baudRate_Bps = 100000;
380 break;
381
382 case ARM_I2C_BUS_SPEED_FAST:
383 baudRate_Bps = 400000;
384 break;
385
386 case ARM_I2C_BUS_SPEED_FAST_PLUS:
387 baudRate_Bps = 1000000;
388 break;
389
390 default:
391 result = ARM_DRIVER_ERROR_UNSUPPORTED;
392 break;
393 }
394
395 I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq());
396 break;
397
398 /* Not supported */
399 case ARM_I2C_BUS_CLEAR:
400 result = ARM_DRIVER_ERROR_UNSUPPORTED;
401 break;
402
403 /* Aborts the data transfer between Master and Slave for Transmit or Receive */
404 case ARM_I2C_ABORT_TRANSFER:
405 if (0U == (i2c->resource->base->IADR))
406 {
407 /* Disable master interrupt and send STOP signal */
408 (void)I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle));
409
410 i2c->handle->master_handle.transferSize = 0;
411 i2c->handle->master_handle.transfer.data = NULL;
412 i2c->handle->master_handle.transfer.dataSize = 0;
413 }
414 /* If slave receive */
415 else if (0U == (i2c->resource->base->I2SR & (uint32_t)kI2C_TransferDirectionFlag))
416 {
417 i2c->resource->base->I2CR |= (uint8_t)I2C_I2CR_TXAK_MASK;
418
419 while (i2c->handle->slave_handle.state != 0U)
420 {
421 }
422 /* Disable slave interrupt */
423
424 I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle));
425
426 i2c->handle->slave_handle.transfer.data = NULL;
427 i2c->handle->slave_handle.transfer.dataSize = 0;
428 }
429 else
430 {
431 /* Avoid MISRA 15.7 violation */
432 }
433 break;
434 default:
435 result = ARM_DRIVER_ERROR_UNSUPPORTED;
436 break;
437 }
438 return result;
439 }
440
I2C_InterruptPowerControl(ARM_POWER_STATE state,cmsis_i2c_interrupt_driver_state_t * i2c)441 static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c)
442 {
443 i2c_master_config_t masterConfig;
444 i2c_slave_config_t slaveConfig;
445 int32_t result = ARM_DRIVER_OK;
446 switch (state)
447 {
448 /* Terminates any pending data transfers, disable i2c moduole and i2c clock */
449 case ARM_POWER_OFF:
450 if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
451 {
452 (void)I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c);
453
454 I2C_MasterDeinit(i2c->resource->base);
455
456 i2c->flags = (uint8_t)I2C_FLAG_INIT;
457 }
458 break;
459 /* Not supported */
460 case ARM_POWER_LOW:
461 result = ARM_DRIVER_ERROR_UNSUPPORTED;
462 break;
463
464 /* Enable i2c moduole and i2c clock */
465 case ARM_POWER_FULL:
466 if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT)
467 {
468 return ARM_DRIVER_ERROR;
469 }
470
471 if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U)
472 {
473 /* Driver already powered */
474 break;
475 }
476
477 I2C_MasterGetDefaultConfig(&masterConfig);
478 I2C_MasterInit(i2c->resource->base, &masterConfig, i2c->resource->GetFreq());
479
480 I2C_SlaveGetDefaultConfig(&slaveConfig);
481 I2C_SlaveInit(i2c->resource->base, &slaveConfig);
482
483 i2c->flags |= (uint8_t)I2C_FLAG_POWER;
484 break;
485
486 default:
487 result = ARM_DRIVER_ERROR_UNSUPPORTED;
488 break;
489 }
490
491 return result;
492 }
493
I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t * i2c)494 static ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c)
495 {
496 ARM_I2C_STATUS stat = {0};
497 uint32_t ksdk_i2c_status = I2C_SlaveGetStatusFlags(i2c->resource->base);
498 uint32_t dataSize;
499
500 if (0U == (i2c->resource->base->IADR))
501 {
502 dataSize = i2c->handle->master_handle.transfer.dataSize;
503 stat.direction = (uint32_t)((ksdk_i2c_status & (uint32_t)kI2C_TransferDirectionFlag) !=
504 0U); /* Direction: 0=Transmitter, 1=Receiver.*/
505 stat.mode = 1UL; /* Mode: 0=Slave, 1=Master.*/
506 }
507 else
508 {
509 dataSize = i2c->handle->slave_handle.transfer.dataSize;
510 stat.direction = (uint32_t)((ksdk_i2c_status & (uint32_t)kI2C_TransferDirectionFlag) !=
511 0U); /* Direction: 0=Transmitter, 1=Receiver.*/
512 stat.mode = 0; /* Mode: 0=Slave, 1=Master.*/
513 }
514
515 if (dataSize != 0U)
516 {
517 stat.busy = 1; /* Busy flag.*/
518 }
519 else
520 {
521 stat.busy = 0; /* Busy flag.*/
522 }
523
524 stat.arbitration_lost = (uint32_t)((ksdk_i2c_status & (uint32_t)kI2C_ArbitrationLostFlag) !=
525 0U); /* Master lost arbitration (cleared on start of next Master operation)*/
526
527 return stat;
528 }
529
530 #endif
531
532 #if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0
533 /* User needs to provide the implementation for I2C0_GetFreq/InitPins/DeinitPins
534 in the application for enabling according instance. */
535 extern uint32_t I2C0_GetFreq(void);
536
537 static cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq};
538
539 static cmsis_i2c_handle_t I2C0_handle;
540
541 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
542 ARMCC_SECTION("i2c0_interrupt_driver_state")
543 static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = {
544 #else
545 static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = {
546 #endif
547 &I2C0_Resource,
548 &I2C0_handle,
549
550 };
551
I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)552 static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
553 {
554 #ifdef RTE_I2C0_PIN_INIT
555 RTE_I2C0_PIN_INIT();
556 #endif
557 return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState);
558 }
559
I2C0_InterruptUninitialize(void)560 static int32_t I2C0_InterruptUninitialize(void)
561 {
562 #ifdef RTE_I2C0_PIN_DEINIT
563 RTE_I2C0_PIN_DEINIT();
564 #endif
565 return I2C_InterruptUninitialize(&I2C0_InterruptDriverState);
566 }
567
I2C0_InterruptPowerControl(ARM_POWER_STATE state)568 static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state)
569 {
570 return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState);
571 }
572
I2C0_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)573 static int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
574 {
575 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState);
576 }
577
I2C0_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)578 static int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
579 {
580 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState);
581 }
582
I2C0_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)583 static int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
584 {
585 return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState);
586 }
587
I2C0_Slave_InterruptReceive(uint8_t * data,uint32_t num)588 static int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num)
589 {
590 return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState);
591 }
592
I2C0_InterruptGetDataCount(void)593 static int32_t I2C0_InterruptGetDataCount(void)
594 {
595 return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState);
596 }
597
I2C0_InterruptControl(uint32_t control,uint32_t arg)598 static int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg)
599 {
600 return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState);
601 }
602
I2C0_InterruptGetStatus(void)603 static ARM_I2C_STATUS I2C0_InterruptGetStatus(void)
604 {
605 return I2C_InterruptGetStatus(&I2C0_InterruptDriverState);
606 }
607
608 ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion,
609 I2Cx_GetCapabilities,
610 I2C0_InterruptInitialize,
611 I2C0_InterruptUninitialize,
612 I2C0_InterruptPowerControl,
613 I2C0_Master_InterruptTransmit,
614 I2C0_Master_InterruptReceive,
615 I2C0_Slave_InterruptTransmit,
616 I2C0_Slave_InterruptReceive,
617 I2C0_InterruptGetDataCount,
618 I2C0_InterruptControl,
619 I2C0_InterruptGetStatus};
620
621 #endif
622
623 #if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1
624
625 /* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins
626 in the application for enabling according instance. */
627 extern uint32_t I2C1_GetFreq(void);
628
629 static cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq};
630 static cmsis_i2c_handle_t I2C1_Handle;
631
632 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
633 ARMCC_SECTION("i2c1_interrupt_driver_state")
634 static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = {
635 #else
636 static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = {
637 #endif
638 &I2C1_Resource,
639 &I2C1_Handle,
640 };
641
I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)642 static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
643 {
644 #ifdef RTE_I2C1_PIN_INIT
645 RTE_I2C1_PIN_INIT();
646 #endif
647 return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState);
648 }
649
I2C1_InterruptUninitialize(void)650 static int32_t I2C1_InterruptUninitialize(void)
651 {
652 #ifdef RTE_I2C1_PIN_DEINIT
653 RTE_I2C1_PIN_DEINIT();
654 #endif
655 return I2C_InterruptUninitialize(&I2C1_InterruptDriverState);
656 }
657
I2C1_InterruptPowerControl(ARM_POWER_STATE state)658 static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state)
659 {
660 return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState);
661 }
662
I2C1_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)663 static int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
664 {
665 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState);
666 }
667
I2C1_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)668 static int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
669 {
670 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState);
671 }
672
I2C1_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)673 static int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
674 {
675 return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState);
676 }
677
I2C1_Slave_InterruptReceive(uint8_t * data,uint32_t num)678 static int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num)
679 {
680 return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState);
681 }
682
I2C1_InterruptGetDataCount(void)683 static int32_t I2C1_InterruptGetDataCount(void)
684 {
685 return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState);
686 }
687
I2C1_InterruptControl(uint32_t control,uint32_t arg)688 static int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg)
689 {
690 return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState);
691 }
692
I2C1_InterruptGetStatus(void)693 static ARM_I2C_STATUS I2C1_InterruptGetStatus(void)
694 {
695 return I2C_InterruptGetStatus(&I2C1_InterruptDriverState);
696 }
697
698 ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion,
699 I2Cx_GetCapabilities,
700 I2C1_InterruptInitialize,
701 I2C1_InterruptUninitialize,
702 I2C1_InterruptPowerControl,
703 I2C1_Master_InterruptTransmit,
704 I2C1_Master_InterruptReceive,
705 I2C1_Slave_InterruptTransmit,
706 I2C1_Slave_InterruptReceive,
707 I2C1_InterruptGetDataCount,
708 I2C1_InterruptControl,
709 I2C1_InterruptGetStatus};
710
711 #endif
712
713 #if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2
714
715 /* User needs to provide the implementation for I2C2_GetFreq/InitPins/DeinitPins
716 in the application for enabling according instance. */
717 extern uint32_t I2C2_GetFreq(void);
718
719 static cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq};
720
721 static cmsis_i2c_handle_t I2C2_Handle;
722
723 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
724 ARMCC_SECTION("i2c2_interrupt_driver_state")
725 static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = {
726 #else
727 static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = {
728 #endif
729 &I2C2_Resource,
730 &I2C2_Handle,
731
732 };
733
I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)734 static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
735 {
736 #ifdef RTE_I2C2_PIN_INIT
737 RTE_I2C2_PIN_INIT();
738 #endif
739 return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState);
740 }
741
I2C2_InterruptUninitialize(void)742 static int32_t I2C2_InterruptUninitialize(void)
743 {
744 #ifdef RTE_I2C2_PIN_DEINIT
745 RTE_I2C2_PIN_DEINIT();
746 #endif
747 return I2C_InterruptUninitialize(&I2C2_InterruptDriverState);
748 }
749
I2C2_InterruptPowerControl(ARM_POWER_STATE state)750 static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state)
751 {
752 return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState);
753 }
754
I2C2_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)755 static int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
756 {
757 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState);
758 }
759
I2C2_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)760 static int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
761 {
762 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState);
763 }
764
I2C2_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)765 static int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
766 {
767 return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState);
768 }
769
I2C2_Slave_InterruptReceive(uint8_t * data,uint32_t num)770 static int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num)
771 {
772 return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState);
773 }
774
I2C2_InterruptGetDataCount(void)775 static int32_t I2C2_InterruptGetDataCount(void)
776 {
777 return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState);
778 }
779
I2C2_InterruptControl(uint32_t control,uint32_t arg)780 static int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg)
781 {
782 return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState);
783 }
784
I2C2_InterruptGetStatus(void)785 static ARM_I2C_STATUS I2C2_InterruptGetStatus(void)
786 {
787 return I2C_InterruptGetStatus(&I2C2_InterruptDriverState);
788 }
789
790 ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion,
791 I2Cx_GetCapabilities,
792 I2C2_InterruptInitialize,
793 I2C2_InterruptUninitialize,
794 I2C2_InterruptPowerControl,
795 I2C2_Master_InterruptTransmit,
796 I2C2_Master_InterruptReceive,
797 I2C2_Slave_InterruptTransmit,
798 I2C2_Slave_InterruptReceive,
799 I2C2_InterruptGetDataCount,
800 I2C2_InterruptControl,
801 I2C2_InterruptGetStatus};
802
803 #endif
804
805 #if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3
806
807 /* User needs to provide the implementation for I2C3_GetFreq/InitPins/DeinitPins
808 in the application for enabling according instance. */
809 extern uint32_t I2C3_GetFreq(void);
810
811 static cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq};
812 static cmsis_i2c_handle_t I2C3_Handle;
813
814 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
815 ARMCC_SECTION("i2c3_interrupt_driver_state")
816 static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = {
817 #else
818 static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = {
819 #endif
820 &I2C3_Resource,
821 &I2C3_Handle,
822 };
823
I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)824 static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
825 {
826 #ifdef RTE_I2C3_PIN_INIT
827 RTE_I2C3_PIN_INIT();
828 #endif
829 return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState);
830 }
831
I2C3_InterruptUninitialize(void)832 static int32_t I2C3_InterruptUninitialize(void)
833 {
834 #ifdef RTE_I2C3_PIN_DEINIT
835 RTE_I2C3_PIN_DEINIT();
836 #endif
837 return I2C_InterruptUninitialize(&I2C3_InterruptDriverState);
838 }
839
I2C3_InterruptPowerControl(ARM_POWER_STATE state)840 static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state)
841 {
842 return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState);
843 }
844
I2C3_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)845 static int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
846 {
847 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState);
848 }
849
I2C3_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)850 static int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
851 {
852 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState);
853 }
854
I2C3_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)855 static int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
856 {
857 return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState);
858 }
859
I2C3_Slave_InterruptReceive(uint8_t * data,uint32_t num)860 static int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num)
861 {
862 return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState);
863 }
864
I2C3_InterruptGetDataCount(void)865 static int32_t I2C3_InterruptGetDataCount(void)
866 {
867 return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState);
868 }
869
I2C3_InterruptControl(uint32_t control,uint32_t arg)870 static int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg)
871 {
872 return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState);
873 }
874
I2C3_InterruptGetStatus(void)875 static ARM_I2C_STATUS I2C3_InterruptGetStatus(void)
876 {
877 return I2C_InterruptGetStatus(&I2C3_InterruptDriverState);
878 }
879
880 ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion,
881 I2Cx_GetCapabilities,
882 I2C3_InterruptInitialize,
883 I2C3_InterruptUninitialize,
884 I2C3_InterruptPowerControl,
885 I2C3_Master_InterruptTransmit,
886 I2C3_Master_InterruptReceive,
887 I2C3_Slave_InterruptTransmit,
888 I2C3_Slave_InterruptReceive,
889 I2C3_InterruptGetDataCount,
890 I2C3_InterruptControl,
891 I2C3_InterruptGetStatus};
892
893 #endif
894
895 #if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4
896
897 /* User needs to provide the implementation for I2C4_GetFreq/InitPins/DeinitPins
898 in the application for enabling according instance. */
899 extern uint32_t I2C4_GetFreq(void);
900
901 static cmsis_i2c_resource_t I2C4_Resource = {I2C4, I2C4_GetFreq};
902 static cmsis_i2c_handle_t I2C4_Handle;
903
904 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
905 ARMCC_SECTION("i2c3_interrupt_driver_state")
906 static cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = {
907 #else
908 static cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = {
909 #endif
910 &I2C4_Resource,
911 &I2C4_Handle,
912 };
913
I2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)914 static int32_t I2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event)
915 {
916 #ifdef RTE_I2C4_PIN_INIT
917 RTE_I2C4_PIN_INIT();
918 #endif
919 return I2C_InterruptInitialize(cb_event, &I2C4_InterruptDriverState);
920 }
921
I2C4_InterruptUninitialize(void)922 static int32_t I2C4_InterruptUninitialize(void)
923 {
924 #ifdef RTE_I2C4_PIN_DEINIT
925 RTE_I2C4_PIN_DEINIT();
926 #endif
927 return I2C_InterruptUninitialize(&I2C4_InterruptDriverState);
928 }
929
I2C4_InterruptPowerControl(ARM_POWER_STATE state)930 static int32_t I2C4_InterruptPowerControl(ARM_POWER_STATE state)
931 {
932 return I2C_InterruptPowerControl(state, &I2C4_InterruptDriverState);
933 }
934
I2C4_Master_InterruptTransmit(uint32_t addr,const uint8_t * data,uint32_t num,bool xfer_pending)935 static int32_t I2C4_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
936 {
937 return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C4_InterruptDriverState);
938 }
939
I2C4_Master_InterruptReceive(uint32_t addr,uint8_t * data,uint32_t num,bool xfer_pending)940 static int32_t I2C4_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
941 {
942 return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C4_InterruptDriverState);
943 }
944
I2C4_Slave_InterruptTransmit(const uint8_t * data,uint32_t num)945 static int32_t I2C4_Slave_InterruptTransmit(const uint8_t *data, uint32_t num)
946 {
947 return I2C_Slave_InterruptTransmit(data, num, &I2C4_InterruptDriverState);
948 }
949
I2C4_Slave_InterruptReceive(uint8_t * data,uint32_t num)950 static int32_t I2C4_Slave_InterruptReceive(uint8_t *data, uint32_t num)
951 {
952 return I2C_Slave_InterruptReceive(data, num, &I2C4_InterruptDriverState);
953 }
954
I2C4_InterruptGetDataCount(void)955 static int32_t I2C4_InterruptGetDataCount(void)
956 {
957 return I2C_InterruptGetDataCount(&I2C4_InterruptDriverState);
958 }
959
I2C4_InterruptControl(uint32_t control,uint32_t arg)960 static int32_t I2C4_InterruptControl(uint32_t control, uint32_t arg)
961 {
962 return I2C_InterruptControl(control, arg, &I2C4_InterruptDriverState);
963 }
964
I2C4_InterruptGetStatus(void)965 static ARM_I2C_STATUS I2C4_InterruptGetStatus(void)
966 {
967 return I2C_InterruptGetStatus(&I2C4_InterruptDriverState);
968 }
969
970 ARM_DRIVER_I2C Driver_I2C4 = {I2Cx_GetVersion,
971 I2Cx_GetCapabilities,
972 I2C4_InterruptInitialize,
973 I2C4_InterruptUninitialize,
974 I2C4_InterruptPowerControl,
975 I2C4_Master_InterruptTransmit,
976 I2C4_Master_InterruptReceive,
977 I2C4_Slave_InterruptTransmit,
978 I2C4_Slave_InterruptReceive,
979 I2C4_InterruptGetDataCount,
980 I2C4_InterruptControl,
981 I2C4_InterruptGetStatus};
982
983 #endif
984
