1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2020 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_spi_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_cmsis"
26 #endif
27
28 #if ((defined(RTE_SPI0) && RTE_SPI0) || (defined(RTE_SPI1) && RTE_SPI1) || (defined(RTE_SPI2) && RTE_SPI2) || \
29 (defined(RTE_SPI3) && RTE_SPI3) || (defined(RTE_SPI4) && RTE_SPI4) || (defined(RTE_SPI5) && RTE_SPI5) || \
30 (defined(RTE_SPI6) && RTE_SPI6) || (defined(RTE_SPI7) && RTE_SPI7) || (defined(RTE_SPI8) && RTE_SPI8) || \
31 (defined(RTE_SPI9) && RTE_SPI9) || (defined(RTE_SPI10) && RTE_SPI10) || (defined(RTE_SPI11) && RTE_SPI11) || \
32 (defined(RTE_SPI12) && RTE_SPI12) || (defined(RTE_SPI13) && RTE_SPI13))
33
34 #define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 5) /* driver version */
35
36 /*! @brief IDs of clock for each FLEXCOMM module */
37 static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
38 /*
39 * ARMCC does not support split the data section automatically, so the driver
40 * needs to split the data to separate sections explicitly, to reduce codesize.
41 */
42 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
43 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
44 #endif
45
46 typedef const struct _cmsis_spi_resource
47 {
48 SPI_Type *base;
49 uint32_t instance;
50 uint32_t (*GetFreq)(void);
51 } cmsis_spi_resource_t;
52
53 typedef union _cmsis_spi_handle
54 {
55 spi_master_handle_t masterHandle;
56 spi_slave_handle_t slaveHandle;
57 } cmsis_spi_handle_t;
58
59 typedef struct _cmsis_spi_interrupt_driver_state
60 {
61 cmsis_spi_resource_t *resource;
62 cmsis_spi_handle_t *handle;
63 ARM_SPI_SignalEvent_t cb_event;
64 uint32_t baudRate_Bps;
65 uint8_t flags; /*!< Control and state flags. */
66 } cmsis_spi_interrupt_driver_state_t;
67
68 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
69
70 typedef const struct _cmsis_spi_dma_resource
71 {
72 DMA_Type *txdmaBase;
73 uint32_t txdmaChannel;
74
75 DMA_Type *rxdmaBase;
76 uint32_t rxdmaChannel;
77 } cmsis_spi_dma_resource_t;
78
79 typedef union _cmsis_spi_dma_handle
80 {
81 spi_dma_handle_t masterHandle;
82 spi_dma_handle_t slaveHandle;
83 } cmsis_spi_dma_handle_t;
84
85 typedef struct _cmsis_spi_dma_driver_state
86 {
87 cmsis_spi_resource_t *resource;
88 cmsis_spi_dma_resource_t *dmaResource;
89 cmsis_spi_dma_handle_t *handle;
90 dma_handle_t *dmaRxDataHandle;
91 dma_handle_t *dmaTxDataHandle;
92
93 uint32_t baudRate_Bps;
94 ARM_SPI_SignalEvent_t cb_event;
95 uint8_t flags; /*!< Control and state flags. */
96 } cmsis_spi_dma_driver_state_t;
97 #endif
98
99 /* Driver Version */
100 static const ARM_DRIVER_VERSION s_SPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION};
101
102 /* Driver Capabilities */
103 static const ARM_SPI_CAPABILITIES s_SPIDriverCapabilities = {
104 1, /* Simplex Mode (Master and Slave) */
105 0, /* TI Synchronous Serial Interface */
106 0, /* Microwire Interface */
107 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
108 };
109
110 /*******************************************************************************
111 * Code
112 ******************************************************************************/
113
SPI_MasterCommonControl(uint32_t control,cmsis_spi_resource_t * resource,uint8_t * status,spi_master_config_t * masterConfig)114 static void SPI_MasterCommonControl(uint32_t control,
115 cmsis_spi_resource_t *resource,
116 uint8_t *status,
117 spi_master_config_t *masterConfig)
118 {
119 switch (resource->instance)
120 {
121 case 0:
122 #if defined(RTE_SPI0_SSEL_NUM)
123 masterConfig->sselNum = RTE_SPI0_SSEL_NUM;
124 #endif
125 #if defined(RTE_SPI0_SSEL_POL)
126 masterConfig->sselPol = RTE_SPI0_SSEL_POL;
127 #endif
128 break;
129
130 case 1:
131 #if defined(RTE_SPI1_SSEL_NUM)
132 masterConfig->sselNum = RTE_SPI1_SSEL_NUM;
133 #endif
134 #if defined(RTE_SPI1_SSEL_POL)
135 masterConfig->sselPol = RTE_SPI1_SSEL_POL;
136 #endif
137 break;
138 case 2:
139 #if defined(RTE_SPI2_SSEL_NUM)
140 masterConfig->sselNum = RTE_SPI2_SSEL_NUM;
141 #endif
142 #if defined(RTE_SPI2_SSEL_POL)
143 masterConfig->sselPol = RTE_SPI2_SSEL_POL;
144 #endif
145 break;
146
147 case 3:
148 #if defined(RTE_SPI3_SSEL_NUM)
149 masterConfig->sselNum = RTE_SPI3_SSEL_NUM;
150 #endif
151 #if defined(RTE_SPI3_SSEL_POL)
152 masterConfig->sselPol = RTE_SPI3_SSEL_POL;
153 #endif
154 break;
155
156 case 4:
157 #if defined(RTE_SPI4_SSEL_NUM)
158 masterConfig->sselNum = RTE_SPI4_SSEL_NUM;
159 #endif
160 #if defined(RTE_SPI4_SSEL_POL)
161 masterConfig->sselPol = RTE_SPI4_SSEL_POL;
162 #endif
163 break;
164
165 case 5:
166 #if defined(RTE_SPI5_SSEL_NUM)
167 masterConfig->sselNum = RTE_SPI5_SSEL_NUM;
168 #endif
169 #if defined(RTE_SPI5_SSEL_POL)
170 masterConfig->sselPol = RTE_SPI5_SSEL_POL;
171 #endif
172 break;
173
174 case 6:
175 #if defined(RTE_SPI6_SSEL_NUM)
176 masterConfig->sselNum = RTE_SPI6_SSEL_NUM;
177 #endif
178 #if defined(RTE_SPI6_SSEL_POL)
179 masterConfig->sselPol = RTE_SPI6_SSEL_POL;
180 #endif
181 break;
182
183 case 7:
184 #if defined(RTE_SPI7_SSEL_NUM)
185 masterConfig->sselNum = RTE_SPI7_SSEL_NUM;
186 #endif
187 #if defined(RTE_SPI7_SSEL_POL)
188 masterConfig->sselPol = RTE_SPI7_SSEL_POL;
189 #endif
190 break;
191
192 case 8:
193 #if defined(RTE_SPI8_SSEL_NUM)
194 masterConfig->sselNum = RTE_SPI8_SSEL_NUM;
195 #endif
196 #if defined(RTE_SPI8_SSEL_POL)
197 masterConfig->sselPol = RTE_SPI8_SSEL_POL;
198 #endif
199 break;
200
201 case 9:
202 #if defined(RTE_SPI9_SSEL_NUM)
203 masterConfig->sselNum = RTE_SPI9_SSEL_NUM;
204 #endif
205 #if defined(RTE_SPI9_SSEL_POL)
206 masterConfig->sselPol = RTE_SPI9_SSEL_POL;
207 #endif
208 break;
209
210 case 10:
211 #if defined(RTE_SPI10_SSEL_NUM)
212 masterConfig->sselNum = RTE_SPI10_SSEL_NUM;
213 #endif
214 #if defined(RTE_SPI10_SSEL_POL)
215 masterConfig->sselPol = RTE_SPI10_SSEL_POL;
216 #endif
217 break;
218
219 case 11:
220 #if defined(RTE_SPI11_SSEL_NUM)
221 masterConfig->sselNum = RTE_SPI11_SSEL_NUM;
222 #endif
223 #if defined(RTE_SPI11_SSEL_POL)
224 masterConfig->sselPol = RTE_SPI11_SSEL_POL;
225 #endif
226 break;
227
228 case 12:
229 #if defined(RTE_SPI12_SSEL_NUM)
230 masterConfig->sselNum = RTE_SPI12_SSEL_NUM;
231 #endif
232 #if defined(RTE_SPI12_SSEL_POL)
233 masterConfig->sselPol = RTE_SPI12_SSEL_POL;
234 #endif
235 break;
236
237 case 13:
238 #if defined(RTE_SPI13_SSEL_NUM)
239 masterConfig->sselNum = RTE_SPI13_SSEL_NUM;
240 #endif
241 #if defined(RTE_SPI13_SSEL_POL)
242 masterConfig->sselPol = RTE_SPI13_SSEL_POL;
243 #endif
244 break;
245
246 default:
247 /* Avoid MISRA 16.4 violation */
248 break;
249 }
250
251 switch (control & ARM_SPI_FRAME_FORMAT_Msk)
252 {
253 case ARM_SPI_CPOL0_CPHA0:
254 masterConfig->polarity = kSPI_ClockPolarityActiveHigh;
255 masterConfig->phase = kSPI_ClockPhaseFirstEdge;
256 break;
257
258 case ARM_SPI_CPOL0_CPHA1:
259 masterConfig->polarity = kSPI_ClockPolarityActiveHigh;
260 masterConfig->phase = kSPI_ClockPhaseSecondEdge;
261 break;
262
263 case ARM_SPI_CPOL1_CPHA0:
264 masterConfig->polarity = kSPI_ClockPolarityActiveLow;
265 masterConfig->phase = kSPI_ClockPhaseFirstEdge;
266 break;
267
268 case ARM_SPI_CPOL1_CPHA1:
269 masterConfig->polarity = kSPI_ClockPolarityActiveLow;
270 masterConfig->phase = kSPI_ClockPhaseSecondEdge;
271 break;
272
273 default:
274 /* Avoid MISRA 16.4 violation */
275 break;
276 }
277
278 if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */
279 {
280 if ((((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4U) &&
281 (((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16U))
282 {
283 masterConfig->dataWidth =
284 (spi_data_width_t)(((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1U);
285 }
286 }
287
288 switch (control & ARM_SPI_BIT_ORDER_Msk)
289 {
290 case ARM_SPI_LSB_MSB:
291 masterConfig->direction = kSPI_LsbFirst;
292 break;
293 case ARM_SPI_MSB_LSB:
294 masterConfig->direction = kSPI_MsbFirst;
295 break;
296
297 default:
298 /* Avoid MISRA 16.4 violation */
299 break;
300 }
301 }
302
SPI_SlaveCommonControl(uint32_t control,cmsis_spi_resource_t * resource,uint8_t * status,spi_slave_config_t * slaveConfig)303 static void SPI_SlaveCommonControl(uint32_t control,
304 cmsis_spi_resource_t *resource,
305 uint8_t *status,
306 spi_slave_config_t *slaveConfig)
307 {
308 switch (resource->instance)
309 {
310 case 0:
311 #if defined(RTE_SPI0_SSEL_POL)
312 slaveConfig->sselPol = RTE_SPI0_SSEL_POL;
313 #endif
314 break;
315
316 case 1:
317 #if defined(RTE_SPI1_SSEL_POL)
318 slaveConfig->sselPol = RTE_SPI1_SSEL_POL;
319 #endif
320 break;
321 case 2:
322 #if defined(RTE_SPI2_SSEL_POL)
323 slaveConfig->sselPol = RTE_SPI2_SSEL_POL;
324 #endif
325 break;
326
327 case 3:
328 #if defined(RTE_SPI3_SSEL_POL)
329 slaveConfig->sselPol = RTE_SPI3_SSEL_POL;
330 #endif
331 break;
332
333 case 4:
334 #if defined(RTE_SPI4_SSEL_POL)
335 slaveConfig->sselPol = RTE_SPI4_SSEL_POL;
336 #endif
337 break;
338
339 case 5:
340 #if defined(RTE_SPI5_SSEL_POL)
341 slaveConfig->sselPol = RTE_SPI5_SSEL_POL;
342 #endif
343 break;
344
345 case 6:
346 #if defined(RTE_SPI6_SSEL_POL)
347 slaveConfig->sselPol = RTE_SPI6_SSEL_POL;
348 #endif
349 break;
350
351 case 7:
352 #if defined(RTE_SPI7_SSEL_POL)
353 slaveConfig->sselPol = RTE_SPI7_SSEL_POL;
354 #endif
355 break;
356
357 case 8:
358 #if defined(RTE_SPI8_SSEL_POL)
359 slaveConfig->sselPol = RTE_SPI8_SSEL_POL;
360 #endif
361 break;
362
363 case 9:
364 #if defined(RTE_SPI9_SSEL_POL)
365 slaveConfig->sselPol = RTE_SPI9_SSEL_POL;
366 #endif
367 break;
368
369 case 10:
370 #if defined(RTE_SPI10_SSEL_POL)
371 slaveConfig->sselPol = RTE_SPI10_SSEL_POL;
372 #endif
373 break;
374
375 case 11:
376 #if defined(RTE_SPI11_SSEL_POL)
377 slaveConfig->sselPol = RTE_SPI11_SSEL_POL;
378 #endif
379 break;
380
381 case 12:
382 #if defined(RTE_SPI12_SSEL_POL)
383 slaveConfig->sselPol = RTE_SPI12_SSEL_POL;
384 #endif
385 break;
386
387 case 13:
388 #if defined(RTE_SPI13_SSEL_POL)
389 slaveConfig->sselPol = RTE_SPI13_SSEL_POL;
390 #endif
391 break;
392
393 default:
394 /* Avoid MISRA 16.4 violation */
395 break;
396 }
397
398 switch (control & ARM_SPI_FRAME_FORMAT_Msk)
399 {
400 case ARM_SPI_CPOL0_CPHA0:
401 slaveConfig->polarity = kSPI_ClockPolarityActiveHigh;
402 slaveConfig->phase = kSPI_ClockPhaseFirstEdge;
403 break;
404
405 case ARM_SPI_CPOL0_CPHA1:
406 slaveConfig->polarity = kSPI_ClockPolarityActiveHigh;
407 slaveConfig->phase = kSPI_ClockPhaseSecondEdge;
408 break;
409
410 case ARM_SPI_CPOL1_CPHA0:
411 slaveConfig->polarity = kSPI_ClockPolarityActiveLow;
412 slaveConfig->phase = kSPI_ClockPhaseFirstEdge;
413 break;
414
415 case ARM_SPI_CPOL1_CPHA1:
416 slaveConfig->polarity = kSPI_ClockPolarityActiveLow;
417 slaveConfig->phase = kSPI_ClockPhaseSecondEdge;
418 break;
419
420 default:
421 /* Avoid MISRA 16.4 violation */
422 break;
423 }
424 if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */
425 {
426 if ((((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4U) &&
427 (((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16U))
428 {
429 slaveConfig->dataWidth =
430 (spi_data_width_t)(((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1U);
431 }
432 }
433 switch (control & ARM_SPI_BIT_ORDER_Msk)
434 {
435 case ARM_SPI_LSB_MSB:
436 slaveConfig->direction = kSPI_LsbFirst;
437 break;
438 case ARM_SPI_MSB_LSB:
439 slaveConfig->direction = kSPI_MsbFirst;
440 break;
441
442 default:
443 /* Avoid MISRA 16.4 violation */
444 break;
445 }
446 }
447
SPIx_GetVersion(void)448 static ARM_DRIVER_VERSION SPIx_GetVersion(void)
449 {
450 return s_SPIDriverVersion;
451 }
452
SPIx_GetCapabilities(void)453 static ARM_SPI_CAPABILITIES SPIx_GetCapabilities(void)
454 {
455 return s_SPIDriverCapabilities;
456 }
457
458 #endif
459
460 #if ((defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN) || (defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || \
461 (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN) || \
462 (defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN) || (defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN) || \
463 (defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN) || (defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN) || \
464 (defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN) || (defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN) || \
465 (defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN) || (defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN) || \
466 (defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN) || (defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN))
467
468 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
469
KSDK_SPI_MasterDMACallback(SPI_Type * base,spi_dma_handle_t * handle,status_t status,void * userData)470 static void KSDK_SPI_MasterDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
471 {
472 uint32_t event = 0;
473
474 if (kStatus_Success == status)
475 {
476 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
477 }
478
479 if (kStatus_SPI_Error == status)
480 {
481 event = ARM_SPI_EVENT_DATA_LOST;
482 }
483
484 if (userData != NULL)
485 {
486 ((ARM_SPI_SignalEvent_t)userData)(event);
487 }
488 }
KSDK_SPI_SlaveDMACallback(SPI_Type * base,spi_dma_handle_t * handle,status_t status,void * userData)489 static void KSDK_SPI_SlaveDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
490 {
491 uint32_t event = 0;
492
493 if (kStatus_Success == status)
494 {
495 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
496 }
497
498 if (kStatus_SPI_Error == status)
499 {
500 event = ARM_SPI_EVENT_DATA_LOST;
501 }
502 /* User data is actually CMSIS driver callback. */
503 if (userData != NULL)
504 {
505 ((ARM_SPI_SignalEvent_t)userData)(event);
506 }
507 }
508
SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_spi_dma_driver_state_t * spi)509 static int32_t SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_dma_driver_state_t *spi)
510 {
511 if (0U == (spi->flags & (uint8_t)SPI_FLAG_INIT))
512 {
513 spi->cb_event = cb_event;
514 spi->flags = (uint8_t)SPI_FLAG_INIT;
515 }
516
517 return ARM_DRIVER_OK;
518 }
519
SPI_DMAUninitialize(cmsis_spi_dma_driver_state_t * spi)520 static int32_t SPI_DMAUninitialize(cmsis_spi_dma_driver_state_t *spi)
521 {
522 spi->flags = (uint8_t)SPI_FLAG_UNINIT;
523 return ARM_DRIVER_OK;
524 }
525
SPI_DMAPowerControl(ARM_POWER_STATE state,cmsis_spi_dma_driver_state_t * spi)526 static int32_t SPI_DMAPowerControl(ARM_POWER_STATE state, cmsis_spi_dma_driver_state_t *spi)
527 {
528 int32_t result = ARM_DRIVER_OK;
529 switch (state)
530 {
531 case ARM_POWER_OFF:
532 if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
533 {
534 SPI_Deinit(spi->resource->base);
535
536 DMA_DisableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
537 DMA_DisableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
538 DMA_Deinit(spi->dmaResource->txdmaBase);
539 DMA_Deinit(spi->dmaResource->rxdmaBase);
540
541 spi->flags = (uint8_t)SPI_FLAG_INIT;
542 }
543 break;
544 case ARM_POWER_LOW:
545 result = ARM_DRIVER_ERROR_UNSUPPORTED;
546 break;
547
548 case ARM_POWER_FULL:
549 if (spi->flags == (uint8_t)SPI_FLAG_UNINIT)
550 {
551 return ARM_DRIVER_ERROR;
552 }
553
554 if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
555 {
556 /* Driver already powered */
557 break;
558 }
559
560 /* Enable flexcomm clock gate */
561 CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]);
562 spi->flags |= (uint8_t)SPI_FLAG_POWER;
563 break;
564 default:
565 /* Avoid MISRA 16.4 violation */
566 break;
567 }
568 return result;
569 }
570
SPI_DMASend(const void * data,uint32_t num,cmsis_spi_dma_driver_state_t * spi)571 static int32_t SPI_DMASend(const void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi)
572 {
573 int32_t ret;
574 status_t status;
575 spi_transfer_t xfer = {0};
576 spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base);
577
578 xfer.rxData = NULL;
579 xfer.txData = (uint8_t *)data;
580 xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL);
581 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
582 {
583 xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
584 }
585
586 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
587 {
588 status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer);
589 }
590 else
591 {
592 status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer);
593 }
594
595 switch (status)
596 {
597 case kStatus_Success:
598 ret = ARM_DRIVER_OK;
599 break;
600 case kStatus_InvalidArgument:
601 ret = ARM_DRIVER_ERROR_PARAMETER;
602 break;
603 case kStatus_SPI_Busy:
604 ret = ARM_DRIVER_ERROR_BUSY;
605 break;
606 default:
607 ret = ARM_DRIVER_ERROR;
608 break;
609 }
610
611 return ret;
612 }
613
SPI_DMAReceive(void * data,uint32_t num,cmsis_spi_dma_driver_state_t * spi)614 static int32_t SPI_DMAReceive(void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi)
615 {
616 int32_t ret;
617 status_t status;
618 spi_transfer_t xfer = {0};
619 spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base);
620
621 xfer.txData = NULL;
622 xfer.rxData = (uint8_t *)data;
623 xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL);
624 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
625 {
626 xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
627 }
628
629 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
630 {
631 status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer);
632 }
633 else
634 {
635 status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer);
636 }
637
638 switch (status)
639 {
640 case kStatus_Success:
641 ret = ARM_DRIVER_OK;
642 break;
643 case kStatus_InvalidArgument:
644 ret = ARM_DRIVER_ERROR_PARAMETER;
645 break;
646 case kStatus_SPI_Busy:
647 ret = ARM_DRIVER_ERROR_BUSY;
648 break;
649 default:
650 ret = ARM_DRIVER_ERROR;
651 break;
652 }
653
654 return ret;
655 }
656
SPI_DMATransfer(const void * data_out,void * data_in,uint32_t num,cmsis_spi_dma_driver_state_t * spi)657 static int32_t SPI_DMATransfer(const void *data_out, void *data_in, uint32_t num, cmsis_spi_dma_driver_state_t *spi)
658 {
659 int32_t ret;
660 status_t status;
661 spi_transfer_t xfer = {0};
662 spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base);
663
664 xfer.txData = (uint8_t *)data_out;
665 xfer.rxData = (uint8_t *)data_in;
666 xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL);
667 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
668 {
669 xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
670 }
671
672 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
673 {
674 status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer);
675 }
676 else
677 {
678 status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer);
679 }
680
681 switch (status)
682 {
683 case kStatus_Success:
684 ret = ARM_DRIVER_OK;
685 break;
686 case kStatus_InvalidArgument:
687 ret = ARM_DRIVER_ERROR_PARAMETER;
688 break;
689 case kStatus_SPI_Busy:
690 ret = ARM_DRIVER_ERROR_BUSY;
691 break;
692 default:
693 ret = ARM_DRIVER_ERROR;
694 break;
695 }
696
697 return ret;
698 }
SPI_DMAGetCount(cmsis_spi_dma_driver_state_t * spi)699 static uint32_t SPI_DMAGetCount(cmsis_spi_dma_driver_state_t *spi)
700 {
701 uint32_t cnt;
702 size_t bytes;
703 spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base);
704
705 bytes = DMA_GetRemainingBytes(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
706
707 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
708 {
709 cnt = spi->handle->masterHandle.transferSize - bytes;
710 }
711 else
712 {
713 cnt = spi->handle->slaveHandle.transferSize - bytes;
714 }
715 cnt /= (((uint32_t)spi_config_p->dataWidth + 8U) / 8U);
716
717 return cnt;
718 }
719
SPI_DMAControl(uint32_t control,uint32_t arg,cmsis_spi_dma_driver_state_t * spi)720 static int32_t SPI_DMAControl(uint32_t control, uint32_t arg, cmsis_spi_dma_driver_state_t *spi)
721 {
722 int32_t result = ARM_DRIVER_OK;
723 bool isContinue = false;
724 if (0U == (spi->flags & (uint8_t)SPI_FLAG_POWER))
725 {
726 return ARM_DRIVER_ERROR;
727 }
728
729 switch (control & ARM_SPI_CONTROL_Msk)
730 {
731 case ARM_SPI_MODE_INACTIVE:
732 SPI_Enable(spi->resource->base, false);
733 isContinue = true;
734 break;
735
736 case ARM_SPI_MODE_MASTER:
737 spi->baudRate_Bps = arg;
738 spi->flags |= (uint8_t)SPI_FLAG_MASTER;
739 isContinue = true;
740 break;
741
742 case ARM_SPI_MODE_SLAVE:
743 spi->flags &= ~(uint8_t)SPI_FLAG_MASTER;
744 isContinue = true;
745 break;
746
747 case ARM_SPI_SET_BUS_SPEED:
748 if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER))
749 {
750 return ARM_DRIVER_ERROR_UNSUPPORTED;
751 }
752
753 (void)SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq());
754 spi->baudRate_Bps = arg;
755 break;
756
757 case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */
758 if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER))
759 {
760 return ARM_DRIVER_ERROR_UNSUPPORTED;
761 }
762 result = (int32_t)spi->baudRate_Bps;
763 break;
764
765 case ARM_SPI_CONTROL_SS:
766 result = ARM_DRIVER_ERROR_UNSUPPORTED;
767 break;
768
769 case ARM_SPI_ABORT_TRANSFER:
770 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
771 {
772 SPI_MasterTransferAbortDMA(spi->resource->base, &spi->handle->masterHandle);
773 }
774 else
775 {
776 SPI_SlaveTransferAbortDMA(spi->resource->base, &spi->handle->slaveHandle);
777 }
778 break;
779
780 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
781 SPI_SetDummyData(spi->resource->base, (uint8_t)arg);
782 result = ARM_DRIVER_OK;
783 break;
784
785 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
786 /* Mode is not supported by current driver. */
787 result = ARM_DRIVER_ERROR_UNSUPPORTED;
788 break;
789
790 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */
791 /* Mode is not supported by current driver. */
792 result = ARM_DRIVER_ERROR_UNSUPPORTED;
793 break;
794
795 default:
796 isContinue = true;
797 /* Avoid MISRA 16.4 violation */
798 break;
799 }
800
801 if (!isContinue)
802 {
803 return result;
804 }
805
806 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
807 {
808 switch (control & ARM_SPI_SS_MASTER_MODE_Msk)
809 {
810 /*
811 * Note:
812 * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or
813 * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured
814 * by user in extern file. Besides, ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver.
815 */
816 case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */
817 break;
818 case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */
819 break;
820 case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */
821 break;
822 case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */
823 break;
824 default:
825 /* Avoid MISRA 16.4 violation */
826 break;
827 }
828 spi_master_config_t masterConfig;
829 SPI_MasterGetDefaultConfig(&masterConfig);
830 masterConfig.baudRate_Bps = spi->baudRate_Bps;
831 SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig);
832
833 if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
834 {
835 SPI_Deinit(spi->resource->base);
836 }
837 (void)SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq());
838
839 DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
840 DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
841 DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority3);
842 DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority2);
843 DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
844 DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
845
846 (void)SPI_MasterTransferCreateHandleDMA(spi->resource->base, &(spi->handle->masterHandle),
847 KSDK_SPI_MasterDMACallback, (void *)spi->cb_event, spi->dmaTxDataHandle,
848 spi->dmaRxDataHandle);
849 spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
850 }
851 else
852 {
853 /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */
854 switch (control & ARM_SPI_SS_SLAVE_MODE_Msk)
855 {
856 case ARM_SPI_SS_SLAVE_HW:
857 break;
858 case ARM_SPI_SS_SLAVE_SW:
859 break;
860 default:
861 /* Avoid MISRA 16.4 violation */
862 break;
863 }
864
865 spi_slave_config_t slaveConfig;
866 SPI_SlaveGetDefaultConfig(&slaveConfig);
867 SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig);
868
869 if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
870 {
871 SPI_Deinit(spi->resource->base);
872 }
873 (void)SPI_SlaveInit(spi->resource->base, &slaveConfig);
874
875 DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
876 DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
877 DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority0);
878 DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority1);
879 DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel);
880 DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel);
881
882 (void)SPI_SlaveTransferCreateHandleDMA(spi->resource->base, &(spi->handle->slaveHandle),
883 KSDK_SPI_SlaveDMACallback, (void *)spi->cb_event, spi->dmaTxDataHandle,
884 spi->dmaRxDataHandle);
885
886 spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
887 }
888
889 return ARM_DRIVER_OK;
890 }
891
SPI_DMAGetStatus(cmsis_spi_dma_driver_state_t * spi)892 static ARM_SPI_STATUS SPI_DMAGetStatus(cmsis_spi_dma_driver_state_t *spi)
893 {
894 ARM_SPI_STATUS stat = {0};
895
896 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
897 {
898 stat.busy =
899 ((spi->handle->masterHandle.txInProgress == true) || (spi->handle->masterHandle.rxInProgress == true)) ?
900 (0U) :
901 (1U);
902 stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U);
903 }
904 else
905 {
906 stat.busy =
907 ((spi->handle->slaveHandle.txInProgress == true) || (spi->handle->slaveHandle.rxInProgress == true)) ?
908 (0U) :
909 (1U);
910 stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U);
911 }
912 stat.mode_fault = 0U;
913 stat.reserved = 0U;
914
915 return stat;
916 }
917 #endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */
918
919 #endif
920
921 #if ((defined(RTE_SPI0) && RTE_SPI0 && !(defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN)) || \
922 (defined(RTE_SPI1) && RTE_SPI1 && !(defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN)) || \
923 (defined(RTE_SPI2) && RTE_SPI2 && !(defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN)) || \
924 (defined(RTE_SPI3) && RTE_SPI3 && !(defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN)) || \
925 (defined(RTE_SPI4) && RTE_SPI4 && !(defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN)) || \
926 (defined(RTE_SPI5) && RTE_SPI5 && !(defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN)) || \
927 (defined(RTE_SPI6) && RTE_SPI6 && !(defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN)) || \
928 (defined(RTE_SPI7) && RTE_SPI7 && !(defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN)) || \
929 (defined(RTE_SPI8) && RTE_SPI8 && !(defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN)) || \
930 (defined(RTE_SPI9) && RTE_SPI9 && !(defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN)) || \
931 (defined(RTE_SPI10) && RTE_SPI10 && !(defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN)) || \
932 (defined(RTE_SPI11) && RTE_SPI11 && !(defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN)) || \
933 (defined(RTE_SPI12) && RTE_SPI12 && !(defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN)) || \
934 (defined(RTE_SPI13) && RTE_SPI13 && !(defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN)))
935
KSDK_SPI_MasterInterruptCallback(SPI_Type * base,spi_master_handle_t * handle,status_t status,void * userData)936 static void KSDK_SPI_MasterInterruptCallback(SPI_Type *base,
937 spi_master_handle_t *handle,
938 status_t status,
939 void *userData)
940 {
941 uint32_t event = 0;
942
943 if ((kStatus_Success == status) || (kStatus_SPI_Idle == status))
944 {
945 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
946 }
947
948 if (kStatus_SPI_Error == status)
949 {
950 event = ARM_SPI_EVENT_DATA_LOST;
951 }
952
953 /* User data is actually CMSIS driver callback. */
954 if (userData != NULL)
955 {
956 ((ARM_SPI_SignalEvent_t)userData)(event);
957 }
958 }
959
KSDK_SPI_SlaveInterruptCallback(SPI_Type * base,spi_slave_handle_t * handle,status_t status,void * userData)960 static void KSDK_SPI_SlaveInterruptCallback(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData)
961 {
962 uint32_t event = 0;
963
964 if ((kStatus_Success == status) || (kStatus_SPI_Idle == status))
965 {
966 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
967 }
968
969 if (kStatus_SPI_Error == status)
970 {
971 event = ARM_SPI_EVENT_DATA_LOST;
972 }
973
974 /* User data is actually CMSIS driver callback. */
975 if (userData != NULL)
976 {
977 ((ARM_SPI_SignalEvent_t)userData)(event);
978 }
979 }
980
SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_spi_interrupt_driver_state_t * spi)981 static int32_t SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_interrupt_driver_state_t *spi)
982 {
983 if (0U == (spi->flags & (uint8_t)SPI_FLAG_INIT))
984 {
985 spi->cb_event = cb_event;
986 spi->flags = (uint8_t)SPI_FLAG_INIT;
987 }
988
989 return ARM_DRIVER_OK;
990 }
991
SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t * spi)992 static int32_t SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t *spi)
993 {
994 spi->flags = (uint8_t)SPI_FLAG_UNINIT;
995 return ARM_DRIVER_OK;
996 }
997
SPI_InterruptPowerControl(ARM_POWER_STATE state,cmsis_spi_interrupt_driver_state_t * spi)998 static int32_t SPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_spi_interrupt_driver_state_t *spi)
999 {
1000 int32_t result = ARM_DRIVER_OK;
1001 switch (state)
1002 {
1003 case ARM_POWER_OFF:
1004 if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
1005 {
1006 SPI_Deinit(spi->resource->base);
1007 spi->flags = (uint8_t)SPI_FLAG_INIT;
1008 }
1009 break;
1010
1011 case ARM_POWER_LOW:
1012 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1013 break;
1014
1015 case ARM_POWER_FULL:
1016 if (spi->flags == (uint8_t)SPI_FLAG_UNINIT)
1017 {
1018 return ARM_DRIVER_ERROR;
1019 }
1020
1021 if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
1022 {
1023 /* Driver already powered */
1024 break;
1025 }
1026
1027 /* Enable flexcomm clock gate */
1028 CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]);
1029 spi->flags |= (uint8_t)SPI_FLAG_POWER;
1030 break;
1031 default:
1032 /* Avoid MISRA 16.4 violation */
1033 break;
1034 }
1035
1036 return result;
1037 }
1038
SPI_InterruptSend(const void * data,uint32_t num,cmsis_spi_interrupt_driver_state_t * spi)1039 static int32_t SPI_InterruptSend(const void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi)
1040 {
1041 int32_t ret;
1042 status_t status;
1043 spi_transfer_t xfer = {0};
1044
1045 xfer.rxData = NULL;
1046 xfer.txData = (uint8_t *)data;
1047 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1048 {
1049 xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
1050 }
1051
1052 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1053 {
1054 xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL);
1055 status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer);
1056 }
1057 else
1058 {
1059 xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL);
1060 status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer);
1061 }
1062
1063 switch (status)
1064 {
1065 case kStatus_Success:
1066 ret = ARM_DRIVER_OK;
1067 break;
1068 case kStatus_InvalidArgument:
1069 ret = ARM_DRIVER_ERROR_PARAMETER;
1070 break;
1071 case kStatus_SPI_Busy:
1072 ret = ARM_DRIVER_ERROR_BUSY;
1073 break;
1074 default:
1075 ret = ARM_DRIVER_ERROR;
1076 break;
1077 }
1078
1079 return ret;
1080 }
1081
SPI_InterruptReceive(void * data,uint32_t num,cmsis_spi_interrupt_driver_state_t * spi)1082 static int32_t SPI_InterruptReceive(void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi)
1083 {
1084 int32_t ret;
1085 status_t status;
1086 spi_transfer_t xfer = {0};
1087
1088 xfer.txData = NULL;
1089 xfer.rxData = (uint8_t *)data;
1090 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1091 {
1092 xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
1093 }
1094
1095 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1096 {
1097 xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL);
1098 status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer);
1099 }
1100 else
1101 {
1102 xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL);
1103 status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer);
1104 }
1105
1106 switch (status)
1107 {
1108 case kStatus_Success:
1109 ret = ARM_DRIVER_OK;
1110 break;
1111 case kStatus_InvalidArgument:
1112 ret = ARM_DRIVER_ERROR_PARAMETER;
1113 break;
1114 case kStatus_SPI_Busy:
1115 ret = ARM_DRIVER_ERROR_BUSY;
1116 break;
1117 default:
1118 ret = ARM_DRIVER_ERROR;
1119 break;
1120 }
1121
1122 return ret;
1123 }
1124
SPI_InterruptTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_spi_interrupt_driver_state_t * spi)1125 static int32_t SPI_InterruptTransfer(const void *data_out,
1126 void *data_in,
1127 uint32_t num,
1128 cmsis_spi_interrupt_driver_state_t *spi)
1129 {
1130 int32_t ret;
1131 status_t status;
1132 spi_transfer_t xfer = {0};
1133
1134 xfer.txData = (uint8_t *)data_out;
1135 xfer.rxData = (uint8_t *)data_in;
1136 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1137 {
1138 xfer.configFlags |= (uint32_t)kSPI_FrameAssert;
1139 }
1140
1141 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1142 {
1143 xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL);
1144 status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer);
1145 }
1146 else
1147 {
1148 xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL);
1149 status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer);
1150 }
1151
1152 switch (status)
1153 {
1154 case kStatus_Success:
1155 ret = ARM_DRIVER_OK;
1156 break;
1157 case kStatus_InvalidArgument:
1158 ret = ARM_DRIVER_ERROR_PARAMETER;
1159 break;
1160 case kStatus_SPI_Busy:
1161 ret = ARM_DRIVER_ERROR_BUSY;
1162 break;
1163 default:
1164 ret = ARM_DRIVER_ERROR;
1165 break;
1166 }
1167
1168 return ret;
1169 }
SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t * spi)1170 static uint32_t SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t *spi)
1171 {
1172 uint32_t cnt;
1173 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1174 {
1175 cnt = spi->handle->masterHandle.totalByteCount - spi->handle->masterHandle.rxRemainingBytes;
1176 cnt /= (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL);
1177 }
1178 else
1179 {
1180 cnt = spi->handle->slaveHandle.totalByteCount - spi->handle->slaveHandle.rxRemainingBytes;
1181 cnt /= (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL);
1182 }
1183
1184 return cnt;
1185 }
1186
SPI_InterruptControl(uint32_t control,uint32_t arg,cmsis_spi_interrupt_driver_state_t * spi)1187 static int32_t SPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_spi_interrupt_driver_state_t *spi)
1188 {
1189 int32_t result = ARM_DRIVER_OK;
1190 bool isContinue = false;
1191 if (0U == (spi->flags & (uint8_t)SPI_FLAG_POWER))
1192 {
1193 return ARM_DRIVER_ERROR;
1194 }
1195
1196 switch (control & ARM_SPI_CONTROL_Msk)
1197 {
1198 case ARM_SPI_MODE_INACTIVE: /* SPI mode Inactive */
1199 (void)FLEXCOMM_Init(spi->resource->base, FLEXCOMM_PERIPH_NONE);
1200 isContinue = true;
1201 break;
1202
1203 case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */
1204 spi->baudRate_Bps = arg;
1205 spi->flags |= (uint8_t)SPI_FLAG_MASTER;
1206 isContinue = true;
1207 break;
1208
1209 case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on MISO, Input on MOSI) */
1210 spi->flags &= ~(uint8_t)SPI_FLAG_MASTER;
1211 isContinue = true;
1212 break;
1213
1214 case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */
1215 if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER))
1216 {
1217 return ARM_DRIVER_ERROR_UNSUPPORTED;
1218 }
1219 result = (int32_t)spi->baudRate_Bps;
1220 break;
1221
1222 case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */
1223 if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER))
1224 {
1225 return ARM_DRIVER_ERROR_UNSUPPORTED;
1226 }
1227 (void)SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq());
1228 spi->baudRate_Bps = arg;
1229 break;
1230
1231 case ARM_SPI_CONTROL_SS:
1232 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1233 break;
1234
1235 case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */
1236 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1237 {
1238 SPI_MasterTransferAbort(spi->resource->base, &spi->handle->masterHandle);
1239 }
1240 else
1241 {
1242 SPI_SlaveTransferAbort(spi->resource->base, &spi->handle->slaveHandle);
1243 }
1244 break;
1245
1246 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
1247 SPI_SetDummyData(spi->resource->base, (uint8_t)arg);
1248 break;
1249
1250 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
1251 /* Mode is not supported by current driver. */
1252 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1253 break;
1254
1255 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */
1256 /* Mode is not supported by current driver. */
1257 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1258 break;
1259
1260 default:
1261 isContinue = true;
1262 /* Avoid MISRA 16.4 violation */
1263 break;
1264 }
1265
1266 if (!isContinue)
1267 {
1268 return result;
1269 }
1270
1271 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1272 {
1273 switch (control & ARM_SPI_SS_MASTER_MODE_Msk)
1274 {
1275 /*
1276 * Note:
1277 * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or
1278 * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured
1279 * by user in extern file. Besides ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver.
1280 */
1281 case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */
1282 break;
1283 case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */
1284 break;
1285 case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */
1286 break;
1287 case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */
1288 break;
1289 default:
1290 /* Avoid MISRA 16.4 violation */
1291 break;
1292 }
1293
1294 spi_master_config_t masterConfig;
1295 SPI_MasterGetDefaultConfig(&masterConfig);
1296 masterConfig.baudRate_Bps = spi->baudRate_Bps;
1297
1298 SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig);
1299
1300 if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
1301 {
1302 SPI_Deinit(spi->resource->base);
1303 }
1304 (void)SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq());
1305 (void)SPI_MasterTransferCreateHandle(spi->resource->base, &spi->handle->masterHandle,
1306 KSDK_SPI_MasterInterruptCallback, (void *)spi->cb_event);
1307 spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1308 }
1309 else
1310 {
1311 /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */
1312 switch (control & ARM_SPI_SS_SLAVE_MODE_Msk)
1313 {
1314 case ARM_SPI_SS_SLAVE_HW:
1315 break;
1316 case ARM_SPI_SS_SLAVE_SW:
1317 break;
1318 default:
1319 /* Avoid MISRA 16.4 violation */
1320 break;
1321 }
1322
1323 spi_slave_config_t slaveConfig;
1324 SPI_SlaveGetDefaultConfig(&slaveConfig);
1325
1326 SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig);
1327
1328 if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
1329 {
1330 SPI_Deinit(spi->resource->base);
1331 }
1332 (void)SPI_SlaveInit(spi->resource->base, &slaveConfig);
1333 (void)SPI_SlaveTransferCreateHandle(spi->resource->base, &spi->handle->slaveHandle,
1334 KSDK_SPI_SlaveInterruptCallback, (void *)spi->cb_event);
1335 spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1336 }
1337
1338 return ARM_DRIVER_OK;
1339 }
1340
SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t * spi)1341 static ARM_SPI_STATUS SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t *spi)
1342 {
1343 ARM_SPI_STATUS stat = {0};
1344
1345 if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1346 {
1347 stat.busy =
1348 ((spi->handle->masterHandle.txRemainingBytes > 0U) || (spi->handle->masterHandle.rxRemainingBytes > 0U)) ?
1349 (0U) :
1350 (1U);
1351 stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U);
1352 }
1353 else
1354 {
1355 stat.busy =
1356 ((spi->handle->slaveHandle.txRemainingBytes > 0U) || (spi->handle->slaveHandle.rxRemainingBytes > 0U)) ?
1357 (0U) :
1358 (1U);
1359 stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U);
1360 }
1361 stat.mode_fault = 0U;
1362 stat.reserved = 0U;
1363
1364 return stat;
1365 }
1366
1367 #endif
1368
1369 #if defined(SPI0) && defined(RTE_SPI0) && RTE_SPI0
1370
1371 /* User needs to provide the implementation for SPI0_GetFreq/InitPins/DeinitPins
1372 in the application for enabling according instance. */
1373 extern uint32_t SPI0_GetFreq(void);
1374
1375 static cmsis_spi_resource_t SPI0_Resource = {SPI0, 0, SPI0_GetFreq};
1376
1377 #if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
1378
1379 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1380
1381 static cmsis_spi_dma_resource_t SPI0_DMAResource = {RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH,
1382 RTE_SPI0_DMA_RX_DMA_BASE, RTE_SPI0_DMA_RX_CH};
1383
1384 static cmsis_spi_dma_handle_t SPI0_DmaHandle;
1385 static dma_handle_t SPI0_DmaTxDataHandle;
1386 static dma_handle_t SPI0_DmaRxDataHandle;
1387
1388 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1389 ARMCC_SECTION("spi0_dma_driver_state")
1390 static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = {
1391 #else
1392 static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = {
1393 #endif
1394 &SPI0_Resource, &SPI0_DMAResource, &SPI0_DmaHandle, &SPI0_DmaTxDataHandle, &SPI0_DmaRxDataHandle,
1395
1396 };
1397
SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)1398 static int32_t SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1399 {
1400 #ifdef RTE_SPI0_PIN_INIT
1401 RTE_SPI0_PIN_INIT();
1402 #endif
1403 return SPI_DMAInitialize(cb_event, &SPI0_DMADriverState);
1404 }
1405
SPI0_DMAUninitialize(void)1406 static int32_t SPI0_DMAUninitialize(void)
1407 {
1408 #ifdef RTE_SPI0_PIN_DEINIT
1409 RTE_SPI0_PIN_DEINIT();
1410 #endif
1411 return SPI_DMAUninitialize(&SPI0_DMADriverState);
1412 }
1413
SPI0_DMAPowerControl(ARM_POWER_STATE state)1414 static int32_t SPI0_DMAPowerControl(ARM_POWER_STATE state)
1415 {
1416 return SPI_DMAPowerControl(state, &SPI0_DMADriverState);
1417 }
1418
SPI0_DMASend(const void * data,uint32_t num)1419 static int32_t SPI0_DMASend(const void *data, uint32_t num)
1420 {
1421 return SPI_DMASend(data, num, &SPI0_DMADriverState);
1422 }
1423
SPI0_DMAReceive(void * data,uint32_t num)1424 static int32_t SPI0_DMAReceive(void *data, uint32_t num)
1425 {
1426 return SPI_DMAReceive(data, num, &SPI0_DMADriverState);
1427 }
1428
SPI0_DMATransfer(const void * data_out,void * data_in,uint32_t num)1429 static int32_t SPI0_DMATransfer(const void *data_out, void *data_in, uint32_t num)
1430 {
1431 return SPI_DMATransfer(data_out, data_in, num, &SPI0_DMADriverState);
1432 }
1433
SPI0_DMAGetCount(void)1434 static uint32_t SPI0_DMAGetCount(void)
1435 {
1436 return SPI_DMAGetCount(&SPI0_DMADriverState);
1437 }
1438
SPI0_DMAControl(uint32_t control,uint32_t arg)1439 static int32_t SPI0_DMAControl(uint32_t control, uint32_t arg)
1440 {
1441 return SPI_DMAControl(control, arg, &SPI0_DMADriverState);
1442 }
1443
SPI0_DMAGetStatus(void)1444 static ARM_SPI_STATUS SPI0_DMAGetStatus(void)
1445 {
1446 return SPI_DMAGetStatus(&SPI0_DMADriverState);
1447 }
1448
1449 #endif
1450
1451 #else
1452
1453 static cmsis_spi_handle_t SPI0_Handle;
1454
1455 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1456 ARMCC_SECTION("spi0_interrupt_driver_state")
1457 static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = {
1458 #else
1459 static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = {
1460 #endif
1461 &SPI0_Resource,
1462 &SPI0_Handle,
1463 };
1464
SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1465 static int32_t SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1466 {
1467 #ifdef RTE_SPI0_PIN_INIT
1468 RTE_SPI0_PIN_INIT();
1469 #endif
1470 return SPI_InterruptInitialize(cb_event, &SPI0_InterruptDriverState);
1471 }
1472
SPI0_InterruptUninitialize(void)1473 static int32_t SPI0_InterruptUninitialize(void)
1474 {
1475 #ifdef RTE_SPI0_PIN_DEINIT
1476 RTE_SPI0_PIN_DEINIT();
1477 #endif
1478 return SPI_InterruptUninitialize(&SPI0_InterruptDriverState);
1479 }
1480
SPI0_InterruptPowerControl(ARM_POWER_STATE state)1481 static int32_t SPI0_InterruptPowerControl(ARM_POWER_STATE state)
1482 {
1483 return SPI_InterruptPowerControl(state, &SPI0_InterruptDriverState);
1484 }
1485
SPI0_InterruptSend(const void * data,uint32_t num)1486 static int32_t SPI0_InterruptSend(const void *data, uint32_t num)
1487 {
1488 return SPI_InterruptSend(data, num, &SPI0_InterruptDriverState);
1489 }
1490
SPI0_InterruptReceive(void * data,uint32_t num)1491 static int32_t SPI0_InterruptReceive(void *data, uint32_t num)
1492 {
1493 return SPI_InterruptReceive(data, num, &SPI0_InterruptDriverState);
1494 }
1495
SPI0_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1496 static int32_t SPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1497 {
1498 return SPI_InterruptTransfer(data_out, data_in, num, &SPI0_InterruptDriverState);
1499 }
1500
SPI0_InterruptGetCount(void)1501 static uint32_t SPI0_InterruptGetCount(void)
1502 {
1503 return SPI_InterruptGetCount(&SPI0_InterruptDriverState);
1504 }
1505
SPI0_InterruptControl(uint32_t control,uint32_t arg)1506 static int32_t SPI0_InterruptControl(uint32_t control, uint32_t arg)
1507 {
1508 return SPI_InterruptControl(control, arg, &SPI0_InterruptDriverState);
1509 }
1510
SPI0_InterruptGetStatus(void)1511 static ARM_SPI_STATUS SPI0_InterruptGetStatus(void)
1512 {
1513 return SPI_InterruptGetStatus(&SPI0_InterruptDriverState);
1514 }
1515
1516 #endif
1517
1518 ARM_DRIVER_SPI Driver_SPI0 = {SPIx_GetVersion, SPIx_GetCapabilities,
1519 #if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN
1520 SPI0_DMAInitialize, SPI0_DMAUninitialize, SPI0_DMAPowerControl, SPI0_DMASend,
1521 SPI0_DMAReceive, SPI0_DMATransfer, SPI0_DMAGetCount, SPI0_DMAControl,
1522 SPI0_DMAGetStatus
1523 #else
1524 SPI0_InterruptInitialize,
1525 SPI0_InterruptUninitialize,
1526 SPI0_InterruptPowerControl,
1527 SPI0_InterruptSend,
1528 SPI0_InterruptReceive,
1529 SPI0_InterruptTransfer,
1530 SPI0_InterruptGetCount,
1531 SPI0_InterruptControl,
1532 SPI0_InterruptGetStatus
1533 #endif
1534 };
1535
1536 #endif /* SPI0 */
1537
1538 #if defined(SPI1) && defined(RTE_SPI1) && RTE_SPI1
1539 /* User needs to provide the implementation for SPI1_GetFreq/InitPins/DeinitPins
1540 in the application for enabling according instance. */
1541 extern uint32_t SPI1_GetFreq(void);
1542 static cmsis_spi_resource_t SPI1_Resource = {SPI1, 1, SPI1_GetFreq};
1543
1544 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1545
1546 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1547
1548 static cmsis_spi_dma_resource_t SPI1_DMAResource = {RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH,
1549 RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH};
1550
1551 static cmsis_spi_dma_handle_t SPI1_DmaHandle;
1552 static dma_handle_t SPI1_DmaTxDataHandle;
1553 static dma_handle_t SPI1_DmaRxDataHandle;
1554
1555 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1556 ARMCC_SECTION("spi1_dma_driver_state")
1557 static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = {
1558 #else
1559 static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = {
1560 #endif
1561 &SPI1_Resource, &SPI1_DMAResource, &SPI1_DmaHandle, &SPI1_DmaRxDataHandle, &SPI1_DmaTxDataHandle,
1562 };
1563
SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)1564 static int32_t SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1565 {
1566 #ifdef RTE_SPI1_PIN_INIT
1567 RTE_SPI1_PIN_INIT();
1568 #endif
1569 return SPI_DMAInitialize(cb_event, &SPI1_DMADriverState);
1570 }
1571
SPI1_DMAUninitialize(void)1572 static int32_t SPI1_DMAUninitialize(void)
1573 {
1574 #ifdef RTE_SPI1_PIN_DEINIT
1575 RTE_SPI1_PIN_DEINIT();
1576 #endif
1577 return SPI_DMAUninitialize(&SPI1_DMADriverState);
1578 }
1579
SPI1_DMAPowerControl(ARM_POWER_STATE state)1580 static int32_t SPI1_DMAPowerControl(ARM_POWER_STATE state)
1581 {
1582 return SPI_DMAPowerControl(state, &SPI1_DMADriverState);
1583 }
1584
SPI1_DMASend(const void * data,uint32_t num)1585 static int32_t SPI1_DMASend(const void *data, uint32_t num)
1586 {
1587 return SPI_DMASend(data, num, &SPI1_DMADriverState);
1588 }
1589
SPI1_DMAReceive(void * data,uint32_t num)1590 static int32_t SPI1_DMAReceive(void *data, uint32_t num)
1591 {
1592 return SPI_DMAReceive(data, num, &SPI1_DMADriverState);
1593 }
1594
SPI1_DMATransfer(const void * data_out,void * data_in,uint32_t num)1595 static int32_t SPI1_DMATransfer(const void *data_out, void *data_in, uint32_t num)
1596 {
1597 return SPI_DMATransfer(data_out, data_in, num, &SPI1_DMADriverState);
1598 }
1599
SPI1_DMAGetCount(void)1600 static uint32_t SPI1_DMAGetCount(void)
1601 {
1602 return SPI_DMAGetCount(&SPI1_DMADriverState);
1603 }
1604
SPI1_DMAControl(uint32_t control,uint32_t arg)1605 static int32_t SPI1_DMAControl(uint32_t control, uint32_t arg)
1606 {
1607 return SPI_DMAControl(control, arg, &SPI1_DMADriverState);
1608 }
1609
SPI1_DMAGetStatus(void)1610 static ARM_SPI_STATUS SPI1_DMAGetStatus(void)
1611 {
1612 return SPI_DMAGetStatus(&SPI1_DMADriverState);
1613 }
1614
1615 #endif
1616
1617 #else
1618
1619 static cmsis_spi_handle_t SPI1_Handle;
1620
1621 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1622 ARMCC_SECTION("spi1_interrupt_driver_state")
1623 static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = {
1624 #else
1625 static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = {
1626 #endif
1627 &SPI1_Resource,
1628 &SPI1_Handle,
1629 };
1630
SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1631 static int32_t SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1632 {
1633 #ifdef RTE_SPI1_PIN_INIT
1634 RTE_SPI1_PIN_INIT();
1635 #endif
1636 return SPI_InterruptInitialize(cb_event, &SPI1_InterruptDriverState);
1637 }
1638
SPI1_InterruptUninitialize(void)1639 static int32_t SPI1_InterruptUninitialize(void)
1640 {
1641 #ifdef RTE_SPI1_PIN_DEINIT
1642 RTE_SPI1_PIN_DEINIT();
1643 #endif
1644 return SPI_InterruptUninitialize(&SPI1_InterruptDriverState);
1645 }
1646
SPI1_InterruptPowerControl(ARM_POWER_STATE state)1647 static int32_t SPI1_InterruptPowerControl(ARM_POWER_STATE state)
1648 {
1649 return SPI_InterruptPowerControl(state, &SPI1_InterruptDriverState);
1650 }
1651
SPI1_InterruptSend(const void * data,uint32_t num)1652 static int32_t SPI1_InterruptSend(const void *data, uint32_t num)
1653 {
1654 return SPI_InterruptSend(data, num, &SPI1_InterruptDriverState);
1655 }
1656
SPI1_InterruptReceive(void * data,uint32_t num)1657 static int32_t SPI1_InterruptReceive(void *data, uint32_t num)
1658 {
1659 return SPI_InterruptReceive(data, num, &SPI1_InterruptDriverState);
1660 }
1661
SPI1_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1662 static int32_t SPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1663 {
1664 return SPI_InterruptTransfer(data_out, data_in, num, &SPI1_InterruptDriverState);
1665 }
1666
SPI1_InterruptGetCount(void)1667 static uint32_t SPI1_InterruptGetCount(void)
1668 {
1669 return SPI_InterruptGetCount(&SPI1_InterruptDriverState);
1670 }
1671
SPI1_InterruptControl(uint32_t control,uint32_t arg)1672 static int32_t SPI1_InterruptControl(uint32_t control, uint32_t arg)
1673 {
1674 return SPI_InterruptControl(control, arg, &SPI1_InterruptDriverState);
1675 }
1676
SPI1_InterruptGetStatus(void)1677 static ARM_SPI_STATUS SPI1_InterruptGetStatus(void)
1678 {
1679 return SPI_InterruptGetStatus(&SPI1_InterruptDriverState);
1680 }
1681
1682 #endif
1683
1684 ARM_DRIVER_SPI Driver_SPI1 = {SPIx_GetVersion, SPIx_GetCapabilities,
1685 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1686 SPI1_DMAInitialize, SPI1_DMAUninitialize, SPI1_DMAPowerControl, SPI1_DMASend,
1687 SPI1_DMAReceive, SPI1_DMATransfer, SPI1_DMAGetCount, SPI1_DMAControl,
1688 SPI1_DMAGetStatus
1689 #else
1690 SPI1_InterruptInitialize,
1691 SPI1_InterruptUninitialize,
1692 SPI1_InterruptPowerControl,
1693 SPI1_InterruptSend,
1694 SPI1_InterruptReceive,
1695 SPI1_InterruptTransfer,
1696 SPI1_InterruptGetCount,
1697 SPI1_InterruptControl,
1698 SPI1_InterruptGetStatus
1699 #endif
1700 };
1701
1702 #endif /* SPI1 */
1703
1704 #if defined(SPI2) && defined(RTE_SPI2) && RTE_SPI2
1705
1706 /* User needs to provide the implementation for SPI2_GetFreq/InitPins/DeinitPins
1707 in the application for enabling according instance. */
1708 extern uint32_t SPI2_GetFreq(void);
1709
1710 static cmsis_spi_resource_t SPI2_Resource = {SPI2, 2, SPI2_GetFreq};
1711
1712 #if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
1713
1714 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1715
1716 static cmsis_spi_dma_resource_t SPI2_DMAResource = {RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH,
1717 RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH};
1718
1719 static cmsis_spi_dma_handle_t SPI2_DmaHandle;
1720 static dma_handle_t SPI2_DmaTxDataHandle;
1721 static dma_handle_t SPI2_DmaRxDataHandle;
1722
1723 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1724 ARMCC_SECTION("spi2_dma_driver_state")
1725 static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = {
1726 #else
1727 static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = {
1728 #endif
1729 &SPI2_Resource, &SPI2_DMAResource, &SPI2_DmaHandle, &SPI2_DmaRxDataHandle, &SPI2_DmaTxDataHandle,
1730 };
1731
SPI2_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)1732 static int32_t SPI2_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1733 {
1734 #ifdef RTE_SPI2_PIN_INIT
1735 RTE_SPI2_PIN_INIT();
1736 #endif
1737 return SPI_DMAInitialize(cb_event, &SPI2_DMADriverState);
1738 }
1739
SPI2_DMAUninitialize(void)1740 static int32_t SPI2_DMAUninitialize(void)
1741 {
1742 #ifdef RTE_SPI2_PIN_DEINIT
1743 RTE_SPI2_PIN_DEINIT();
1744 #endif
1745 return SPI_DMAUninitialize(&SPI2_DMADriverState);
1746 }
1747
SPI2_DMAPowerControl(ARM_POWER_STATE state)1748 static int32_t SPI2_DMAPowerControl(ARM_POWER_STATE state)
1749 {
1750 return SPI_DMAPowerControl(state, &SPI2_DMADriverState);
1751 }
1752
SPI2_DMASend(const void * data,uint32_t num)1753 static int32_t SPI2_DMASend(const void *data, uint32_t num)
1754 {
1755 return SPI_DMASend(data, num, &SPI2_DMADriverState);
1756 }
1757
SPI2_DMAReceive(void * data,uint32_t num)1758 static int32_t SPI2_DMAReceive(void *data, uint32_t num)
1759 {
1760 return SPI_DMAReceive(data, num, &SPI2_DMADriverState);
1761 }
1762
SPI2_DMATransfer(const void * data_out,void * data_in,uint32_t num)1763 static int32_t SPI2_DMATransfer(const void *data_out, void *data_in, uint32_t num)
1764 {
1765 return SPI_DMATransfer(data_out, data_in, num, &SPI2_DMADriverState);
1766 }
1767
SPI2_DMAGetCount(void)1768 static uint32_t SPI2_DMAGetCount(void)
1769 {
1770 return SPI_DMAGetCount(&SPI2_DMADriverState);
1771 }
1772
SPI2_DMAControl(uint32_t control,uint32_t arg)1773 static int32_t SPI2_DMAControl(uint32_t control, uint32_t arg)
1774 {
1775 return SPI_DMAControl(control, arg, &SPI2_DMADriverState);
1776 }
1777
SPI2_DMAGetStatus(void)1778 static ARM_SPI_STATUS SPI2_DMAGetStatus(void)
1779 {
1780 return SPI_DMAGetStatus(&SPI2_DMADriverState);
1781 }
1782
1783 #endif
1784
1785 #else
1786
1787 static cmsis_spi_handle_t SPI2_Handle;
1788
1789 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1790 ARMCC_SECTION("spi2_interrupt_driver_state")
1791 static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = {
1792 #else
1793 static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = {
1794 #endif
1795 &SPI2_Resource,
1796 &SPI2_Handle,
1797 };
1798
SPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1799 static int32_t SPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1800 {
1801 #ifdef RTE_SPI2_PIN_INIT
1802 RTE_SPI2_PIN_INIT();
1803 #endif
1804 return SPI_InterruptInitialize(cb_event, &SPI2_InterruptDriverState);
1805 }
1806
SPI2_InterruptUninitialize(void)1807 static int32_t SPI2_InterruptUninitialize(void)
1808 {
1809 #ifdef RTE_SPI2_PIN_DEINIT
1810 RTE_SPI2_PIN_DEINIT();
1811 #endif
1812 return SPI_InterruptUninitialize(&SPI2_InterruptDriverState);
1813 }
1814
SPI2_InterruptPowerControl(ARM_POWER_STATE state)1815 static int32_t SPI2_InterruptPowerControl(ARM_POWER_STATE state)
1816 {
1817 return SPI_InterruptPowerControl(state, &SPI2_InterruptDriverState);
1818 }
1819
SPI2_InterruptSend(const void * data,uint32_t num)1820 static int32_t SPI2_InterruptSend(const void *data, uint32_t num)
1821 {
1822 return SPI_InterruptSend(data, num, &SPI2_InterruptDriverState);
1823 }
1824
SPI2_InterruptReceive(void * data,uint32_t num)1825 static int32_t SPI2_InterruptReceive(void *data, uint32_t num)
1826 {
1827 return SPI_InterruptReceive(data, num, &SPI2_InterruptDriverState);
1828 }
1829
SPI2_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1830 static int32_t SPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1831 {
1832 return SPI_InterruptTransfer(data_out, data_in, num, &SPI2_InterruptDriverState);
1833 }
1834
SPI2_InterruptGetCount(void)1835 static uint32_t SPI2_InterruptGetCount(void)
1836 {
1837 return SPI_InterruptGetCount(&SPI2_InterruptDriverState);
1838 }
1839
SPI2_InterruptControl(uint32_t control,uint32_t arg)1840 static int32_t SPI2_InterruptControl(uint32_t control, uint32_t arg)
1841 {
1842 return SPI_InterruptControl(control, arg, &SPI2_InterruptDriverState);
1843 }
1844
SPI2_InterruptGetStatus(void)1845 static ARM_SPI_STATUS SPI2_InterruptGetStatus(void)
1846 {
1847 return SPI_InterruptGetStatus(&SPI2_InterruptDriverState);
1848 }
1849
1850 #endif
1851
1852 ARM_DRIVER_SPI Driver_SPI2 = {SPIx_GetVersion, SPIx_GetCapabilities,
1853 #if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
1854 SPI2_DMAInitialize, SPI2_DMAUninitialize, SPI2_DMAPowerControl, SPI2_DMASend,
1855 SPI2_DMAReceive, SPI2_DMATransfer, SPI2_DMAGetCount, SPI2_DMAControl,
1856 SPI2_DMAGetStatus
1857 #else
1858 SPI2_InterruptInitialize,
1859 SPI2_InterruptUninitialize,
1860 SPI2_InterruptPowerControl,
1861 SPI2_InterruptSend,
1862 SPI2_InterruptReceive,
1863 SPI2_InterruptTransfer,
1864 SPI2_InterruptGetCount,
1865 SPI2_InterruptControl,
1866 SPI2_InterruptGetStatus
1867 #endif
1868 };
1869
1870 #endif /* SPI2 */
1871
1872 #if defined(SPI3) && defined(RTE_SPI3) && RTE_SPI3
1873
1874 /* User needs to provide the implementation for SPI3_GetFreq/InitPins/DeinitPins
1875 in the application for enabling according instance. */
1876 extern uint32_t SPI3_GetFreq(void);
1877
1878 static cmsis_spi_resource_t SPI3_Resource = {SPI3, 3, SPI3_GetFreq};
1879
1880 #if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN
1881
1882 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
1883
1884 static cmsis_spi_dma_resource_t SPI3_DMAResource = {RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH,
1885 RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH};
1886
1887 static cmsis_spi_dma_handle_t SPI3_DmaHandle;
1888 static dma_handle_t SPI3_DmaTxDataHandle;
1889 static dma_handle_t SPI3_DmaRxDataHandle;
1890
1891 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1892 ARMCC_SECTION("spi3_dma_driver_state")
1893 static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = {
1894 #else
1895 static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = {
1896 #endif
1897 &SPI3_Resource, &SPI3_DMAResource, &SPI3_DmaHandle, &SPI3_DmaRxDataHandle, &SPI3_DmaTxDataHandle,
1898 };
1899
SPI3_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)1900 static int32_t SPI3_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1901 {
1902 #ifdef RTE_SPI3_PIN_INIT
1903 RTE_SPI3_PIN_INIT();
1904 #endif
1905 return SPI_DMAInitialize(cb_event, &SPI3_DMADriverState);
1906 }
1907
SPI3_DMAUninitialize(void)1908 static int32_t SPI3_DMAUninitialize(void)
1909 {
1910 #ifdef RTE_SPI3_PIN_DEINIT
1911 RTE_SPI3_PIN_DEINIT();
1912 #endif
1913 return SPI_DMAUninitialize(&SPI3_DMADriverState);
1914 }
1915
SPI3_DMAPowerControl(ARM_POWER_STATE state)1916 static int32_t SPI3_DMAPowerControl(ARM_POWER_STATE state)
1917 {
1918 return SPI_DMAPowerControl(state, &SPI3_DMADriverState);
1919 }
1920
SPI3_DMASend(const void * data,uint32_t num)1921 static int32_t SPI3_DMASend(const void *data, uint32_t num)
1922 {
1923 return SPI_DMASend(data, num, &SPI3_DMADriverState);
1924 }
1925
SPI3_DMAReceive(void * data,uint32_t num)1926 static int32_t SPI3_DMAReceive(void *data, uint32_t num)
1927 {
1928 return SPI_DMAReceive(data, num, &SPI3_DMADriverState);
1929 }
1930
SPI3_DMATransfer(const void * data_out,void * data_in,uint32_t num)1931 static int32_t SPI3_DMATransfer(const void *data_out, void *data_in, uint32_t num)
1932 {
1933 return SPI_DMATransfer(data_out, data_in, num, &SPI3_DMADriverState);
1934 }
1935
SPI3_DMAGetCount(void)1936 static uint32_t SPI3_DMAGetCount(void)
1937 {
1938 return SPI_DMAGetCount(&SPI3_DMADriverState);
1939 }
1940
SPI3_DMAControl(uint32_t control,uint32_t arg)1941 static int32_t SPI3_DMAControl(uint32_t control, uint32_t arg)
1942 {
1943 return SPI_DMAControl(control, arg, &SPI3_DMADriverState);
1944 }
1945
SPI3_DMAGetStatus(void)1946 static ARM_SPI_STATUS SPI3_DMAGetStatus(void)
1947 {
1948 return SPI_DMAGetStatus(&SPI3_DMADriverState);
1949 }
1950
1951 #endif
1952
1953 #else
1954
1955 static cmsis_spi_handle_t SPI3_Handle;
1956
1957 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1958 ARMCC_SECTION("spi3_interrupt_driver_state")
1959 static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = {
1960 #else
1961 static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = {
1962 #endif
1963 &SPI3_Resource,
1964 &SPI3_Handle,
1965 };
1966
SPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1967 static int32_t SPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1968 {
1969 #ifdef RTE_SPI3_PIN_INIT
1970 RTE_SPI3_PIN_INIT();
1971 #endif
1972 return SPI_InterruptInitialize(cb_event, &SPI3_InterruptDriverState);
1973 }
1974
SPI3_InterruptUninitialize(void)1975 static int32_t SPI3_InterruptUninitialize(void)
1976 {
1977 #ifdef RTE_SPI3_PIN_DEINIT
1978 RTE_SPI3_PIN_DEINIT();
1979 #endif
1980 return SPI_InterruptUninitialize(&SPI3_InterruptDriverState);
1981 }
1982
SPI3_InterruptPowerControl(ARM_POWER_STATE state)1983 static int32_t SPI3_InterruptPowerControl(ARM_POWER_STATE state)
1984 {
1985 return SPI_InterruptPowerControl(state, &SPI3_InterruptDriverState);
1986 }
1987
SPI3_InterruptSend(const void * data,uint32_t num)1988 static int32_t SPI3_InterruptSend(const void *data, uint32_t num)
1989 {
1990 return SPI_InterruptSend(data, num, &SPI3_InterruptDriverState);
1991 }
1992
SPI3_InterruptReceive(void * data,uint32_t num)1993 static int32_t SPI3_InterruptReceive(void *data, uint32_t num)
1994 {
1995 return SPI_InterruptReceive(data, num, &SPI3_InterruptDriverState);
1996 }
1997
SPI3_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1998 static int32_t SPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1999 {
2000 return SPI_InterruptTransfer(data_out, data_in, num, &SPI3_InterruptDriverState);
2001 }
2002
SPI3_InterruptGetCount(void)2003 static uint32_t SPI3_InterruptGetCount(void)
2004 {
2005 return SPI_InterruptGetCount(&SPI3_InterruptDriverState);
2006 }
2007
SPI3_InterruptControl(uint32_t control,uint32_t arg)2008 static int32_t SPI3_InterruptControl(uint32_t control, uint32_t arg)
2009 {
2010 return SPI_InterruptControl(control, arg, &SPI3_InterruptDriverState);
2011 }
2012
SPI3_InterruptGetStatus(void)2013 static ARM_SPI_STATUS SPI3_InterruptGetStatus(void)
2014 {
2015 return SPI_InterruptGetStatus(&SPI3_InterruptDriverState);
2016 }
2017
2018 #endif
2019
2020 ARM_DRIVER_SPI Driver_SPI3 = {SPIx_GetVersion, SPIx_GetCapabilities,
2021 #if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN
2022 SPI3_DMAInitialize, SPI3_DMAUninitialize, SPI3_DMAPowerControl, SPI3_DMASend,
2023 SPI3_DMAReceive, SPI3_DMATransfer, SPI3_DMAGetCount, SPI3_DMAControl,
2024 SPI3_DMAGetStatus
2025 #else
2026 SPI3_InterruptInitialize,
2027 SPI3_InterruptUninitialize,
2028 SPI3_InterruptPowerControl,
2029 SPI3_InterruptSend,
2030 SPI3_InterruptReceive,
2031 SPI3_InterruptTransfer,
2032 SPI3_InterruptGetCount,
2033 SPI3_InterruptControl,
2034 SPI3_InterruptGetStatus
2035 #endif
2036 };
2037
2038 #endif /* SPI3 */
2039
2040 #if defined(SPI4) && defined(RTE_SPI4) && RTE_SPI4
2041
2042 /* User needs to provide the implementation for SPI4_GetFreq/InitPins/DeinitPins
2043 in the application for enabling according instance. */
2044 extern uint32_t SPI4_GetFreq(void);
2045
2046 static cmsis_spi_resource_t SPI4_Resource = {SPI4, 4, SPI4_GetFreq};
2047
2048 #if defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN
2049
2050 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2051
2052 static cmsis_spi_dma_resource_t SPI4_DMAResource = {RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH,
2053 RTE_SPI4_DMA_RX_DMA_BASE, RTE_SPI4_DMA_RX_CH};
2054
2055 static cmsis_spi_dma_handle_t SPI4_DmaHandle;
2056 static dma_handle_t SPI4_DmaTxDataHandle;
2057 static dma_handle_t SPI4_DmaRxDataHandle;
2058
2059 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2060 ARMCC_SECTION("spi4_dma_driver_state")
2061 static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = {
2062 #else
2063 static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = {
2064 #endif
2065 &SPI4_Resource, &SPI4_DMAResource, &SPI4_DmaHandle, &SPI4_DmaRxDataHandle, &SPI4_DmaTxDataHandle,
2066 };
2067
SPI4_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)2068 static int32_t SPI4_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
2069 {
2070 #ifdef RTE_SPI4_PIN_INIT
2071 RTE_SPI4_PIN_INIT();
2072 #endif
2073 return SPI_DMAInitialize(cb_event, &SPI4_DMADriverState);
2074 }
2075
SPI4_DMAUninitialize(void)2076 static int32_t SPI4_DMAUninitialize(void)
2077 {
2078 #ifdef RTE_SPI4_PIN_DEINIT
2079 RTE_SPI4_PIN_DEINIT();
2080 #endif
2081 return SPI_DMAUninitialize(&SPI4_DMADriverState);
2082 }
2083
SPI4_DMAPowerControl(ARM_POWER_STATE state)2084 static int32_t SPI4_DMAPowerControl(ARM_POWER_STATE state)
2085 {
2086 return SPI_DMAPowerControl(state, &SPI4_DMADriverState);
2087 }
2088
SPI4_DMASend(const void * data,uint32_t num)2089 static int32_t SPI4_DMASend(const void *data, uint32_t num)
2090 {
2091 return SPI_DMASend(data, num, &SPI4_DMADriverState);
2092 }
2093
SPI4_DMAReceive(void * data,uint32_t num)2094 static int32_t SPI4_DMAReceive(void *data, uint32_t num)
2095 {
2096 return SPI_DMAReceive(data, num, &SPI4_DMADriverState);
2097 }
2098
SPI4_DMATransfer(const void * data_out,void * data_in,uint32_t num)2099 static int32_t SPI4_DMATransfer(const void *data_out, void *data_in, uint32_t num)
2100 {
2101 return SPI_DMATransfer(data_out, data_in, num, &SPI4_DMADriverState);
2102 }
2103
SPI4_DMAGetCount(void)2104 static uint32_t SPI4_DMAGetCount(void)
2105 {
2106 return SPI_DMAGetCount(&SPI4_DMADriverState);
2107 }
2108
SPI4_DMAControl(uint32_t control,uint32_t arg)2109 static int32_t SPI4_DMAControl(uint32_t control, uint32_t arg)
2110 {
2111 return SPI_DMAControl(control, arg, &SPI4_DMADriverState);
2112 }
2113
SPI4_DMAGetStatus(void)2114 static ARM_SPI_STATUS SPI4_DMAGetStatus(void)
2115 {
2116 return SPI_DMAGetStatus(&SPI4_DMADriverState);
2117 }
2118
2119 #endif
2120
2121 #else
2122
2123 static cmsis_spi_handle_t SPI4_Handle;
2124
2125 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2126 ARMCC_SECTION("spi4_interrupt_driver_state")
2127 static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = {
2128 #else
2129 static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = {
2130 #endif
2131 &SPI4_Resource,
2132 &SPI4_Handle,
2133 };
2134
SPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2135 static int32_t SPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2136 {
2137 #ifdef RTE_SPI4_PIN_INIT
2138 RTE_SPI4_PIN_INIT();
2139 #endif
2140 return SPI_InterruptInitialize(cb_event, &SPI4_InterruptDriverState);
2141 }
2142
SPI4_InterruptUninitialize(void)2143 static int32_t SPI4_InterruptUninitialize(void)
2144 {
2145 #ifdef RTE_SPI4_PIN_DEINIT
2146 RTE_SPI4_PIN_DEINIT();
2147 #endif
2148 return SPI_InterruptUninitialize(&SPI4_InterruptDriverState);
2149 }
2150
SPI4_InterruptPowerControl(ARM_POWER_STATE state)2151 static int32_t SPI4_InterruptPowerControl(ARM_POWER_STATE state)
2152 {
2153 return SPI_InterruptPowerControl(state, &SPI4_InterruptDriverState);
2154 }
2155
SPI4_InterruptSend(const void * data,uint32_t num)2156 static int32_t SPI4_InterruptSend(const void *data, uint32_t num)
2157 {
2158 return SPI_InterruptSend(data, num, &SPI4_InterruptDriverState);
2159 }
2160
SPI4_InterruptReceive(void * data,uint32_t num)2161 static int32_t SPI4_InterruptReceive(void *data, uint32_t num)
2162 {
2163 return SPI_InterruptReceive(data, num, &SPI4_InterruptDriverState);
2164 }
2165
SPI4_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2166 static int32_t SPI4_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2167 {
2168 return SPI_InterruptTransfer(data_out, data_in, num, &SPI4_InterruptDriverState);
2169 }
2170
SPI4_InterruptGetCount(void)2171 static uint32_t SPI4_InterruptGetCount(void)
2172 {
2173 return SPI_InterruptGetCount(&SPI4_InterruptDriverState);
2174 }
2175
SPI4_InterruptControl(uint32_t control,uint32_t arg)2176 static int32_t SPI4_InterruptControl(uint32_t control, uint32_t arg)
2177 {
2178 return SPI_InterruptControl(control, arg, &SPI4_InterruptDriverState);
2179 }
2180
SPI4_InterruptGetStatus(void)2181 static ARM_SPI_STATUS SPI4_InterruptGetStatus(void)
2182 {
2183 return SPI_InterruptGetStatus(&SPI4_InterruptDriverState);
2184 }
2185
2186 #endif
2187
2188 ARM_DRIVER_SPI Driver_SPI4 = {SPIx_GetVersion, SPIx_GetCapabilities,
2189 #if defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN
2190 SPI4_DMAInitialize, SPI4_DMAUninitialize, SPI4_DMAPowerControl, SPI4_DMASend,
2191 SPI4_DMAReceive, SPI4_DMATransfer, SPI4_DMAGetCount, SPI4_DMAControl,
2192 SPI4_DMAGetStatus
2193 #else
2194 SPI4_InterruptInitialize,
2195 SPI4_InterruptUninitialize,
2196 SPI4_InterruptPowerControl,
2197 SPI4_InterruptSend,
2198 SPI4_InterruptReceive,
2199 SPI4_InterruptTransfer,
2200 SPI4_InterruptGetCount,
2201 SPI4_InterruptControl,
2202 SPI4_InterruptGetStatus
2203 #endif
2204 };
2205
2206 #endif /* SPI4 */
2207
2208 #if defined(SPI5) && defined(RTE_SPI5) && RTE_SPI5
2209
2210 /* User needs to provide the implementation for SPI5_GetFreq/InitPins/DeinitPins
2211 in the application for enabling according instance. */
2212 extern uint32_t SPI5_GetFreq(void);
2213
2214 static cmsis_spi_resource_t SPI5_Resource = {SPI5, 5, SPI5_GetFreq};
2215
2216 #if defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN
2217
2218 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2219
2220 static cmsis_spi_dma_resource_t SPI5_DMAResource = {RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH,
2221 RTE_SPI5_DMA_RX_DMA_BASE, RTE_SPI5_DMA_RX_CH};
2222
2223 static cmsis_spi_dma_handle_t SPI5_DmaHandle;
2224 static dma_handle_t SPI5_DmaTxDataHandle;
2225 static dma_handle_t SPI5_DmaRxDataHandle;
2226
2227 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2228 ARMCC_SECTION("spi5_dma_driver_state")
2229 static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = {
2230 #else
2231 static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = {
2232 #endif
2233 &SPI5_Resource, &SPI5_DMAResource, &SPI5_DmaHandle, &SPI5_DmaRxDataHandle, &SPI5_DmaTxDataHandle,
2234 };
2235
SPI5_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)2236 static int32_t SPI5_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
2237 {
2238 #ifdef RTE_SPI5_PIN_INIT
2239 RTE_SPI5_PIN_INIT();
2240 #endif
2241 return SPI_DMAInitialize(cb_event, &SPI5_DMADriverState);
2242 }
2243
SPI5_DMAUninitialize(void)2244 static int32_t SPI5_DMAUninitialize(void)
2245 {
2246 #ifdef RTE_SPI5_PIN_DEINIT
2247 RTE_SPI5_PIN_DEINIT();
2248 #endif
2249 return SPI_DMAUninitialize(&SPI5_DMADriverState);
2250 }
2251
SPI5_DMAPowerControl(ARM_POWER_STATE state)2252 static int32_t SPI5_DMAPowerControl(ARM_POWER_STATE state)
2253 {
2254 return SPI_DMAPowerControl(state, &SPI5_DMADriverState);
2255 }
2256
SPI5_DMASend(const void * data,uint32_t num)2257 static int32_t SPI5_DMASend(const void *data, uint32_t num)
2258 {
2259 return SPI_DMASend(data, num, &SPI5_DMADriverState);
2260 }
2261
SPI5_DMAReceive(void * data,uint32_t num)2262 static int32_t SPI5_DMAReceive(void *data, uint32_t num)
2263 {
2264 return SPI_DMAReceive(data, num, &SPI5_DMADriverState);
2265 }
2266
SPI5_DMATransfer(const void * data_out,void * data_in,uint32_t num)2267 static int32_t SPI5_DMATransfer(const void *data_out, void *data_in, uint32_t num)
2268 {
2269 return SPI_DMATransfer(data_out, data_in, num, &SPI5_DMADriverState);
2270 }
2271
SPI5_DMAGetCount(void)2272 static uint32_t SPI5_DMAGetCount(void)
2273 {
2274 return SPI_DMAGetCount(&SPI5_DMADriverState);
2275 }
2276
SPI5_DMAControl(uint32_t control,uint32_t arg)2277 static int32_t SPI5_DMAControl(uint32_t control, uint32_t arg)
2278 {
2279 return SPI_DMAControl(control, arg, &SPI5_DMADriverState);
2280 }
2281
SPI5_DMAGetStatus(void)2282 static ARM_SPI_STATUS SPI5_DMAGetStatus(void)
2283 {
2284 return SPI_DMAGetStatus(&SPI5_DMADriverState);
2285 }
2286
2287 #endif
2288
2289 #else
2290
2291 static cmsis_spi_handle_t SPI5_Handle;
2292
2293 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2294 ARMCC_SECTION("spi5_interrupt_driver_state")
2295 static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = {
2296 #else
2297 static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = {
2298 #endif
2299 &SPI5_Resource,
2300 &SPI5_Handle,
2301 };
2302
SPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2303 static int32_t SPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2304 {
2305 #ifdef RTE_SPI5_PIN_INIT
2306 RTE_SPI5_PIN_INIT();
2307 #endif
2308 return SPI_InterruptInitialize(cb_event, &SPI5_InterruptDriverState);
2309 }
2310
SPI5_InterruptUninitialize(void)2311 static int32_t SPI5_InterruptUninitialize(void)
2312 {
2313 #ifdef RTE_SPI5_PIN_DEINIT
2314 RTE_SPI5_PIN_DEINIT();
2315 #endif
2316 return SPI_InterruptUninitialize(&SPI5_InterruptDriverState);
2317 }
2318
SPI5_InterruptPowerControl(ARM_POWER_STATE state)2319 static int32_t SPI5_InterruptPowerControl(ARM_POWER_STATE state)
2320 {
2321 return SPI_InterruptPowerControl(state, &SPI5_InterruptDriverState);
2322 }
2323
SPI5_InterruptSend(const void * data,uint32_t num)2324 static int32_t SPI5_InterruptSend(const void *data, uint32_t num)
2325 {
2326 return SPI_InterruptSend(data, num, &SPI5_InterruptDriverState);
2327 }
2328
SPI5_InterruptReceive(void * data,uint32_t num)2329 static int32_t SPI5_InterruptReceive(void *data, uint32_t num)
2330 {
2331 return SPI_InterruptReceive(data, num, &SPI5_InterruptDriverState);
2332 }
2333
SPI5_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2334 static int32_t SPI5_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2335 {
2336 return SPI_InterruptTransfer(data_out, data_in, num, &SPI5_InterruptDriverState);
2337 }
2338
SPI5_InterruptGetCount(void)2339 static uint32_t SPI5_InterruptGetCount(void)
2340 {
2341 return SPI_InterruptGetCount(&SPI5_InterruptDriverState);
2342 }
2343
SPI5_InterruptControl(uint32_t control,uint32_t arg)2344 static int32_t SPI5_InterruptControl(uint32_t control, uint32_t arg)
2345 {
2346 return SPI_InterruptControl(control, arg, &SPI5_InterruptDriverState);
2347 }
2348
SPI5_InterruptGetStatus(void)2349 static ARM_SPI_STATUS SPI5_InterruptGetStatus(void)
2350 {
2351 return SPI_InterruptGetStatus(&SPI5_InterruptDriverState);
2352 }
2353
2354 #endif
2355
2356 ARM_DRIVER_SPI Driver_SPI5 = {SPIx_GetVersion, SPIx_GetCapabilities,
2357 #if defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN
2358 SPI5_DMAInitialize, SPI5_DMAUninitialize, SPI5_DMAPowerControl, SPI5_DMASend,
2359 SPI5_DMAReceive, SPI5_DMATransfer, SPI5_DMAGetCount, SPI5_DMAControl,
2360 SPI5_DMAGetStatus
2361 #else
2362 SPI5_InterruptInitialize,
2363 SPI5_InterruptUninitialize,
2364 SPI5_InterruptPowerControl,
2365 SPI5_InterruptSend,
2366 SPI5_InterruptReceive,
2367 SPI5_InterruptTransfer,
2368 SPI5_InterruptGetCount,
2369 SPI5_InterruptControl,
2370 SPI5_InterruptGetStatus
2371 #endif
2372 };
2373
2374 #endif /* SPI5 */
2375
2376 #if defined(SPI6) && defined(RTE_SPI6) && RTE_SPI6
2377
2378 /* User needs to provide the implementation for SPI6_GetFreq/InitPins/DeinitPins
2379 in the application for enabling according instance. */
2380 extern uint32_t SPI6_GetFreq(void);
2381
2382 static cmsis_spi_resource_t SPI6_Resource = {SPI6, 6, SPI6_GetFreq};
2383
2384 #if defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN
2385
2386 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2387
2388 static cmsis_spi_dma_resource_t SPI6_DMAResource = {RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH,
2389 RTE_SPI6_DMA_RX_DMA_BASE, RTE_SPI6_DMA_RX_CH};
2390
2391 static cmsis_spi_dma_handle_t SPI6_DmaHandle;
2392 static dma_handle_t SPI6_DmaTxDataHandle;
2393 static dma_handle_t SPI6_DmaRxDataHandle;
2394
2395 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2396 ARMCC_SECTION("spi6_dma_driver_state")
2397 static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = {
2398 #else
2399 static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = {
2400 #endif
2401 &SPI6_Resource, &SPI6_DMAResource, &SPI6_DmaHandle, &SPI6_DmaRxDataHandle, &SPI6_DmaTxDataHandle,
2402 };
2403
SPI6_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)2404 static int32_t SPI6_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
2405 {
2406 #ifdef RTE_SPI6_PIN_INIT
2407 RTE_SPI6_PIN_INIT();
2408 #endif
2409 return SPI_DMAInitialize(cb_event, &SPI6_DMADriverState);
2410 }
2411
SPI6_DMAUninitialize(void)2412 static int32_t SPI6_DMAUninitialize(void)
2413 {
2414 #ifdef RTE_SPI6_PIN_DEINIT
2415 RTE_SPI6_PIN_DEINIT();
2416 #endif
2417 return SPI_DMAUninitialize(&SPI6_DMADriverState);
2418 }
2419
SPI6_DMAPowerControl(ARM_POWER_STATE state)2420 static int32_t SPI6_DMAPowerControl(ARM_POWER_STATE state)
2421 {
2422 return SPI_DMAPowerControl(state, &SPI6_DMADriverState);
2423 }
2424
SPI6_DMASend(const void * data,uint32_t num)2425 static int32_t SPI6_DMASend(const void *data, uint32_t num)
2426 {
2427 return SPI_DMASend(data, num, &SPI6_DMADriverState);
2428 }
2429
SPI6_DMAReceive(void * data,uint32_t num)2430 static int32_t SPI6_DMAReceive(void *data, uint32_t num)
2431 {
2432 return SPI_DMAReceive(data, num, &SPI6_DMADriverState);
2433 }
2434
SPI6_DMATransfer(const void * data_out,void * data_in,uint32_t num)2435 static int32_t SPI6_DMATransfer(const void *data_out, void *data_in, uint32_t num)
2436 {
2437 return SPI_DMATransfer(data_out, data_in, num, &SPI6_DMADriverState);
2438 }
2439
SPI6_DMAGetCount(void)2440 static uint32_t SPI6_DMAGetCount(void)
2441 {
2442 return SPI_DMAGetCount(&SPI6_DMADriverState);
2443 }
2444
SPI6_DMAControl(uint32_t control,uint32_t arg)2445 static int32_t SPI6_DMAControl(uint32_t control, uint32_t arg)
2446 {
2447 return SPI_DMAControl(control, arg, &SPI6_DMADriverState);
2448 }
2449
SPI6_DMAGetStatus(void)2450 static ARM_SPI_STATUS SPI6_DMAGetStatus(void)
2451 {
2452 return SPI_DMAGetStatus(&SPI6_DMADriverState);
2453 }
2454
2455 #endif
2456
2457 #else
2458
2459 static cmsis_spi_handle_t SPI6_Handle;
2460
2461 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2462 ARMCC_SECTION("spi6_interrupt_driver_state")
2463 static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = {
2464 #else
2465 static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = {
2466 #endif
2467 &SPI6_Resource,
2468 &SPI6_Handle,
2469 };
2470
SPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2471 static int32_t SPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2472 {
2473 #ifdef RTE_SPI6_PIN_INIT
2474 RTE_SPI6_PIN_INIT();
2475 #endif
2476 return SPI_InterruptInitialize(cb_event, &SPI6_InterruptDriverState);
2477 }
2478
SPI6_InterruptUninitialize(void)2479 static int32_t SPI6_InterruptUninitialize(void)
2480 {
2481 #ifdef RTE_SPI6_PIN_DEINIT
2482 RTE_SPI6_PIN_DEINIT();
2483 #endif
2484 return SPI_InterruptUninitialize(&SPI6_InterruptDriverState);
2485 }
2486
SPI6_InterruptPowerControl(ARM_POWER_STATE state)2487 static int32_t SPI6_InterruptPowerControl(ARM_POWER_STATE state)
2488 {
2489 return SPI_InterruptPowerControl(state, &SPI6_InterruptDriverState);
2490 }
2491
SPI6_InterruptSend(const void * data,uint32_t num)2492 static int32_t SPI6_InterruptSend(const void *data, uint32_t num)
2493 {
2494 return SPI_InterruptSend(data, num, &SPI6_InterruptDriverState);
2495 }
2496
SPI6_InterruptReceive(void * data,uint32_t num)2497 static int32_t SPI6_InterruptReceive(void *data, uint32_t num)
2498 {
2499 return SPI_InterruptReceive(data, num, &SPI6_InterruptDriverState);
2500 }
2501
SPI6_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2502 static int32_t SPI6_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2503 {
2504 return SPI_InterruptTransfer(data_out, data_in, num, &SPI6_InterruptDriverState);
2505 }
2506
SPI6_InterruptGetCount(void)2507 static uint32_t SPI6_InterruptGetCount(void)
2508 {
2509 return SPI_InterruptGetCount(&SPI6_InterruptDriverState);
2510 }
2511
SPI6_InterruptControl(uint32_t control,uint32_t arg)2512 static int32_t SPI6_InterruptControl(uint32_t control, uint32_t arg)
2513 {
2514 return SPI_InterruptControl(control, arg, &SPI6_InterruptDriverState);
2515 }
2516
SPI6_InterruptGetStatus(void)2517 static ARM_SPI_STATUS SPI6_InterruptGetStatus(void)
2518 {
2519 return SPI_InterruptGetStatus(&SPI6_InterruptDriverState);
2520 }
2521
2522 #endif
2523
2524 ARM_DRIVER_SPI Driver_SPI6 = {SPIx_GetVersion, SPIx_GetCapabilities,
2525 #if defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN
2526 SPI6_DMAInitialize, SPI6_DMAUninitialize, SPI6_DMAPowerControl, SPI6_DMASend,
2527 SPI6_DMAReceive, SPI6_DMATransfer, SPI6_DMAGetCount, SPI6_DMAControl,
2528 SPI6_DMAGetStatus
2529 #else
2530 SPI6_InterruptInitialize,
2531 SPI6_InterruptUninitialize,
2532 SPI6_InterruptPowerControl,
2533 SPI6_InterruptSend,
2534 SPI6_InterruptReceive,
2535 SPI6_InterruptTransfer,
2536 SPI6_InterruptGetCount,
2537 SPI6_InterruptControl,
2538 SPI6_InterruptGetStatus
2539 #endif
2540 };
2541
2542 #endif /* SPI6 */
2543
2544 #if defined(SPI7) && defined(RTE_SPI7) && RTE_SPI7
2545
2546 /* User needs to provide the implementation for SPI7_GetFreq/InitPins/DeinitPins
2547 in the application for enabling according instance. */
2548 extern uint32_t SPI7_GetFreq(void);
2549
2550 static cmsis_spi_resource_t SPI7_Resource = {SPI7, 7, SPI7_GetFreq};
2551
2552 #if defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN
2553
2554 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2555
2556 static cmsis_spi_dma_resource_t SPI7_DMAResource = {RTE_SPI7_DMA_TX_DMA_BASE, RTE_SPI7_DMA_TX_CH,
2557 RTE_SPI7_DMA_RX_DMA_BASE, RTE_SPI7_DMA_RX_CH};
2558
2559 static cmsis_spi_dma_handle_t SPI7_DmaHandle;
2560 static dma_handle_t SPI7_DmaTxDataHandle;
2561 static dma_handle_t SPI7_DmaRxDataHandle;
2562
2563 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2564 ARMCC_SECTION("spi7_dma_driver_state")
2565 static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = {
2566 #else
2567 static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = {
2568 #endif
2569 &SPI7_Resource, &SPI7_DMAResource, &SPI7_DmaHandle, &SPI7_DmaRxDataHandle, &SPI7_DmaTxDataHandle,
2570 };
2571
SPI7_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)2572 static int32_t SPI7_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
2573 {
2574 #ifdef RTE_SPI7_PIN_INIT
2575 RTE_SPI7_PIN_INIT();
2576 #endif
2577 return SPI_DMAInitialize(cb_event, &SPI7_DMADriverState);
2578 }
2579
SPI7_DMAUninitialize(void)2580 static int32_t SPI7_DMAUninitialize(void)
2581 {
2582 #ifdef RTE_SPI7_PIN_DEINIT
2583 RTE_SPI7_PIN_DEINIT();
2584 #endif
2585 return SPI_DMAUninitialize(&SPI7_DMADriverState);
2586 }
2587
SPI7_DMAPowerControl(ARM_POWER_STATE state)2588 static int32_t SPI7_DMAPowerControl(ARM_POWER_STATE state)
2589 {
2590 return SPI_DMAPowerControl(state, &SPI7_DMADriverState);
2591 }
2592
SPI7_DMASend(const void * data,uint32_t num)2593 static int32_t SPI7_DMASend(const void *data, uint32_t num)
2594 {
2595 return SPI_DMASend(data, num, &SPI7_DMADriverState);
2596 }
2597
SPI7_DMAReceive(void * data,uint32_t num)2598 static int32_t SPI7_DMAReceive(void *data, uint32_t num)
2599 {
2600 return SPI_DMAReceive(data, num, &SPI7_DMADriverState);
2601 }
2602
SPI7_DMATransfer(const void * data_out,void * data_in,uint32_t num)2603 static int32_t SPI7_DMATransfer(const void *data_out, void *data_in, uint32_t num)
2604 {
2605 return SPI_DMATransfer(data_out, data_in, num, &SPI7_DMADriverState);
2606 }
2607
SPI7_DMAGetCount(void)2608 static uint32_t SPI7_DMAGetCount(void)
2609 {
2610 return SPI_DMAGetCount(&SPI7_DMADriverState);
2611 }
2612
SPI7_DMAControl(uint32_t control,uint32_t arg)2613 static int32_t SPI7_DMAControl(uint32_t control, uint32_t arg)
2614 {
2615 return SPI_DMAControl(control, arg, &SPI7_DMADriverState);
2616 }
2617
SPI7_DMAGetStatus(void)2618 static ARM_SPI_STATUS SPI7_DMAGetStatus(void)
2619 {
2620 return SPI_DMAGetStatus(&SPI7_DMADriverState);
2621 }
2622
2623 #endif
2624
2625 #else
2626
2627 static cmsis_spi_handle_t SPI7_Handle;
2628
2629 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2630 ARMCC_SECTION("spi7_interrupt_driver_state")
2631 static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = {
2632 #else
2633 static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = {
2634 #endif
2635 &SPI7_Resource,
2636 &SPI7_Handle,
2637 };
2638
SPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2639 static int32_t SPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2640 {
2641 #ifdef RTE_SPI7_PIN_INIT
2642 RTE_SPI7_PIN_INIT();
2643 #endif
2644 return SPI_InterruptInitialize(cb_event, &SPI7_InterruptDriverState);
2645 }
2646
SPI7_InterruptUninitialize(void)2647 static int32_t SPI7_InterruptUninitialize(void)
2648 {
2649 #ifdef RTE_SPI7_PIN_DEINIT
2650 RTE_SPI7_PIN_DEINIT();
2651 #endif
2652 return SPI_InterruptUninitialize(&SPI7_InterruptDriverState);
2653 }
2654
SPI7_InterruptPowerControl(ARM_POWER_STATE state)2655 static int32_t SPI7_InterruptPowerControl(ARM_POWER_STATE state)
2656 {
2657 return SPI_InterruptPowerControl(state, &SPI7_InterruptDriverState);
2658 }
2659
SPI7_InterruptSend(const void * data,uint32_t num)2660 static int32_t SPI7_InterruptSend(const void *data, uint32_t num)
2661 {
2662 return SPI_InterruptSend(data, num, &SPI7_InterruptDriverState);
2663 }
2664
SPI7_InterruptReceive(void * data,uint32_t num)2665 static int32_t SPI7_InterruptReceive(void *data, uint32_t num)
2666 {
2667 return SPI_InterruptReceive(data, num, &SPI7_InterruptDriverState);
2668 }
2669
SPI7_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2670 static int32_t SPI7_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2671 {
2672 return SPI_InterruptTransfer(data_out, data_in, num, &SPI7_InterruptDriverState);
2673 }
2674
SPI7_InterruptGetCount(void)2675 static uint32_t SPI7_InterruptGetCount(void)
2676 {
2677 return SPI_InterruptGetCount(&SPI7_InterruptDriverState);
2678 }
2679
SPI7_InterruptControl(uint32_t control,uint32_t arg)2680 static int32_t SPI7_InterruptControl(uint32_t control, uint32_t arg)
2681 {
2682 return SPI_InterruptControl(control, arg, &SPI7_InterruptDriverState);
2683 }
2684
SPI7_InterruptGetStatus(void)2685 static ARM_SPI_STATUS SPI7_InterruptGetStatus(void)
2686 {
2687 return SPI_InterruptGetStatus(&SPI7_InterruptDriverState);
2688 }
2689
2690 #endif
2691
2692 ARM_DRIVER_SPI Driver_SPI7 = {SPIx_GetVersion, SPIx_GetCapabilities,
2693 #if defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN
2694 SPI7_DMAInitialize, SPI7_DMAUninitialize, SPI7_DMAPowerControl, SPI7_DMASend,
2695 SPI7_DMAReceive, SPI7_DMATransfer, SPI7_DMAGetCount, SPI7_DMAControl,
2696 SPI7_DMAGetStatus
2697 #else
2698 SPI7_InterruptInitialize,
2699 SPI7_InterruptUninitialize,
2700 SPI7_InterruptPowerControl,
2701 SPI7_InterruptSend,
2702 SPI7_InterruptReceive,
2703 SPI7_InterruptTransfer,
2704 SPI7_InterruptGetCount,
2705 SPI7_InterruptControl,
2706 SPI7_InterruptGetStatus
2707 #endif
2708 };
2709
2710 #endif /* SPI7 */
2711
2712 #if defined(SPI8) && defined(RTE_SPI8) && RTE_SPI8
2713
2714 /* User needs to provide the implementation for SPI8_GetFreq/InitPins/DeinitPins
2715 in the application for enabling according instance. */
2716 extern uint32_t SPI8_GetFreq(void);
2717
2718 static cmsis_spi_resource_t SPI8_Resource = {SPI8, 8, SPI8_GetFreq};
2719
2720 #if defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN
2721
2722 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2723
2724 static cmsis_spi_dma_resource_t SPI8_DMAResource = {RTE_SPI8_DMA_TX_DMA_BASE, RTE_SPI8_DMA_TX_CH,
2725 RTE_SPI8_DMA_RX_DMA_BASE, RTE_SPI8_DMA_RX_CH};
2726
2727 static cmsis_spi_dma_handle_t SPI8_DmaHandle;
2728 static dma_handle_t SPI8_DmaTxDataHandle;
2729 static dma_handle_t SPI8_DmaRxDataHandle;
2730
2731 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2732 ARMCC_SECTION("spi8_dma_driver_state")
2733 static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = {
2734 #else
2735 static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = {
2736 #endif
2737 &SPI8_Resource, &SPI8_DMAResource, &SPI8_DmaHandle, &SPI8_DmaRxDataHandle, &SPI8_DmaTxDataHandle,
2738 };
2739
SPI8_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)2740 static int32_t SPI8_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
2741 {
2742 #ifdef RTE_SPI8_PIN_INIT
2743 RTE_SPI8_PIN_INIT();
2744 #endif
2745 return SPI_DMAInitialize(cb_event, &SPI8_DMADriverState);
2746 }
2747
SPI8_DMAUninitialize(void)2748 static int32_t SPI8_DMAUninitialize(void)
2749 {
2750 #ifdef RTE_SPI8_PIN_DEINIT
2751 RTE_SPI8_PIN_DEINIT();
2752 #endif
2753 return SPI_DMAUninitialize(&SPI8_DMADriverState);
2754 }
2755
SPI8_DMAPowerControl(ARM_POWER_STATE state)2756 static int32_t SPI8_DMAPowerControl(ARM_POWER_STATE state)
2757 {
2758 return SPI_DMAPowerControl(state, &SPI8_DMADriverState);
2759 }
2760
SPI8_DMASend(const void * data,uint32_t num)2761 static int32_t SPI8_DMASend(const void *data, uint32_t num)
2762 {
2763 return SPI_DMASend(data, num, &SPI8_DMADriverState);
2764 }
2765
SPI8_DMAReceive(void * data,uint32_t num)2766 static int32_t SPI8_DMAReceive(void *data, uint32_t num)
2767 {
2768 return SPI_DMAReceive(data, num, &SPI8_DMADriverState);
2769 }
2770
SPI8_DMATransfer(const void * data_out,void * data_in,uint32_t num)2771 static int32_t SPI8_DMATransfer(const void *data_out, void *data_in, uint32_t num)
2772 {
2773 return SPI_DMATransfer(data_out, data_in, num, &SPI8_DMADriverState);
2774 }
2775
SPI8_DMAGetCount(void)2776 static uint32_t SPI8_DMAGetCount(void)
2777 {
2778 return SPI_DMAGetCount(&SPI8_DMADriverState);
2779 }
2780
SPI8_DMAControl(uint32_t control,uint32_t arg)2781 static int32_t SPI8_DMAControl(uint32_t control, uint32_t arg)
2782 {
2783 return SPI_DMAControl(control, arg, &SPI8_DMADriverState);
2784 }
2785
SPI8_DMAGetStatus(void)2786 static ARM_SPI_STATUS SPI8_DMAGetStatus(void)
2787 {
2788 return SPI_DMAGetStatus(&SPI8_DMADriverState);
2789 }
2790
2791 #endif
2792
2793 #else
2794
2795 static cmsis_spi_handle_t SPI8_Handle;
2796
2797 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2798 ARMCC_SECTION("spi8_interrupt_driver_state")
2799 static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = {
2800 #else
2801 static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = {
2802 #endif
2803 &SPI8_Resource,
2804 &SPI8_Handle,
2805 };
2806
SPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2807 static int32_t SPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2808 {
2809 #ifdef RTE_SPI8_PIN_INIT
2810 RTE_SPI8_PIN_INIT();
2811 #endif
2812 return SPI_InterruptInitialize(cb_event, &SPI8_InterruptDriverState);
2813 }
2814
SPI8_InterruptUninitialize(void)2815 static int32_t SPI8_InterruptUninitialize(void)
2816 {
2817 #ifdef RTE_SPI8_PIN_DEINIT
2818 RTE_SPI8_PIN_DEINIT();
2819 #endif
2820 return SPI_InterruptUninitialize(&SPI8_InterruptDriverState);
2821 }
2822
SPI8_InterruptPowerControl(ARM_POWER_STATE state)2823 static int32_t SPI8_InterruptPowerControl(ARM_POWER_STATE state)
2824 {
2825 return SPI_InterruptPowerControl(state, &SPI8_InterruptDriverState);
2826 }
2827
SPI8_InterruptSend(const void * data,uint32_t num)2828 static int32_t SPI8_InterruptSend(const void *data, uint32_t num)
2829 {
2830 return SPI_InterruptSend(data, num, &SPI8_InterruptDriverState);
2831 }
2832
SPI8_InterruptReceive(void * data,uint32_t num)2833 static int32_t SPI8_InterruptReceive(void *data, uint32_t num)
2834 {
2835 return SPI_InterruptReceive(data, num, &SPI8_InterruptDriverState);
2836 }
2837
SPI8_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)2838 static int32_t SPI8_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
2839 {
2840 return SPI_InterruptTransfer(data_out, data_in, num, &SPI8_InterruptDriverState);
2841 }
2842
SPI8_InterruptGetCount(void)2843 static uint32_t SPI8_InterruptGetCount(void)
2844 {
2845 return SPI_InterruptGetCount(&SPI8_InterruptDriverState);
2846 }
2847
SPI8_InterruptControl(uint32_t control,uint32_t arg)2848 static int32_t SPI8_InterruptControl(uint32_t control, uint32_t arg)
2849 {
2850 return SPI_InterruptControl(control, arg, &SPI8_InterruptDriverState);
2851 }
2852
SPI8_InterruptGetStatus(void)2853 static ARM_SPI_STATUS SPI8_InterruptGetStatus(void)
2854 {
2855 return SPI_InterruptGetStatus(&SPI8_InterruptDriverState);
2856 }
2857
2858 #endif
2859
2860 ARM_DRIVER_SPI Driver_SPI8 = {SPIx_GetVersion, SPIx_GetCapabilities,
2861 #if defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN
2862 SPI8_DMAInitialize, SPI8_DMAUninitialize, SPI8_DMAPowerControl, SPI8_DMASend,
2863 SPI8_DMAReceive, SPI8_DMATransfer, SPI8_DMAGetCount, SPI8_DMAControl,
2864 SPI8_DMAGetStatus
2865 #else
2866 SPI8_InterruptInitialize,
2867 SPI8_InterruptUninitialize,
2868 SPI8_InterruptPowerControl,
2869 SPI8_InterruptSend,
2870 SPI8_InterruptReceive,
2871 SPI8_InterruptTransfer,
2872 SPI8_InterruptGetCount,
2873 SPI8_InterruptControl,
2874 SPI8_InterruptGetStatus
2875 #endif
2876 };
2877
2878 #endif /* SPI8 */
2879
2880 #if defined(SPI9) && defined(RTE_SPI9) && RTE_SPI9
2881
2882 /* User needs to provide the implementation for SPI9_GetFreq/InitPins/DeinitPins
2883 in the application for enabling according instance. */
2884 extern uint32_t SPI9_GetFreq(void);
2885
2886 static cmsis_spi_resource_t SPI9_Resource = {SPI9, 9, SPI9_GetFreq};
2887
2888 #if defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN
2889
2890 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
2891
2892 static cmsis_spi_dma_resource_t SPI9_DMAResource = {RTE_SPI9_DMA_TX_DMA_BASE, RTE_SPI9_DMA_TX_CH,
2893 RTE_SPI9_DMA_RX_DMA_BASE, RTE_SPI9_DMA_RX_CH};
2894
2895 static cmsis_spi_dma_handle_t SPI9_DmaHandle;
2896 static dma_handle_t SPI9_DmaTxDataHandle;
2897 static dma_handle_t SPI9_DmaRxDataHandle;
2898
2899 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2900 ARMCC_SECTION("spi9_dma_driver_state")
2901 static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = {
2902 #else
2903 static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = {
2904 #endif
2905 &SPI9_Resource, &SPI9_DMAResource, &SPI9_DmaHandle, &SPI9_DmaRxDataHandle, &SPI9_DmaTxDataHandle,
2906 };
2907
SPI9_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)2908 static int32_t SPI9_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
2909 {
2910 #ifdef RTE_SPI9_PIN_INIT
2911 RTE_SPI9_PIN_INIT();
2912 #endif
2913 return SPI_DMAInitialize(cb_event, &SPI9_DMADriverState);
2914 }
2915
SPI9_DMAUninitialize(void)2916 static int32_t SPI9_DMAUninitialize(void)
2917 {
2918 #ifdef RTE_SPI9_PIN_DEINIT
2919 RTE_SPI9_PIN_DEINIT();
2920 #endif
2921 return SPI_DMAUninitialize(&SPI9_DMADriverState);
2922 }
2923
SPI9_DMAPowerControl(ARM_POWER_STATE state)2924 static int32_t SPI9_DMAPowerControl(ARM_POWER_STATE state)
2925 {
2926 return SPI_DMAPowerControl(state, &SPI9_DMADriverState);
2927 }
2928
SPI9_DMASend(const void * data,uint32_t num)2929 static int32_t SPI9_DMASend(const void *data, uint32_t num)
2930 {
2931 return SPI_DMASend(data, num, &SPI9_DMADriverState);
2932 }
2933
SPI9_DMAReceive(void * data,uint32_t num)2934 static int32_t SPI9_DMAReceive(void *data, uint32_t num)
2935 {
2936 return SPI_DMAReceive(data, num, &SPI9_DMADriverState);
2937 }
2938
SPI9_DMATransfer(const void * data_out,void * data_in,uint32_t num)2939 static int32_t SPI9_DMATransfer(const void *data_out, void *data_in, uint32_t num)
2940 {
2941 return SPI_DMATransfer(data_out, data_in, num, &SPI9_DMADriverState);
2942 }
2943
SPI9_DMAGetCount(void)2944 static uint32_t SPI9_DMAGetCount(void)
2945 {
2946 return SPI_DMAGetCount(&SPI9_DMADriverState);
2947 }
2948
SPI9_DMAControl(uint32_t control,uint32_t arg)2949 static int32_t SPI9_DMAControl(uint32_t control, uint32_t arg)
2950 {
2951 return SPI_DMAControl(control, arg, &SPI9_DMADriverState);
2952 }
2953
SPI9_DMAGetStatus(void)2954 static ARM_SPI_STATUS SPI9_DMAGetStatus(void)
2955 {
2956 return SPI_DMAGetStatus(&SPI9_DMADriverState);
2957 }
2958
2959 #endif
2960
2961 #else
2962
2963 static cmsis_spi_handle_t SPI9_Handle;
2964
2965 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
2966 ARMCC_SECTION("spi9_interrupt_driver_state")
2967 static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = {
2968 #else
2969 static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = {
2970 #endif
2971 &SPI9_Resource,
2972 &SPI9_Handle,
2973 };
2974
SPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)2975 static int32_t SPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
2976 {
2977 #ifdef RTE_SPI9_PIN_INIT
2978 RTE_SPI9_PIN_INIT();
2979 #endif
2980 return SPI_InterruptInitialize(cb_event, &SPI9_InterruptDriverState);
2981 }
2982
SPI9_InterruptUninitialize(void)2983 static int32_t SPI9_InterruptUninitialize(void)
2984 {
2985 #ifdef RTE_SPI9_PIN_DEINIT
2986 RTE_SPI9_PIN_DEINIT();
2987 #endif
2988 return SPI_InterruptUninitialize(&SPI9_InterruptDriverState);
2989 }
2990
SPI9_InterruptPowerControl(ARM_POWER_STATE state)2991 static int32_t SPI9_InterruptPowerControl(ARM_POWER_STATE state)
2992 {
2993 return SPI_InterruptPowerControl(state, &SPI9_InterruptDriverState);
2994 }
2995
SPI9_InterruptSend(const void * data,uint32_t num)2996 static int32_t SPI9_InterruptSend(const void *data, uint32_t num)
2997 {
2998 return SPI_InterruptSend(data, num, &SPI9_InterruptDriverState);
2999 }
3000
SPI9_InterruptReceive(void * data,uint32_t num)3001 static int32_t SPI9_InterruptReceive(void *data, uint32_t num)
3002 {
3003 return SPI_InterruptReceive(data, num, &SPI9_InterruptDriverState);
3004 }
3005
SPI9_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3006 static int32_t SPI9_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3007 {
3008 return SPI_InterruptTransfer(data_out, data_in, num, &SPI9_InterruptDriverState);
3009 }
3010
SPI9_InterruptGetCount(void)3011 static uint32_t SPI9_InterruptGetCount(void)
3012 {
3013 return SPI_InterruptGetCount(&SPI9_InterruptDriverState);
3014 }
3015
SPI9_InterruptControl(uint32_t control,uint32_t arg)3016 static int32_t SPI9_InterruptControl(uint32_t control, uint32_t arg)
3017 {
3018 return SPI_InterruptControl(control, arg, &SPI9_InterruptDriverState);
3019 }
3020
SPI9_InterruptGetStatus(void)3021 static ARM_SPI_STATUS SPI9_InterruptGetStatus(void)
3022 {
3023 return SPI_InterruptGetStatus(&SPI9_InterruptDriverState);
3024 }
3025
3026 #endif
3027
3028 ARM_DRIVER_SPI Driver_SPI9 = {SPIx_GetVersion, SPIx_GetCapabilities,
3029 #if defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN
3030 SPI9_DMAInitialize, SPI9_DMAUninitialize, SPI9_DMAPowerControl, SPI9_DMASend,
3031 SPI9_DMAReceive, SPI9_DMATransfer, SPI9_DMAGetCount, SPI9_DMAControl,
3032 SPI9_DMAGetStatus
3033 #else
3034 SPI9_InterruptInitialize,
3035 SPI9_InterruptUninitialize,
3036 SPI9_InterruptPowerControl,
3037 SPI9_InterruptSend,
3038 SPI9_InterruptReceive,
3039 SPI9_InterruptTransfer,
3040 SPI9_InterruptGetCount,
3041 SPI9_InterruptControl,
3042 SPI9_InterruptGetStatus
3043 #endif
3044 };
3045
3046 #endif /* SPI9 */
3047
3048 #if defined(SPI10) && defined(RTE_SPI10) && RTE_SPI10
3049 /* User needs to provide the implementation for SPI10_GetFreq/InitPins/DeinitPins
3050 in the application for enabling according instance. */
3051 extern uint32_t SPI10_GetFreq(void);
3052 static cmsis_spi_resource_t SPI10_Resource = {SPI10, 1, SPI10_GetFreq};
3053
3054 #if RTE_SPI10_DMA_EN
3055
3056 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
3057
3058 static cmsis_spi_dma_resource_t SPI10_DMAResource = {RTE_SPI10_DMA_TX_DMA_BASE, RTE_SPI10_DMA_TX_CH,
3059 RTE_SPI10_DMA_RX_DMA_BASE, RTE_SPI10_DMA_RX_CH};
3060
3061 static cmsis_spi_dma_handle_t SPI10_DmaHandle;
3062 static dma_handle_t SPI10_DmaTxDataHandle;
3063 static dma_handle_t SPI10_DmaRxDataHandle;
3064
3065 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3066 ARMCC_SECTION("spi10_dma_driver_state")
3067 static cmsis_spi_dma_driver_state_t SPI10_DMADriverState = {
3068 #else
3069 static cmsis_spi_dma_driver_state_t SPI10_DMADriverState = {
3070 #endif
3071 &SPI10_Resource, &SPI10_DMAResource, &SPI10_DmaHandle, &SPI10_DmaRxDataHandle, &SPI10_DmaTxDataHandle,
3072 };
3073
SPI10_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)3074 static int32_t SPI10_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
3075 {
3076 #ifdef RTE_SPI10_PIN_INIT
3077 RTE_SPI10_PIN_INIT();
3078 #endif
3079 return SPI_DMAInitialize(cb_event, &SPI10_DMADriverState);
3080 }
3081
SPI10_DMAUninitialize(void)3082 static int32_t SPI10_DMAUninitialize(void)
3083 {
3084 #ifdef RTE_SPI10_PIN_DEINIT
3085 RTE_SPI10_PIN_DEINIT();
3086 #endif
3087 return SPI_DMAUninitialize(&SPI10_DMADriverState);
3088 }
3089
SPI10_DMAPowerControl(ARM_POWER_STATE state)3090 static int32_t SPI10_DMAPowerControl(ARM_POWER_STATE state)
3091 {
3092 return SPI_DMAPowerControl(state, &SPI10_DMADriverState);
3093 }
3094
SPI10_DMASend(const void * data,uint32_t num)3095 static int32_t SPI10_DMASend(const void *data, uint32_t num)
3096 {
3097 return SPI_DMASend(data, num, &SPI10_DMADriverState);
3098 }
3099
SPI10_DMAReceive(void * data,uint32_t num)3100 static int32_t SPI10_DMAReceive(void *data, uint32_t num)
3101 {
3102 return SPI_DMAReceive(data, num, &SPI10_DMADriverState);
3103 }
3104
SPI10_DMATransfer(const void * data_out,void * data_in,uint32_t num)3105 static int32_t SPI10_DMATransfer(const void *data_out, void *data_in, uint32_t num)
3106 {
3107 return SPI_DMATransfer(data_out, data_in, num, &SPI10_DMADriverState);
3108 }
3109
SPI10_DMAGetCount(void)3110 static uint32_t SPI10_DMAGetCount(void)
3111 {
3112 return SPI_DMAGetCount(&SPI10_DMADriverState);
3113 }
3114
SPI10_DMAControl(uint32_t control,uint32_t arg)3115 static int32_t SPI10_DMAControl(uint32_t control, uint32_t arg)
3116 {
3117 return SPI_DMAControl(control, arg, &SPI10_DMADriverState);
3118 }
3119
SPI10_DMAGetStatus(void)3120 static ARM_SPI_STATUS SPI10_DMAGetStatus(void)
3121 {
3122 return SPI_DMAGetStatus(&SPI10_DMADriverState);
3123 }
3124
3125 #endif
3126
3127 #else
3128
3129 static cmsis_spi_handle_t SPI10_Handle;
3130
3131 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3132 ARMCC_SECTION("spi10_interrupt_driver_state")
3133 static cmsis_spi_interrupt_driver_state_t SPI10_InterruptDriverState = {
3134 #else
3135 static cmsis_spi_interrupt_driver_state_t SPI10_InterruptDriverState = {
3136 #endif
3137 &SPI10_Resource,
3138 &SPI10_Handle,
3139 };
3140
SPI10_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3141 static int32_t SPI10_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3142 {
3143 #ifdef RTE_SPI10_PIN_INIT
3144 RTE_SPI10_PIN_INIT();
3145 #endif
3146 return SPI_InterruptInitialize(cb_event, &SPI10_InterruptDriverState);
3147 }
3148
SPI10_InterruptUninitialize(void)3149 static int32_t SPI10_InterruptUninitialize(void)
3150 {
3151 #ifdef RTE_SPI10_PIN_DEINIT
3152 RTE_SPI10_PIN_DEINIT();
3153 #endif
3154 return SPI_InterruptUninitialize(&SPI10_InterruptDriverState);
3155 }
3156
SPI10_InterruptPowerControl(ARM_POWER_STATE state)3157 static int32_t SPI10_InterruptPowerControl(ARM_POWER_STATE state)
3158 {
3159 return SPI_InterruptPowerControl(state, &SPI10_InterruptDriverState);
3160 }
3161
SPI10_InterruptSend(const void * data,uint32_t num)3162 static int32_t SPI10_InterruptSend(const void *data, uint32_t num)
3163 {
3164 return SPI_InterruptSend(data, num, &SPI10_InterruptDriverState);
3165 }
3166
SPI10_InterruptReceive(void * data,uint32_t num)3167 static int32_t SPI10_InterruptReceive(void *data, uint32_t num)
3168 {
3169 return SPI_InterruptReceive(data, num, &SPI10_InterruptDriverState);
3170 }
3171
SPI10_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3172 static int32_t SPI10_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3173 {
3174 return SPI_InterruptTransfer(data_out, data_in, num, &SPI10_InterruptDriverState);
3175 }
3176
SPI10_InterruptGetCount(void)3177 static uint32_t SPI10_InterruptGetCount(void)
3178 {
3179 return SPI_InterruptGetCount(&SPI10_InterruptDriverState);
3180 }
3181
SPI10_InterruptControl(uint32_t control,uint32_t arg)3182 static int32_t SPI10_InterruptControl(uint32_t control, uint32_t arg)
3183 {
3184 return SPI_InterruptControl(control, arg, &SPI10_InterruptDriverState);
3185 }
3186
SPI10_InterruptGetStatus(void)3187 static ARM_SPI_STATUS SPI10_InterruptGetStatus(void)
3188 {
3189 return SPI_InterruptGetStatus(&SPI10_InterruptDriverState);
3190 }
3191
3192 #endif
3193
3194 ARM_DRIVER_SPI Driver_SPI10 = {SPIx_GetVersion, SPIx_GetCapabilities,
3195 #if defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN
3196 SPI10_DMAInitialize, SPI10_DMAUninitialize, SPI10_DMAPowerControl, SPI10_DMASend,
3197 SPI10_DMAReceive, SPI10_DMATransfer, SPI10_DMAGetCount, SPI10_DMAControl,
3198 SPI10_DMAGetStatus
3199 #else
3200 SPI10_InterruptInitialize,
3201 SPI10_InterruptUninitialize,
3202 SPI10_InterruptPowerControl,
3203 SPI10_InterruptSend,
3204 SPI10_InterruptReceive,
3205 SPI10_InterruptTransfer,
3206 SPI10_InterruptGetCount,
3207 SPI10_InterruptControl,
3208 SPI10_InterruptGetStatus
3209 #endif
3210 };
3211
3212 #endif /* SPI10 */
3213
3214 #if defined(SPI11) && defined(RTE_SPI11) && RTE_SPI11
3215 /* User needs to provide the implementation for SPI11_GetFreq/InitPins/DeinitPins
3216 in the application for enabling according instance. */
3217 extern uint32_t SPI11_GetFreq(void);
3218 static cmsis_spi_resource_t SPI11_Resource = {SPI11, 1, SPI11_GetFreq};
3219
3220 #if defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN
3221
3222 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
3223
3224 static cmsis_spi_dma_resource_t SPI11_DMAResource = {RTE_SPI11_DMA_TX_DMA_BASE, RTE_SPI11_DMA_TX_CH,
3225 RTE_SPI11_DMA_RX_DMA_BASE, RTE_SPI11_DMA_RX_CH};
3226
3227 static cmsis_spi_dma_handle_t SPI11_DmaHandle;
3228 static dma_handle_t SPI11_DmaTxDataHandle;
3229 static dma_handle_t SPI11_DmaRxDataHandle;
3230
3231 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3232 ARMCC_SECTION("spi11_dma_driver_state")
3233 static cmsis_spi_dma_driver_state_t SPI11_DMADriverState = {
3234 #else
3235 static cmsis_spi_dma_driver_state_t SPI11_DMADriverState = {
3236 #endif
3237 &SPI11_Resource, &SPI11_DMAResource, &SPI11_DmaHandle, &SPI11_DmaRxDataHandle, &SPI11_DmaTxDataHandle,
3238 };
3239
SPI11_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)3240 static int32_t SPI11_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
3241 {
3242 #ifdef RTE_SPI11_PIN_INIT
3243 RTE_SPI11_PIN_INIT();
3244 #endif
3245 return SPI_DMAInitialize(cb_event, &SPI11_DMADriverState);
3246 }
3247
SPI11_DMAUninitialize(void)3248 static int32_t SPI11_DMAUninitialize(void)
3249 {
3250 #ifdef RTE_SPI11_PIN_DEINIT
3251 RTE_SPI11_PIN_DEINIT();
3252 #endif
3253 return SPI_DMAUninitialize(&SPI11_DMADriverState);
3254 }
3255
SPI11_DMAPowerControl(ARM_POWER_STATE state)3256 static int32_t SPI11_DMAPowerControl(ARM_POWER_STATE state)
3257 {
3258 return SPI_DMAPowerControl(state, &SPI11_DMADriverState);
3259 }
3260
SPI11_DMASend(const void * data,uint32_t num)3261 static int32_t SPI11_DMASend(const void *data, uint32_t num)
3262 {
3263 return SPI_DMASend(data, num, &SPI11_DMADriverState);
3264 }
3265
SPI11_DMAReceive(void * data,uint32_t num)3266 static int32_t SPI11_DMAReceive(void *data, uint32_t num)
3267 {
3268 return SPI_DMAReceive(data, num, &SPI11_DMADriverState);
3269 }
3270
SPI11_DMATransfer(const void * data_out,void * data_in,uint32_t num)3271 static int32_t SPI11_DMATransfer(const void *data_out, void *data_in, uint32_t num)
3272 {
3273 return SPI_DMATransfer(data_out, data_in, num, &SPI11_DMADriverState);
3274 }
3275
SPI11_DMAGetCount(void)3276 static uint32_t SPI11_DMAGetCount(void)
3277 {
3278 return SPI_DMAGetCount(&SPI11_DMADriverState);
3279 }
3280
SPI11_DMAControl(uint32_t control,uint32_t arg)3281 static int32_t SPI11_DMAControl(uint32_t control, uint32_t arg)
3282 {
3283 return SPI_DMAControl(control, arg, &SPI11_DMADriverState);
3284 }
3285
SPI11_DMAGetStatus(void)3286 static ARM_SPI_STATUS SPI11_DMAGetStatus(void)
3287 {
3288 return SPI_DMAGetStatus(&SPI11_DMADriverState);
3289 }
3290
3291 #endif
3292
3293 #else
3294
3295 static cmsis_spi_handle_t SPI11_Handle;
3296
3297 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3298 ARMCC_SECTION("spi11_interrupt_driver_state")
3299 static cmsis_spi_interrupt_driver_state_t SPI11_InterruptDriverState = {
3300 #else
3301 static cmsis_spi_interrupt_driver_state_t SPI11_InterruptDriverState = {
3302 #endif
3303 &SPI11_Resource,
3304 &SPI11_Handle,
3305 };
3306
SPI11_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3307 static int32_t SPI11_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3308 {
3309 #ifdef RTE_SPI11_PIN_INIT
3310 RTE_SPI11_PIN_INIT();
3311 #endif
3312 return SPI_InterruptInitialize(cb_event, &SPI11_InterruptDriverState);
3313 }
3314
SPI11_InterruptUninitialize(void)3315 static int32_t SPI11_InterruptUninitialize(void)
3316 {
3317 #ifdef RTE_SPI11_PIN_DEINIT
3318 RTE_SPI11_PIN_DEINIT();
3319 #endif
3320 return SPI_InterruptUninitialize(&SPI11_InterruptDriverState);
3321 }
3322
SPI11_InterruptPowerControl(ARM_POWER_STATE state)3323 static int32_t SPI11_InterruptPowerControl(ARM_POWER_STATE state)
3324 {
3325 return SPI_InterruptPowerControl(state, &SPI11_InterruptDriverState);
3326 }
3327
SPI11_InterruptSend(const void * data,uint32_t num)3328 static int32_t SPI11_InterruptSend(const void *data, uint32_t num)
3329 {
3330 return SPI_InterruptSend(data, num, &SPI11_InterruptDriverState);
3331 }
3332
SPI11_InterruptReceive(void * data,uint32_t num)3333 static int32_t SPI11_InterruptReceive(void *data, uint32_t num)
3334 {
3335 return SPI_InterruptReceive(data, num, &SPI11_InterruptDriverState);
3336 }
3337
SPI11_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3338 static int32_t SPI11_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3339 {
3340 return SPI_InterruptTransfer(data_out, data_in, num, &SPI11_InterruptDriverState);
3341 }
3342
SPI11_InterruptGetCount(void)3343 static uint32_t SPI11_InterruptGetCount(void)
3344 {
3345 return SPI_InterruptGetCount(&SPI11_InterruptDriverState);
3346 }
3347
SPI11_InterruptControl(uint32_t control,uint32_t arg)3348 static int32_t SPI11_InterruptControl(uint32_t control, uint32_t arg)
3349 {
3350 return SPI_InterruptControl(control, arg, &SPI11_InterruptDriverState);
3351 }
3352
SPI11_InterruptGetStatus(void)3353 static ARM_SPI_STATUS SPI11_InterruptGetStatus(void)
3354 {
3355 return SPI_InterruptGetStatus(&SPI11_InterruptDriverState);
3356 }
3357
3358 #endif
3359
3360 ARM_DRIVER_SPI Driver_SPI11 = {SPIx_GetVersion, SPIx_GetCapabilities,
3361 #if defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN
3362 SPI11_DMAInitialize, SPI11_DMAUninitialize, SPI11_DMAPowerControl, SPI11_DMASend,
3363 SPI11_DMAReceive, SPI11_DMATransfer, SPI11_DMAGetCount, SPI11_DMAControl,
3364 SPI11_DMAGetStatus
3365 #else
3366 SPI11_InterruptInitialize,
3367 SPI11_InterruptUninitialize,
3368 SPI11_InterruptPowerControl,
3369 SPI11_InterruptSend,
3370 SPI11_InterruptReceive,
3371 SPI11_InterruptTransfer,
3372 SPI11_InterruptGetCount,
3373 SPI11_InterruptControl,
3374 SPI11_InterruptGetStatus
3375 #endif
3376 };
3377
3378 #endif /* SPI11 */
3379
3380 #if defined(SPI12) && defined(RTE_SPI12) && RTE_SPI12
3381 /* User needs to provide the implementation for SPI12_GetFreq/InitPins/DeinitPins
3382 in the application for enabling according instance. */
3383 extern uint32_t SPI12_GetFreq(void);
3384 static cmsis_spi_resource_t SPI12_Resource = {SPI12, 1, SPI12_GetFreq};
3385
3386 #if defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN
3387
3388 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
3389
3390 static cmsis_spi_dma_resource_t SPI12_DMAResource = {RTE_SPI12_DMA_TX_DMA_BASE, RTE_SPI12_DMA_TX_CH,
3391 RTE_SPI12_DMA_RX_DMA_BASE, RTE_SPI12_DMA_RX_CH};
3392
3393 static cmsis_spi_dma_handle_t SPI12_DmaHandle;
3394 static dma_handle_t SPI12_DmaTxDataHandle;
3395 static dma_handle_t SPI12_DmaRxDataHandle;
3396
3397 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3398 ARMCC_SECTION("spi12_dma_driver_state")
3399 static cmsis_spi_dma_driver_state_t SPI12_DMADriverState = {
3400 #else
3401 static cmsis_spi_dma_driver_state_t SPI12_DMADriverState = {
3402 #endif
3403 &SPI12_Resource, &SPI12_DMAResource, &SPI12_DmaHandle, &SPI12_DmaRxDataHandle, &SPI12_DmaTxDataHandle,
3404 };
3405
SPI12_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)3406 static int32_t SPI12_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
3407 {
3408 #ifdef RTE_SPI12_PIN_INIT
3409 RTE_SPI12_PIN_INIT();
3410 #endif
3411 return SPI_DMAInitialize(cb_event, &SPI12_DMADriverState);
3412 }
3413
SPI12_DMAUninitialize(void)3414 static int32_t SPI12_DMAUninitialize(void)
3415 {
3416 #ifdef RTE_SPI12_PIN_DEINIT
3417 RTE_SPI12_PIN_DEINIT();
3418 #endif
3419 return SPI_DMAUninitialize(&SPI12_DMADriverState);
3420 }
3421
SPI12_DMAPowerControl(ARM_POWER_STATE state)3422 static int32_t SPI12_DMAPowerControl(ARM_POWER_STATE state)
3423 {
3424 return SPI_DMAPowerControl(state, &SPI12_DMADriverState);
3425 }
3426
SPI12_DMASend(const void * data,uint32_t num)3427 static int32_t SPI12_DMASend(const void *data, uint32_t num)
3428 {
3429 return SPI_DMASend(data, num, &SPI12_DMADriverState);
3430 }
3431
SPI12_DMAReceive(void * data,uint32_t num)3432 static int32_t SPI12_DMAReceive(void *data, uint32_t num)
3433 {
3434 return SPI_DMAReceive(data, num, &SPI12_DMADriverState);
3435 }
3436
SPI12_DMATransfer(const void * data_out,void * data_in,uint32_t num)3437 static int32_t SPI12_DMATransfer(const void *data_out, void *data_in, uint32_t num)
3438 {
3439 return SPI_DMATransfer(data_out, data_in, num, &SPI12_DMADriverState);
3440 }
3441
SPI12_DMAGetCount(void)3442 static uint32_t SPI12_DMAGetCount(void)
3443 {
3444 return SPI_DMAGetCount(&SPI12_DMADriverState);
3445 }
3446
SPI12_DMAControl(uint32_t control,uint32_t arg)3447 static int32_t SPI12_DMAControl(uint32_t control, uint32_t arg)
3448 {
3449 return SPI_DMAControl(control, arg, &SPI12_DMADriverState);
3450 }
3451
SPI12_DMAGetStatus(void)3452 static ARM_SPI_STATUS SPI12_DMAGetStatus(void)
3453 {
3454 return SPI_DMAGetStatus(&SPI12_DMADriverState);
3455 }
3456
3457 #endif
3458
3459 #else
3460
3461 static cmsis_spi_handle_t SPI12_Handle;
3462
3463 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3464 ARMCC_SECTION("spi12_interrupt_driver_state")
3465 static cmsis_spi_interrupt_driver_state_t SPI12_InterruptDriverState = {
3466 #else
3467 static cmsis_spi_interrupt_driver_state_t SPI12_InterruptDriverState = {
3468 #endif
3469 &SPI12_Resource,
3470 &SPI12_Handle,
3471 };
3472
SPI12_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3473 static int32_t SPI12_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3474 {
3475 #ifdef RTE_SPI12_PIN_INIT
3476 RTE_SPI12_PIN_INIT();
3477 #endif
3478 return SPI_InterruptInitialize(cb_event, &SPI12_InterruptDriverState);
3479 }
3480
SPI12_InterruptUninitialize(void)3481 static int32_t SPI12_InterruptUninitialize(void)
3482 {
3483 #ifdef RTE_SPI12_PIN_DEINIT
3484 RTE_SPI12_PIN_DEINIT();
3485 #endif
3486 return SPI_InterruptUninitialize(&SPI12_InterruptDriverState);
3487 }
3488
SPI12_InterruptPowerControl(ARM_POWER_STATE state)3489 static int32_t SPI12_InterruptPowerControl(ARM_POWER_STATE state)
3490 {
3491 return SPI_InterruptPowerControl(state, &SPI12_InterruptDriverState);
3492 }
3493
SPI12_InterruptSend(const void * data,uint32_t num)3494 static int32_t SPI12_InterruptSend(const void *data, uint32_t num)
3495 {
3496 return SPI_InterruptSend(data, num, &SPI12_InterruptDriverState);
3497 }
3498
SPI12_InterruptReceive(void * data,uint32_t num)3499 static int32_t SPI12_InterruptReceive(void *data, uint32_t num)
3500 {
3501 return SPI_InterruptReceive(data, num, &SPI12_InterruptDriverState);
3502 }
3503
SPI12_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3504 static int32_t SPI12_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3505 {
3506 return SPI_InterruptTransfer(data_out, data_in, num, &SPI12_InterruptDriverState);
3507 }
3508
SPI12_InterruptGetCount(void)3509 static uint32_t SPI12_InterruptGetCount(void)
3510 {
3511 return SPI_InterruptGetCount(&SPI12_InterruptDriverState);
3512 }
3513
SPI12_InterruptControl(uint32_t control,uint32_t arg)3514 static int32_t SPI12_InterruptControl(uint32_t control, uint32_t arg)
3515 {
3516 return SPI_InterruptControl(control, arg, &SPI12_InterruptDriverState);
3517 }
3518
SPI12_InterruptGetStatus(void)3519 static ARM_SPI_STATUS SPI12_InterruptGetStatus(void)
3520 {
3521 return SPI_InterruptGetStatus(&SPI12_InterruptDriverState);
3522 }
3523
3524 #endif
3525
3526 ARM_DRIVER_SPI Driver_SPI12 = {SPIx_GetVersion, SPIx_GetCapabilities,
3527 #if defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN
3528 SPI12_DMAInitialize, SPI12_DMAUninitialize, SPI12_DMAPowerControl, SPI12_DMASend,
3529 SPI12_DMAReceive, SPI12_DMATransfer, SPI12_DMAGetCount, SPI12_DMAControl,
3530 SPI12_DMAGetStatus
3531 #else
3532 SPI12_InterruptInitialize,
3533 SPI12_InterruptUninitialize,
3534 SPI12_InterruptPowerControl,
3535 SPI12_InterruptSend,
3536 SPI12_InterruptReceive,
3537 SPI12_InterruptTransfer,
3538 SPI12_InterruptGetCount,
3539 SPI12_InterruptControl,
3540 SPI12_InterruptGetStatus
3541 #endif
3542 };
3543
3544 #endif /* SPI12 */
3545
3546 #if defined(SPI13) && defined(RTE_SPI13) && RTE_SPI13
3547 /* User needs to provide the implementation for SPI13_GetFreq/InitPins/DeinitPins
3548 in the application for enabling according instance. */
3549 extern uint32_t SPI13_GetFreq(void);
3550 static cmsis_spi_resource_t SPI13_Resource = {SPI13, 1, SPI13_GetFreq};
3551
3552 #if defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN
3553
3554 #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
3555
3556 static cmsis_spi_dma_resource_t SPI13_DMAResource = {RTE_SPI13_DMA_TX_DMA_BASE, RTE_SPI13_DMA_TX_CH,
3557 RTE_SPI13_DMA_RX_DMA_BASE, RTE_SPI13_DMA_RX_CH};
3558
3559 static cmsis_spi_dma_handle_t SPI13_DmaHandle;
3560 static dma_handle_t SPI13_DmaTxDataHandle;
3561 static dma_handle_t SPI13_DmaRxDataHandle;
3562
3563 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3564 ARMCC_SECTION("spi13_dma_driver_state")
3565 static cmsis_spi_dma_driver_state_t SPI13_DMADriverState = {
3566 #else
3567 static cmsis_spi_dma_driver_state_t SPI13_DMADriverState = {
3568 #endif
3569 &SPI13_Resource, &SPI13_DMAResource, &SPI13_DmaHandle, &SPI13_DmaRxDataHandle, &SPI13_DmaTxDataHandle,
3570 };
3571
SPI13_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)3572 static int32_t SPI13_DMAInitialize(ARM_SPI_SignalEvent_t cb_event)
3573 {
3574 #ifdef RTE_SPI13_PIN_INIT
3575 RTE_SPI13_PIN_INIT();
3576 #endif
3577 return SPI_DMAInitialize(cb_event, &SPI13_DMADriverState);
3578 }
3579
SPI13_DMAUninitialize(void)3580 static int32_t SPI13_DMAUninitialize(void)
3581 {
3582 #ifdef RTE_SPI13_PIN_DEINIT
3583 RTE_SPI13_PIN_DEINIT();
3584 #endif
3585 return SPI_DMAUninitialize(&SPI13_DMADriverState);
3586 }
3587
SPI13_DMAPowerControl(ARM_POWER_STATE state)3588 static int32_t SPI13_DMAPowerControl(ARM_POWER_STATE state)
3589 {
3590 return SPI_DMAPowerControl(state, &SPI13_DMADriverState);
3591 }
3592
SPI13_DMASend(const void * data,uint32_t num)3593 static int32_t SPI13_DMASend(const void *data, uint32_t num)
3594 {
3595 return SPI_DMASend(data, num, &SPI13_DMADriverState);
3596 }
3597
SPI13_DMAReceive(void * data,uint32_t num)3598 static int32_t SPI13_DMAReceive(void *data, uint32_t num)
3599 {
3600 return SPI_DMAReceive(data, num, &SPI13_DMADriverState);
3601 }
3602
SPI13_DMATransfer(const void * data_out,void * data_in,uint32_t num)3603 static int32_t SPI13_DMATransfer(const void *data_out, void *data_in, uint32_t num)
3604 {
3605 return SPI_DMATransfer(data_out, data_in, num, &SPI13_DMADriverState);
3606 }
3607
SPI13_DMAGetCount(void)3608 static uint32_t SPI13_DMAGetCount(void)
3609 {
3610 return SPI_DMAGetCount(&SPI13_DMADriverState);
3611 }
3612
SPI13_DMAControl(uint32_t control,uint32_t arg)3613 static int32_t SPI13_DMAControl(uint32_t control, uint32_t arg)
3614 {
3615 return SPI_DMAControl(control, arg, &SPI13_DMADriverState);
3616 }
3617
SPI13_DMAGetStatus(void)3618 static ARM_SPI_STATUS SPI13_DMAGetStatus(void)
3619 {
3620 return SPI_DMAGetStatus(&SPI13_DMADriverState);
3621 }
3622
3623 #endif
3624
3625 #else
3626
3627 static cmsis_spi_handle_t SPI13_Handle;
3628
3629 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
3630 ARMCC_SECTION("spi13_interrupt_driver_state")
3631 static cmsis_spi_interrupt_driver_state_t SPI13_InterruptDriverState = {
3632 #else
3633 static cmsis_spi_interrupt_driver_state_t SPI13_InterruptDriverState = {
3634 #endif
3635 &SPI13_Resource,
3636 &SPI13_Handle,
3637 };
3638
SPI13_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)3639 static int32_t SPI13_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
3640 {
3641 #ifdef RTE_SPI13_PIN_INIT
3642 RTE_SPI13_PIN_INIT();
3643 #endif
3644 return SPI_InterruptInitialize(cb_event, &SPI13_InterruptDriverState);
3645 }
3646
SPI13_InterruptUninitialize(void)3647 static int32_t SPI13_InterruptUninitialize(void)
3648 {
3649 #ifdef RTE_SPI13_PIN_DEINIT
3650 RTE_SPI13_PIN_DEINIT();
3651 #endif
3652 return SPI_InterruptUninitialize(&SPI13_InterruptDriverState);
3653 }
3654
SPI13_InterruptPowerControl(ARM_POWER_STATE state)3655 static int32_t SPI13_InterruptPowerControl(ARM_POWER_STATE state)
3656 {
3657 return SPI_InterruptPowerControl(state, &SPI13_InterruptDriverState);
3658 }
3659
SPI13_InterruptSend(const void * data,uint32_t num)3660 static int32_t SPI13_InterruptSend(const void *data, uint32_t num)
3661 {
3662 return SPI_InterruptSend(data, num, &SPI13_InterruptDriverState);
3663 }
3664
SPI13_InterruptReceive(void * data,uint32_t num)3665 static int32_t SPI13_InterruptReceive(void *data, uint32_t num)
3666 {
3667 return SPI_InterruptReceive(data, num, &SPI13_InterruptDriverState);
3668 }
3669
SPI13_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)3670 static int32_t SPI13_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
3671 {
3672 return SPI_InterruptTransfer(data_out, data_in, num, &SPI13_InterruptDriverState);
3673 }
3674
SPI13_InterruptGetCount(void)3675 static uint32_t SPI13_InterruptGetCount(void)
3676 {
3677 return SPI_InterruptGetCount(&SPI13_InterruptDriverState);
3678 }
3679
SPI13_InterruptControl(uint32_t control,uint32_t arg)3680 static int32_t SPI13_InterruptControl(uint32_t control, uint32_t arg)
3681 {
3682 return SPI_InterruptControl(control, arg, &SPI13_InterruptDriverState);
3683 }
3684
SPI13_InterruptGetStatus(void)3685 static ARM_SPI_STATUS SPI13_InterruptGetStatus(void)
3686 {
3687 return SPI_InterruptGetStatus(&SPI13_InterruptDriverState);
3688 }
3689
3690 #endif
3691
3692 ARM_DRIVER_SPI Driver_SPI13 = {SPIx_GetVersion, SPIx_GetCapabilities,
3693 #if defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN
3694 SPI13_DMAInitialize, SPI13_DMAUninitialize, SPI13_DMAPowerControl, SPI13_DMASend,
3695 SPI13_DMAReceive, SPI13_DMATransfer, SPI13_DMAGetCount, SPI13_DMAControl,
3696 SPI13_DMAGetStatus
3697 #else
3698 SPI13_InterruptInitialize,
3699 SPI13_InterruptUninitialize,
3700 SPI13_InterruptPowerControl,
3701 SPI13_InterruptSend,
3702 SPI13_InterruptReceive,
3703 SPI13_InterruptTransfer,
3704 SPI13_InterruptGetCount,
3705 SPI13_InterruptControl,
3706 SPI13_InterruptGetStatus
3707 #endif
3708 };
3709
3710 #endif /* SPI13 */
3711
