1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2021 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_ecspi_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.ecspi_cmsis"
26 #endif
27
28 #if ((defined(RTE_SPI1) && RTE_SPI1) || (defined(RTE_SPI2) && RTE_SPI2) || (defined(RTE_SPI3) && RTE_SPI3))
29
30 #define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) /* driver version */
31
32 /*
33 * ARMCC does not support split the data section automatically, so the driver
34 * needs to split the data to separate sections explicitly, to reduce codesize.
35 */
36 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
37 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
38 #endif
39
40 typedef const struct _cmsis_ecspi_resource
41 {
42 ECSPI_Type *base;
43 uint32_t instance;
44 uint32_t (*GetFreq)(void);
45 } cmsis_ecspi_resource_t;
46
47 #if ((defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || \
48 (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN))
49 #if (defined(FSL_FEATURE_SOC_SDMA_COUNT) && FSL_FEATURE_SOC_SDMA_COUNT)
50 typedef const struct _cmsis_ecspi_sdma_resource
51 {
52 SDMAARM_Type *txSdmaBase;
53 uint32_t txSdmaChannel;
54 uint32_t txSdmaRequest;
55 uint8_t txSdmaPriority;
56 sdma_context_data_t *txSdmaContext;
57
58 SDMAARM_Type *rxSdmaBase;
59 uint32_t rxSdmaChannel;
60 uint32_t rxSdmaRequest;
61 uint8_t rxSdmaPriority;
62 sdma_context_data_t *rxSdmaContext;
63 } cmsis_ecspi_sdma_resource_t;
64
65 typedef struct _cmsis_ecspi_sdma_driver_state
66 {
67 cmsis_ecspi_resource_t *resource;
68 cmsis_ecspi_sdma_resource_t *sdmaResource;
69 ecspi_sdma_handle_t *handle;
70 sdma_handle_t *sdmaRxDataHandle;
71 sdma_handle_t *sdmaTxDataHandle;
72
73 uint32_t baudRate_Bps;
74 ARM_SPI_SignalEvent_t cb_event;
75 uint8_t flags; /*!< Control and state flags. */
76 } cmsis_ecspi_sdma_driver_state_t;
77 #endif
78 #else /* SDMA unused. */
79 typedef struct _cmsis_ecspi_interrupt_driver_state
80 {
81 cmsis_ecspi_resource_t *resource;
82 ecspi_master_handle_t *handle;
83 ARM_SPI_SignalEvent_t cb_event;
84 uint32_t baudRate_Bps;
85 uint8_t flags; /*!< Control and state flags. */
86 } cmsis_ecspi_interrupt_driver_state_t;
87 #endif
88
89 /* Driver Version */
90 static const ARM_DRIVER_VERSION s_ECSPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION};
91
92 /* Driver Capabilities */
93 static const ARM_SPI_CAPABILITIES s_ECSPIDriverCapabilities = {
94 1, /* Simplex Mode (Master and Slave) */
95 0, /* TI Synchronous Serial Interface */
96 0, /* Microwire Interface */
97 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
98 };
99
100 /*******************************************************************************
101 * Code
102 ******************************************************************************/
103
ECSPI_MasterCommonControl(uint32_t control,cmsis_ecspi_resource_t * resource,ecspi_master_config_t * masterConfig)104 static void ECSPI_MasterCommonControl(uint32_t control,
105 cmsis_ecspi_resource_t *resource,
106 ecspi_master_config_t *masterConfig)
107 {
108 switch (control & (uint32_t)ARM_SPI_SS_MASTER_MODE_Msk)
109 {
110 /*
111 * Note:
112 * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or
113 * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured
114 * by user in extern file. Besides, ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver.
115 */
116 case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */
117 break;
118 case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */
119 break;
120 case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */
121 break;
122 case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */
123 break;
124 default:
125 /* Avoid MISRA 16.4 violations. */
126 break;
127 }
128
129 /* Configure the channel to be used. Default channel is channel0. */
130 switch (resource->instance)
131 {
132 case 1:
133 #if defined(RTE_SPI1_TRANSFER_CHANNEL)
134 masterConfig->channel = RTE_SPI1_TRANSFER_CHANNEL;
135 #endif
136 break;
137 case 2:
138 #if defined(RTE_SPI2_TRANSFER_CHANNEL)
139 masterConfig->channel = RTE_SPI2_TRANSFER_CHANNEL;
140 #endif
141 break;
142 case 3:
143 #if defined(RTE_SPI3_TRANSFER_CHANNEL)
144 masterConfig->channel = RTE_SPI3_TRANSFER_CHANNEL;
145 #endif
146 break;
147 default:
148 /* Avoid MISRA 16.4 violations. */
149 break;
150 }
151
152 switch (control & (uint32_t)ARM_SPI_FRAME_FORMAT_Msk)
153 {
154 case ARM_SPI_CPOL0_CPHA0:
155 masterConfig->channelConfig.polarity = kECSPI_PolarityActiveHigh;
156 masterConfig->channelConfig.phase = kECSPI_ClockPhaseFirstEdge;
157 break;
158
159 case ARM_SPI_CPOL0_CPHA1:
160 masterConfig->channelConfig.polarity = kECSPI_PolarityActiveHigh;
161 masterConfig->channelConfig.phase = kECSPI_ClockPhaseSecondEdge;
162 break;
163
164 case ARM_SPI_CPOL1_CPHA0:
165 masterConfig->channelConfig.polarity = kECSPI_PolarityActiveLow;
166 masterConfig->channelConfig.phase = kECSPI_ClockPhaseFirstEdge;
167 break;
168
169 case ARM_SPI_CPOL1_CPHA1:
170 masterConfig->channelConfig.polarity = kECSPI_PolarityActiveLow;
171 masterConfig->channelConfig.phase = kECSPI_ClockPhaseSecondEdge;
172 break;
173 default:
174 /* Avoid MISRA 16.4 violations. */
175 break;
176 }
177 /* setting Number of burst length. */
178 if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U)
179 {
180 masterConfig->burstLength = (uint8_t)((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos);
181 }
182 }
183
ECSPI_SlaveCommonControl(uint32_t control,cmsis_ecspi_resource_t * resource,ecspi_slave_config_t * slaveConfig)184 static void ECSPI_SlaveCommonControl(uint32_t control,
185 cmsis_ecspi_resource_t *resource,
186 ecspi_slave_config_t *slaveConfig)
187 {
188 /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */
189 switch (control & (uint32_t)ARM_SPI_SS_SLAVE_MODE_Msk)
190 {
191 case ARM_SPI_SS_SLAVE_HW:
192 break;
193 case ARM_SPI_SS_SLAVE_SW:
194 break;
195 default:
196 /* Avoid MISRA 16.4 violations. */
197 break;
198 }
199
200 /* Configure the channel to be used. Default channel is channel0. */
201 switch (resource->instance)
202 {
203 case 1:
204 #if defined(RTE_SPI1_TRANSFER_CHANNEL)
205 slaveConfig->channel = RTE_SPI1_TRANSFER_CHANNEL;
206 #endif
207 break;
208 case 2:
209 #if defined(RTE_SPI2_TRANSFER_CHANNEL)
210 slaveConfig->channel = RTE_SPI2_TRANSFER_CHANNEL;
211 #endif
212 break;
213 case 3:
214 #if defined(RTE_SPI3_TRANSFER_CHANNEL)
215 slaveConfig->channel = RTE_SPI3_TRANSFER_CHANNEL;
216 #endif
217 break;
218 default:
219 /* Avoid MISRA 16.4 violations. */
220 break;
221 }
222
223 switch (control & (uint32_t)ARM_SPI_FRAME_FORMAT_Msk)
224 {
225 case ARM_SPI_CPOL0_CPHA0:
226 slaveConfig->channelConfig.polarity = kECSPI_PolarityActiveHigh;
227 slaveConfig->channelConfig.phase = kECSPI_ClockPhaseFirstEdge;
228 break;
229
230 case ARM_SPI_CPOL0_CPHA1:
231 slaveConfig->channelConfig.polarity = kECSPI_PolarityActiveHigh;
232 slaveConfig->channelConfig.phase = kECSPI_ClockPhaseSecondEdge;
233 break;
234
235 case ARM_SPI_CPOL1_CPHA0:
236 slaveConfig->channelConfig.polarity = kECSPI_PolarityActiveLow;
237 slaveConfig->channelConfig.phase = kECSPI_ClockPhaseFirstEdge;
238 break;
239
240 case ARM_SPI_CPOL1_CPHA1:
241 slaveConfig->channelConfig.polarity = kECSPI_PolarityActiveLow;
242 slaveConfig->channelConfig.phase = kECSPI_ClockPhaseSecondEdge;
243 break;
244 default:
245 /* Avoid MISRA 16.4 violations. */
246 break;
247 }
248
249 if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */
250 {
251 slaveConfig->burstLength = (uint8_t)((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos);
252 }
253 }
254
ECSPIx_GetVersion(void)255 static ARM_DRIVER_VERSION ECSPIx_GetVersion(void)
256 {
257 return s_ECSPIDriverVersion;
258 }
259
ECSPIx_GetCapabilities(void)260 static ARM_SPI_CAPABILITIES ECSPIx_GetCapabilities(void)
261 {
262 return s_ECSPIDriverCapabilities;
263 }
264
265 #endif
266
267 #if ((defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || \
268 (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN))
269
270 #if (defined(FSL_FEATURE_SOC_SDMA_COUNT) && FSL_FEATURE_SOC_SDMA_COUNT)
271
KSDK_ECSPI_MasterSDMACallback(ECSPI_Type * base,ecspi_sdma_handle_t * handle,status_t status,void * userData)272 static void KSDK_ECSPI_MasterSDMACallback(ECSPI_Type *base,
273 ecspi_sdma_handle_t *handle,
274 status_t status,
275 void *userData)
276 {
277 uint32_t event = 0U;
278
279 if (kStatus_Success == status)
280 {
281 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
282 }
283
284 /* User data is actually CMSIS driver callback. */
285 if (userData != NULL)
286 {
287 ((ARM_SPI_SignalEvent_t)userData)(event);
288 }
289 }
KSDK_ECSPI_SlaveSDMACallback(ECSPI_Type * base,ecspi_sdma_handle_t * handle,status_t status,void * userData)290 static void KSDK_ECSPI_SlaveSDMACallback(ECSPI_Type *base, ecspi_sdma_handle_t *handle, status_t status, void *userData)
291 {
292 uint32_t event = 0U;
293
294 if (kStatus_Success == status)
295 {
296 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
297 }
298
299 /* User data is actually CMSIS driver callback. */
300 if (userData != NULL)
301 {
302 ((ARM_SPI_SignalEvent_t)userData)(event);
303 }
304 }
305
ECSPI_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_ecspi_sdma_driver_state_t * ecspi)306 static int32_t ECSPI_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_ecspi_sdma_driver_state_t *ecspi)
307 {
308 if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_INIT))
309 {
310 ecspi->cb_event = cb_event;
311 ecspi->flags = (uint8_t)SPI_FLAG_INIT;
312 }
313 return ARM_DRIVER_OK;
314 }
315
ECSPI_SDMAUninitialize(cmsis_ecspi_sdma_driver_state_t * ecspi)316 static int32_t ECSPI_SDMAUninitialize(cmsis_ecspi_sdma_driver_state_t *ecspi)
317 {
318 ecspi->flags = (uint8_t)SPI_FLAG_UNINIT;
319 return ARM_DRIVER_OK;
320 }
321
ECSPI_SDMAPowerControl(ARM_POWER_STATE state,cmsis_ecspi_sdma_driver_state_t * ecspi)322 static int32_t ECSPI_SDMAPowerControl(ARM_POWER_STATE state, cmsis_ecspi_sdma_driver_state_t *ecspi)
323 {
324 int32_t result = ARM_DRIVER_OK;
325
326 switch (state)
327 {
328 case ARM_POWER_OFF:
329 if ((ecspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
330 {
331 ECSPI_Deinit(ecspi->resource->base);
332 ecspi->flags &= ~(uint8_t)SPI_FLAG_POWER;
333 }
334 break;
335 case ARM_POWER_LOW:
336 result = ARM_DRIVER_ERROR_UNSUPPORTED;
337 break;
338
339 case ARM_POWER_FULL:
340 if (ecspi->flags == (uint8_t)SPI_FLAG_UNINIT)
341 {
342 result = ARM_DRIVER_ERROR;
343 break;
344 }
345 if ((ecspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
346 {
347 /* Driver already powered */
348 break;
349 }
350 ecspi->flags |= (uint8_t)SPI_FLAG_POWER;
351 break;
352 default:
353 result = ARM_DRIVER_ERROR_UNSUPPORTED;
354 break;
355 }
356 return result;
357 }
358
ECSPI_SDMASend(const void * data,uint32_t num,cmsis_ecspi_sdma_driver_state_t * ecspi)359 static int32_t ECSPI_SDMASend(const void *data, uint32_t num, cmsis_ecspi_sdma_driver_state_t *ecspi)
360 {
361 int32_t ret;
362 status_t status;
363 ecspi_transfer_t xfer = {0};
364 uint32_t datawidth =
365 (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT;
366
367 xfer.rxData = NULL;
368 xfer.txData = (uint32_t *)data;
369 xfer.dataSize = num * ((datawidth + 8U) / 8U);
370 xfer.channel = kECSPI_Channel0;
371
372 /* Configure the channel to be used. */
373 switch (ecspi->resource->instance)
374 {
375 case 1:
376 #if defined(RTE_SPI1_TRANSFER_CHANNEL)
377 xfer.channel = RTE_SPI1_TRANSFER_CHANNEL;
378 #endif
379 break;
380 case 2:
381 #if defined(RTE_SPI2_TRANSFER_CHANNEL)
382 xfer.channel = RTE_SPI2_TRANSFER_CHANNEL;
383 #endif
384 break;
385 case 3:
386 #if defined(RTE_SPI3_TRANSFER_CHANNEL)
387 xfer.channel = RTE_SPI3_TRANSFER_CHANNEL;
388 #endif
389 break;
390 default:
391 /* Avoid MISRA 16.4 violations. */
392 break;
393 }
394
395 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
396 {
397 status = ECSPI_MasterTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer);
398 }
399 else
400 {
401 status = ECSPI_SlaveTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer);
402 }
403
404 switch (status)
405 {
406 case kStatus_Success:
407 ret = ARM_DRIVER_OK;
408 break;
409 case kStatus_InvalidArgument:
410 ret = ARM_DRIVER_ERROR_PARAMETER;
411 break;
412 case kStatus_ECSPI_Busy:
413 ret = ARM_DRIVER_ERROR_BUSY;
414 break;
415 default:
416 ret = ARM_DRIVER_ERROR;
417 break;
418 }
419
420 return ret;
421 }
422
ECSPI_SDMAReceive(void * data,uint32_t num,cmsis_ecspi_sdma_driver_state_t * ecspi)423 static int32_t ECSPI_SDMAReceive(void *data, uint32_t num, cmsis_ecspi_sdma_driver_state_t *ecspi)
424 {
425 int32_t ret;
426 status_t status;
427 ecspi_transfer_t xfer = {0};
428 uint32_t datawidth =
429 (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT;
430
431 xfer.txData = NULL;
432 xfer.rxData = (uint32_t *)data;
433 xfer.dataSize = num * ((datawidth + 8U) / 8U);
434 xfer.channel = kECSPI_Channel0;
435
436 /* Configure the channel to be used. */
437 switch (ecspi->resource->instance)
438 {
439 case 1:
440 #if defined(RTE_SPI1_TRANSFER_CHANNEL)
441 xfer.channel = RTE_SPI1_TRANSFER_CHANNEL;
442 #endif
443 break;
444 case 2:
445 #if defined(RTE_SPI2_TRANSFER_CHANNEL)
446 xfer.channel = RTE_SPI2_TRANSFER_CHANNEL;
447 #endif
448 break;
449 case 3:
450 #if defined(RTE_SPI3_TRANSFER_CHANNEL)
451 xfer.channel = RTE_SPI3_TRANSFER_CHANNEL;
452 #endif
453 break;
454 default:
455 /* Avoid MISRA 16.4 violations. */
456 break;
457 }
458
459 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
460 {
461 status = ECSPI_MasterTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer);
462 }
463 else
464 {
465 status = ECSPI_SlaveTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer);
466 }
467
468 switch (status)
469 {
470 case kStatus_Success:
471 ret = ARM_DRIVER_OK;
472 break;
473 case kStatus_InvalidArgument:
474 ret = ARM_DRIVER_ERROR_PARAMETER;
475 break;
476 case kStatus_ECSPI_Busy:
477 ret = ARM_DRIVER_ERROR_BUSY;
478 break;
479 default:
480 ret = ARM_DRIVER_ERROR;
481 break;
482 }
483
484 return ret;
485 }
486
ECSPI_SDMATransfer(const void * data_out,void * data_in,uint32_t num,cmsis_ecspi_sdma_driver_state_t * ecspi)487 static int32_t ECSPI_SDMATransfer(const void *data_out,
488 void *data_in,
489 uint32_t num,
490 cmsis_ecspi_sdma_driver_state_t *ecspi)
491 {
492 int32_t ret;
493 status_t status;
494 ecspi_transfer_t xfer = {0};
495 uint32_t datawidth =
496 (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT;
497
498 xfer.txData = (uint32_t *)data_out;
499 xfer.rxData = (uint32_t *)data_in;
500 xfer.dataSize = num * ((datawidth + 8U) / 8U);
501 xfer.channel = kECSPI_Channel0;
502
503 /* Configure the channel to be used. */
504 switch (ecspi->resource->instance)
505 {
506 case 1:
507 #if defined(RTE_SPI1_TRANSFER_CHANNEL)
508 xfer.channel = RTE_SPI1_TRANSFER_CHANNEL;
509 #endif
510 break;
511 case 2:
512 #if defined(RTE_SPI2_TRANSFER_CHANNEL)
513 xfer.channel = RTE_SPI2_TRANSFER_CHANNEL;
514 #endif
515 break;
516 case 3:
517 #if defined(RTE_SPI3_TRANSFER_CHANNEL)
518 xfer.channel = RTE_SPI3_TRANSFER_CHANNEL;
519 #endif
520 break;
521 default:
522 /* Avoid MISRA 16.4 violations. */
523 break;
524 }
525
526 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
527 {
528 status = ECSPI_MasterTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer);
529 }
530 else
531 {
532 status = ECSPI_SlaveTransferSDMA(ecspi->resource->base, ecspi->handle, &xfer);
533 }
534
535 switch (status)
536 {
537 case kStatus_Success:
538 ret = ARM_DRIVER_OK;
539 break;
540 case kStatus_InvalidArgument:
541 ret = ARM_DRIVER_ERROR_PARAMETER;
542 break;
543 case kStatus_ECSPI_Busy:
544 ret = ARM_DRIVER_ERROR_BUSY;
545 break;
546 default:
547 ret = ARM_DRIVER_ERROR;
548 break;
549 }
550
551 return ret;
552 }
ECSPI_SDMAGetCount(cmsis_ecspi_sdma_driver_state_t * ecspi)553 static uint32_t ECSPI_SDMAGetCount(cmsis_ecspi_sdma_driver_state_t *ecspi)
554 {
555 /* Unsupported by current driver. */
556 return 0U;
557 }
558
ECSPI_SDMAControl(uint32_t control,uint32_t arg,cmsis_ecspi_sdma_driver_state_t * ecspi)559 static int32_t ECSPI_SDMAControl(uint32_t control, uint32_t arg, cmsis_ecspi_sdma_driver_state_t *ecspi)
560 {
561 int32_t result = ARM_DRIVER_OK;
562 bool isDone = false;
563
564 if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_POWER))
565 {
566 return ARM_DRIVER_ERROR;
567 }
568
569 switch (control & ARM_SPI_CONTROL_Msk)
570 {
571 case ARM_SPI_MODE_INACTIVE:
572 ECSPI_Enable(ecspi->resource->base, false);
573 isDone = true;
574 break;
575
576 case ARM_SPI_MODE_MASTER:
577 ecspi->baudRate_Bps = arg;
578 ecspi->flags |= (uint8_t)SPI_FLAG_MASTER;
579 break;
580
581 case ARM_SPI_MODE_SLAVE:
582 ecspi->flags &= ~(uint8_t)SPI_FLAG_MASTER;
583 break;
584
585 case ARM_SPI_SET_BUS_SPEED:
586 if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_MASTER))
587 {
588 result = ARM_DRIVER_ERROR_UNSUPPORTED;
589 break;
590 }
591 ECSPI_SetBaudRate(ecspi->resource->base, arg, ecspi->resource->GetFreq());
592 ecspi->baudRate_Bps = arg;
593 isDone = true;
594 break;
595
596 case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */
597 if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_MASTER))
598 {
599 result = ARM_DRIVER_ERROR_UNSUPPORTED;
600 break;
601 }
602 result = (int32_t)ecspi->baudRate_Bps;
603 isDone = true;
604 break;
605
606 case ARM_SPI_CONTROL_SS:
607 result = ARM_DRIVER_ERROR_UNSUPPORTED;
608 break;
609
610 case ARM_SPI_ABORT_TRANSFER:
611 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
612 {
613 ECSPI_MasterTransferAbortSDMA(ecspi->resource->base, ecspi->handle);
614 }
615 else
616 {
617 ECSPI_SlaveTransferAbortSDMA(ecspi->resource->base, ecspi->handle);
618 }
619 isDone = true;
620 break;
621
622 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
623 /* Unsupported by current driver. */
624 result = ARM_DRIVER_ERROR_UNSUPPORTED;
625 break;
626
627 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
628 /* Mode is not supported by current driver. */
629 result = ARM_DRIVER_ERROR_UNSUPPORTED;
630 break;
631
632 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */
633 /* Mode is not supported by current driver. */
634 result = ARM_DRIVER_ERROR_UNSUPPORTED;
635 break;
636
637 default:
638 /* Avoid MISRA 16.4 violation */
639 break;
640 }
641
642 if ((result != ARM_DRIVER_OK) || isDone)
643 {
644 return result;
645 }
646
647 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
648 {
649 ecspi_master_config_t masterConfig;
650 ECSPI_MasterGetDefaultConfig(&masterConfig);
651 masterConfig.baudRate_Bps = ecspi->baudRate_Bps;
652
653 ECSPI_MasterCommonControl(control, ecspi->resource, &masterConfig);
654
655 if ((ecspi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
656 {
657 ECSPI_Deinit(ecspi->resource->base);
658 }
659 ECSPI_MasterInit(ecspi->resource->base, &masterConfig, ecspi->resource->GetFreq());
660
661 SDMA_CreateHandle(ecspi->sdmaTxDataHandle, ecspi->sdmaResource->txSdmaBase, ecspi->sdmaResource->txSdmaChannel,
662 ecspi->sdmaResource->txSdmaContext);
663 SDMA_CreateHandle(ecspi->sdmaRxDataHandle, ecspi->sdmaResource->rxSdmaBase, ecspi->sdmaResource->rxSdmaChannel,
664 ecspi->sdmaResource->rxSdmaContext);
665 ECSPI_MasterTransferCreateHandleSDMA(ecspi->resource->base, ecspi->handle, KSDK_ECSPI_MasterSDMACallback,
666 (void *)ecspi->cb_event, ecspi->sdmaTxDataHandle, ecspi->sdmaRxDataHandle,
667 ecspi->sdmaResource->txSdmaRequest, ecspi->sdmaResource->rxSdmaRequest,
668 ecspi->sdmaResource->txSdmaChannel, ecspi->sdmaResource->rxSdmaChannel);
669
670 SDMA_SetChannelPriority(ecspi->sdmaResource->txSdmaBase, ecspi->sdmaResource->txSdmaChannel,
671 ecspi->sdmaResource->txSdmaPriority);
672 SDMA_SetChannelPriority(ecspi->sdmaResource->rxSdmaBase, ecspi->sdmaResource->rxSdmaChannel,
673 ecspi->sdmaResource->rxSdmaPriority);
674
675 ecspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
676 }
677 else
678 {
679 ecspi_slave_config_t slaveConfig;
680 ECSPI_SlaveGetDefaultConfig(&slaveConfig);
681 ECSPI_SlaveCommonControl(control, ecspi->resource, &slaveConfig);
682
683 if ((ecspi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
684 {
685 ECSPI_Deinit(ecspi->resource->base);
686 }
687 ECSPI_SlaveInit(ecspi->resource->base, &slaveConfig);
688
689 SDMA_CreateHandle(ecspi->sdmaTxDataHandle, ecspi->sdmaResource->txSdmaBase, ecspi->sdmaResource->txSdmaChannel,
690 ecspi->sdmaResource->txSdmaContext);
691 SDMA_CreateHandle(ecspi->sdmaRxDataHandle, ecspi->sdmaResource->rxSdmaBase, ecspi->sdmaResource->rxSdmaChannel,
692 ecspi->sdmaResource->rxSdmaContext);
693 ECSPI_SlaveTransferCreateHandleSDMA(ecspi->resource->base, ecspi->handle, KSDK_ECSPI_SlaveSDMACallback,
694 (void *)ecspi->cb_event, ecspi->sdmaTxDataHandle, ecspi->sdmaRxDataHandle,
695 ecspi->sdmaResource->txSdmaRequest, ecspi->sdmaResource->rxSdmaRequest,
696 ecspi->sdmaResource->txSdmaChannel, ecspi->sdmaResource->rxSdmaChannel);
697
698 SDMA_SetChannelPriority(ecspi->sdmaResource->txSdmaBase, ecspi->sdmaResource->txSdmaChannel,
699 ecspi->sdmaResource->txSdmaPriority);
700 SDMA_SetChannelPriority(ecspi->sdmaResource->rxSdmaBase, ecspi->sdmaResource->rxSdmaChannel,
701 ecspi->sdmaResource->rxSdmaPriority);
702
703 ecspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
704 }
705
706 return ARM_DRIVER_OK;
707 }
708
ECSPI_SDMAGetStatus(cmsis_ecspi_sdma_driver_state_t * ecspi)709 static ARM_SPI_STATUS ECSPI_SDMAGetStatus(cmsis_ecspi_sdma_driver_state_t *ecspi)
710 {
711 ARM_SPI_STATUS stat = {0};
712
713 stat.busy = ((ecspi->handle->txInProgress == true) || (ecspi->handle->rxInProgress == true)) ? (0U) : (1U);
714 stat.data_lost = 0U;
715 stat.mode_fault = 0U;
716 stat.reserved = 0U;
717
718 return stat;
719 }
720 #endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */
721
722 #endif
723
724 #if ((defined(RTE_SPI1) && RTE_SPI1 && !RTE_SPI1_DMA_EN) || (defined(RTE_SPI2) && RTE_SPI2 && !RTE_SPI2_DMA_EN) || \
725 (defined(RTE_SPI3) && RTE_SPI3 && !RTE_SPI3_DMA_EN))
726
KSDK_ECSPI_MasterInterruptCallback(ECSPI_Type * base,ecspi_master_handle_t * handle,status_t status,void * userData)727 static void KSDK_ECSPI_MasterInterruptCallback(ECSPI_Type *base,
728 ecspi_master_handle_t *handle,
729 status_t status,
730 void *userData)
731 {
732 uint32_t event = 0U;
733
734 if (kStatus_Success == status)
735 {
736 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
737 }
738
739 if (kStatus_ECSPI_HardwareOverFlow == status)
740 {
741 event = ARM_SPI_EVENT_DATA_LOST;
742 }
743
744 /* User data is actually CMSIS driver callback. */
745 if (userData != NULL)
746 {
747 ((ARM_SPI_SignalEvent_t)userData)(event);
748 }
749 }
750
KSDK_ECSPI_SlaveInterruptCallback(ECSPI_Type * base,ecspi_slave_handle_t * handle,status_t status,void * userData)751 static void KSDK_ECSPI_SlaveInterruptCallback(ECSPI_Type *base,
752 ecspi_slave_handle_t *handle,
753 status_t status,
754 void *userData)
755 {
756 uint32_t event = 0;
757
758 if (kStatus_Success == status)
759 {
760 event = ARM_SPI_EVENT_TRANSFER_COMPLETE;
761 }
762
763 if (kStatus_ECSPI_HardwareOverFlow == status)
764 {
765 event = ARM_SPI_EVENT_DATA_LOST;
766 }
767
768 /* User data is actually CMSIS driver callback. */
769 if (userData != NULL)
770 {
771 ((ARM_SPI_SignalEvent_t)userData)(event);
772 }
773 }
774
ECSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event,cmsis_ecspi_interrupt_driver_state_t * ecspi)775 static int32_t ECSPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_ecspi_interrupt_driver_state_t *ecspi)
776 {
777 if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_INIT))
778 {
779 ecspi->cb_event = cb_event;
780 ecspi->flags = (uint8_t)SPI_FLAG_INIT;
781 }
782 return ARM_DRIVER_OK;
783 }
784
ECSPI_InterruptUninitialize(cmsis_ecspi_interrupt_driver_state_t * ecspi)785 static int32_t ECSPI_InterruptUninitialize(cmsis_ecspi_interrupt_driver_state_t *ecspi)
786 {
787 ecspi->flags = (uint8_t)SPI_FLAG_UNINIT;
788 return ARM_DRIVER_OK;
789 }
790
ECSPI_InterruptPowerControl(ARM_POWER_STATE state,cmsis_ecspi_interrupt_driver_state_t * ecspi)791 static int32_t ECSPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_ecspi_interrupt_driver_state_t *ecspi)
792 {
793 int32_t result = ARM_DRIVER_OK;
794 switch (state)
795 {
796 case ARM_POWER_OFF:
797 if ((ecspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
798 {
799 ECSPI_Deinit(ecspi->resource->base);
800 ecspi->flags &= ~(uint8_t)SPI_FLAG_POWER;
801 }
802 break;
803
804 case ARM_POWER_LOW:
805 result = ARM_DRIVER_ERROR_UNSUPPORTED;
806 break;
807
808 case ARM_POWER_FULL:
809 if (ecspi->flags == (uint8_t)SPI_FLAG_UNINIT)
810 {
811 return ARM_DRIVER_ERROR;
812 }
813 /* Driver already powered */
814 if ((ecspi->flags & (uint8_t)SPI_FLAG_POWER) != 0U)
815 {
816 break;
817 }
818 ecspi->flags |= (uint8_t)SPI_FLAG_POWER;
819 break;
820 default:
821 result = ARM_DRIVER_ERROR_UNSUPPORTED;
822 break;
823 }
824 return result;
825 }
826
ECSPI_InterruptSend(const void * data,uint32_t num,cmsis_ecspi_interrupt_driver_state_t * ecspi)827 static int32_t ECSPI_InterruptSend(const void *data, uint32_t num, cmsis_ecspi_interrupt_driver_state_t *ecspi)
828 {
829 int32_t ret;
830 status_t status;
831 ecspi_transfer_t xfer = {0};
832 uint32_t datawidth =
833 (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT;
834
835 xfer.rxData = NULL;
836 xfer.txData = (uint32_t *)data;
837 xfer.dataSize = num * ((datawidth + 8U) / 8U);
838 xfer.channel = kECSPI_Channel0;
839
840 /* Configure the channel to be used. */
841 switch (ecspi->resource->instance)
842 {
843 case 1:
844 #if defined(RTE_SPI1_TRANSFER_CHANNEL)
845 xfer.channel = RTE_SPI1_TRANSFER_CHANNEL;
846 #endif
847 break;
848 case 2:
849 #if defined(RTE_SPI2_TRANSFER_CHANNEL)
850 xfer.channel = RTE_SPI2_TRANSFER_CHANNEL;
851 #endif
852 break;
853 case 3:
854 #if defined(RTE_SPI3_TRANSFER_CHANNEL)
855 xfer.channel = RTE_SPI3_TRANSFER_CHANNEL;
856 #endif
857 break;
858 default:
859 /* Avoid MISRA 16.4 violations. */
860 break;
861 }
862
863 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
864 {
865 status = ECSPI_MasterTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer);
866 }
867 else
868 {
869 status = ECSPI_SlaveTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer);
870 }
871
872 switch (status)
873 {
874 case kStatus_Success:
875 ret = ARM_DRIVER_OK;
876 break;
877 case kStatus_InvalidArgument:
878 ret = ARM_DRIVER_ERROR_PARAMETER;
879 break;
880 case kStatus_ECSPI_Busy:
881 ret = ARM_DRIVER_ERROR_BUSY;
882 break;
883 default:
884 ret = ARM_DRIVER_ERROR;
885 break;
886 }
887
888 return ret;
889 }
890
ECSPI_InterruptReceive(void * data,uint32_t num,cmsis_ecspi_interrupt_driver_state_t * ecspi)891 static int32_t ECSPI_InterruptReceive(void *data, uint32_t num, cmsis_ecspi_interrupt_driver_state_t *ecspi)
892 {
893 int32_t ret;
894 status_t status;
895 ecspi_transfer_t xfer = {0};
896 uint32_t datawidth =
897 (ecspi->resource->base->CONREG & ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT;
898
899 xfer.txData = NULL;
900 xfer.rxData = (uint32_t *)data;
901 xfer.dataSize = num * ((datawidth + 8U) / 8U);
902 xfer.channel = kECSPI_Channel0;
903
904 /* Configure the channel to be used. */
905 switch (ecspi->resource->instance)
906 {
907 case 1:
908 #if defined(RTE_SPI1_TRANSFER_CHANNEL)
909 xfer.channel = RTE_SPI1_TRANSFER_CHANNEL;
910 #endif
911 break;
912 case 2:
913 #if defined(RTE_SPI2_TRANSFER_CHANNEL)
914 xfer.channel = RTE_SPI2_TRANSFER_CHANNEL;
915 #endif
916 break;
917 case 3:
918 #if defined(RTE_SPI3_TRANSFER_CHANNEL)
919 xfer.channel = RTE_SPI3_TRANSFER_CHANNEL;
920 #endif
921 break;
922 default:
923 /* Avoid MISRA 16.4 violations. */
924 break;
925 }
926
927 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
928 {
929 status = ECSPI_MasterTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer);
930 }
931 else
932 {
933 status = ECSPI_SlaveTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer);
934 }
935
936 switch (status)
937 {
938 case kStatus_Success:
939 ret = ARM_DRIVER_OK;
940 break;
941 case kStatus_InvalidArgument:
942 ret = ARM_DRIVER_ERROR_PARAMETER;
943 break;
944 case kStatus_ECSPI_Busy:
945 ret = ARM_DRIVER_ERROR_BUSY;
946 break;
947 default:
948 ret = ARM_DRIVER_ERROR;
949 break;
950 }
951
952 return ret;
953 }
954
ECSPI_InterruptTransfer(const void * data_out,void * data_in,uint32_t num,cmsis_ecspi_interrupt_driver_state_t * ecspi)955 static int32_t ECSPI_InterruptTransfer(const void *data_out,
956 void *data_in,
957 uint32_t num,
958 cmsis_ecspi_interrupt_driver_state_t *ecspi)
959 {
960 int32_t ret;
961 status_t status;
962 ecspi_transfer_t xfer = {0};
963 uint32_t datawidth =
964 (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT;
965
966 xfer.txData = (uint32_t *)data_out;
967 xfer.rxData = (uint32_t *)data_in;
968 xfer.dataSize = num * ((datawidth + 8U) / 8U);
969 xfer.channel = kECSPI_Channel0;
970
971 /* Configure the channel to be used. */
972 switch (ecspi->resource->instance)
973 {
974 case 1:
975 #if defined(RTE_SPI1_TRANSFER_CHANNEL)
976 xfer.channel = RTE_SPI1_TRANSFER_CHANNEL;
977 #endif
978 break;
979 case 2:
980 #if defined(RTE_SPI2_TRANSFER_CHANNEL)
981 xfer.channel = RTE_SPI2_TRANSFER_CHANNEL;
982 #endif
983 break;
984 case 3:
985 #if defined(RTE_SPI3_TRANSFER_CHANNEL)
986 xfer.channel = RTE_SPI3_TRANSFER_CHANNEL;
987 #endif
988 break;
989 default:
990 /* Avoid MISRA 16.4 violations. */
991 break;
992 }
993
994 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
995 {
996 status = ECSPI_MasterTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer);
997 }
998 else
999 {
1000 status = ECSPI_SlaveTransferNonBlocking(ecspi->resource->base, ecspi->handle, &xfer);
1001 }
1002
1003 switch (status)
1004 {
1005 case kStatus_Success:
1006 ret = ARM_DRIVER_OK;
1007 break;
1008 case kStatus_InvalidArgument:
1009 ret = ARM_DRIVER_ERROR_PARAMETER;
1010 break;
1011 case kStatus_ECSPI_Busy:
1012 ret = ARM_DRIVER_ERROR_BUSY;
1013 break;
1014 default:
1015 ret = ARM_DRIVER_ERROR;
1016 break;
1017 }
1018
1019 return ret;
1020 }
ECSPI_InterruptGetCount(cmsis_ecspi_interrupt_driver_state_t * ecspi)1021 static uint32_t ECSPI_InterruptGetCount(cmsis_ecspi_interrupt_driver_state_t *ecspi)
1022 {
1023 uint32_t datawidth =
1024 (ecspi->resource->base->CONREG & (uint32_t)ECSPI_CONREG_BURST_LENGTH_MASK) >> ECSPI_CONREG_BURST_LENGTH_SHIFT;
1025 uint32_t cnt = ecspi->handle->transferSize - ecspi->handle->rxRemainingBytes;
1026 cnt /= ((datawidth + 8U) / 8U);
1027 return cnt;
1028 }
1029
ECSPI_InterruptControl(uint32_t control,uint32_t arg,cmsis_ecspi_interrupt_driver_state_t * ecspi)1030 static int32_t ECSPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_ecspi_interrupt_driver_state_t *ecspi)
1031 {
1032 int32_t result = ARM_DRIVER_OK;
1033 bool isContinue = false;
1034 if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_POWER))
1035 {
1036 return ARM_DRIVER_ERROR;
1037 }
1038
1039 switch (control & ARM_SPI_CONTROL_Msk)
1040 {
1041 case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */
1042 ecspi->baudRate_Bps = arg;
1043 ecspi->flags |= (uint8_t)SPI_FLAG_MASTER;
1044 isContinue = true;
1045 break;
1046
1047 case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on MISO, Input on MOSI) */
1048 ecspi->flags &= ~(uint8_t)SPI_FLAG_MASTER;
1049 isContinue = true;
1050 break;
1051
1052 case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */
1053 if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_MASTER))
1054 {
1055 return ARM_DRIVER_ERROR_UNSUPPORTED;
1056 }
1057 result = (int32_t)ecspi->baudRate_Bps;
1058 break;
1059
1060 case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */
1061 if (0U == (ecspi->flags & (uint8_t)SPI_FLAG_MASTER))
1062 {
1063 return ARM_DRIVER_ERROR_UNSUPPORTED;
1064 }
1065 ECSPI_SetBaudRate(ecspi->resource->base, arg, ecspi->resource->GetFreq());
1066 ecspi->baudRate_Bps = arg;
1067 break;
1068
1069 case ARM_SPI_CONTROL_SS:
1070 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1071 break;
1072
1073 case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */
1074 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1075 {
1076 ECSPI_MasterTransferAbort(ecspi->resource->base, ecspi->handle);
1077 }
1078 else
1079 {
1080 ECSPI_SlaveTransferAbort(ecspi->resource->base, ecspi->handle);
1081 }
1082 break;
1083
1084 case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */
1085 /* Mode is not supported by current driver. */
1086 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1087 break;
1088
1089 case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */
1090 /* Mode is not supported by current driver. */
1091 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1092 break;
1093
1094 case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */
1095 /* Mode is not supported by current driver. */
1096 result = ARM_DRIVER_ERROR_UNSUPPORTED;
1097 break;
1098
1099 default:
1100 isContinue = true;
1101 /* Avoid MISRA 16.4 violation */
1102 break;
1103 }
1104
1105 if (!isContinue)
1106 {
1107 return result;
1108 }
1109
1110 if ((ecspi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U)
1111 {
1112 ecspi_master_config_t masterConfig;
1113 ECSPI_MasterGetDefaultConfig(&masterConfig);
1114 masterConfig.baudRate_Bps = ecspi->baudRate_Bps;
1115
1116 ECSPI_MasterCommonControl(control, ecspi->resource, &masterConfig);
1117
1118 if ((ecspi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
1119 {
1120 ECSPI_Deinit(ecspi->resource->base);
1121 }
1122 ECSPI_MasterInit(ecspi->resource->base, &masterConfig, ecspi->resource->GetFreq());
1123 ECSPI_MasterTransferCreateHandle(ecspi->resource->base, ecspi->handle, KSDK_ECSPI_MasterInterruptCallback,
1124 (void *)ecspi->cb_event);
1125 ecspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1126 }
1127 else
1128 {
1129 ecspi_slave_config_t slaveConfig;
1130 ECSPI_SlaveGetDefaultConfig(&slaveConfig);
1131
1132 ECSPI_SlaveCommonControl(control, ecspi->resource, &slaveConfig);
1133
1134 if ((ecspi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U)
1135 {
1136 ECSPI_Deinit(ecspi->resource->base);
1137 }
1138 ECSPI_SlaveInit(ecspi->resource->base, &slaveConfig);
1139 ECSPI_SlaveTransferCreateHandle(ecspi->resource->base, ecspi->handle, KSDK_ECSPI_SlaveInterruptCallback,
1140 (void *)ecspi->cb_event);
1141 ecspi->flags |= (uint8_t)SPI_FLAG_CONFIGURED;
1142 }
1143
1144 return result;
1145 }
1146
ECSPI_InterruptGetStatus(cmsis_ecspi_interrupt_driver_state_t * ecspi)1147 static ARM_SPI_STATUS ECSPI_InterruptGetStatus(cmsis_ecspi_interrupt_driver_state_t *ecspi)
1148 {
1149 ARM_SPI_STATUS stat = {0};
1150
1151 stat.busy = ((ecspi->handle->txRemainingBytes > 0U) || (ecspi->handle->rxRemainingBytes > 0U)) ? (0U) : (1U);
1152 stat.data_lost = 0U;
1153 stat.mode_fault = 0U;
1154 stat.reserved = 0U;
1155
1156 return stat;
1157 }
1158
1159 #endif
1160
1161 #if defined(ECSPI1) && defined(RTE_SPI1) && RTE_SPI1
1162
1163 /* User needs to provide the implementation for ECSPI1_GetFreq/InitPins/DeinitPins
1164 * in the application for enabling according instance.
1165 */
1166 extern uint32_t ECSPI1_GetFreq(void);
1167
1168 static cmsis_ecspi_resource_t ECSPI1_Resource = {ECSPI1, 1, ECSPI1_GetFreq};
1169
1170 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1171
1172 AT_NONCACHEABLE_SECTION_ALIGN(static ecspi_sdma_handle_t ECSPI1_SdmaHandle, 4);
1173 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t ECSPI1_TxSdmaHandle, 4);
1174 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t ECSPI1_RxSdmaHandle, 4);
1175
1176 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t ECSPI1_TxSdmaContext, 4);
1177 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t ECSPI1_RxSdmaContext, 4);
1178
1179 static cmsis_ecspi_sdma_resource_t ECSPI1_SDMAResource = {
1180 RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, RTE_SPI1_DMA_TX_CH_REQUEST, RTE_SPI1_DMA_TX_CH_PRIORITY,
1181 &ECSPI1_TxSdmaContext, RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH, RTE_SPI1_DMA_RX_CH_REQUEST,
1182 RTE_SPI1_DMA_RX_CH_PRIORITY, &ECSPI1_RxSdmaContext};
1183
1184 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1185 ARMCC_SECTION("ecspi1_sdma_driver_state")
1186 static cmsis_ecspi_sdma_driver_state_t ECSPI1_SDMADriverState = {
1187 #else
1188 static cmsis_ecspi_sdma_driver_state_t ECSPI1_SDMADriverState = {
1189 #endif
1190 &ECSPI1_Resource, &ECSPI1_SDMAResource, &ECSPI1_SdmaHandle, &ECSPI1_RxSdmaHandle, &ECSPI1_TxSdmaHandle};
1191
ECSPI1_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event)1192 static int32_t ECSPI1_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1193 {
1194 #ifdef RTE_SPI1_PIN_INIT
1195 RTE_SPI1_PIN_INIT();
1196 #endif
1197 return ECSPI_SDMAInitialize(cb_event, &ECSPI1_SDMADriverState);
1198 }
1199
ECSPI1_SDMAUninitialize(void)1200 static int32_t ECSPI1_SDMAUninitialize(void)
1201 {
1202 #ifdef RTE_SPI1_PIN_DEINIT
1203 RTE_SPI1_PIN_DEINIT();
1204 #endif
1205 return ECSPI_SDMAUninitialize(&ECSPI1_SDMADriverState);
1206 }
1207
ECSPI1_SDMAPowerControl(ARM_POWER_STATE state)1208 static int32_t ECSPI1_SDMAPowerControl(ARM_POWER_STATE state)
1209 {
1210 return ECSPI_SDMAPowerControl(state, &ECSPI1_SDMADriverState);
1211 }
1212
ECSPI1_SDMASend(const void * data,uint32_t num)1213 static int32_t ECSPI1_SDMASend(const void *data, uint32_t num)
1214 {
1215 return ECSPI_SDMASend(data, num, &ECSPI1_SDMADriverState);
1216 }
1217
ECSPI1_SDMAReceive(void * data,uint32_t num)1218 static int32_t ECSPI1_SDMAReceive(void *data, uint32_t num)
1219 {
1220 return ECSPI_SDMAReceive(data, num, &ECSPI1_SDMADriverState);
1221 }
1222
ECSPI1_SDMATransfer(const void * data_out,void * data_in,uint32_t num)1223 static int32_t ECSPI1_SDMATransfer(const void *data_out, void *data_in, uint32_t num)
1224 {
1225 return ECSPI_SDMATransfer(data_out, data_in, num, &ECSPI1_SDMADriverState);
1226 }
1227
ECSPI1_SDMAGetCount(void)1228 static uint32_t ECSPI1_SDMAGetCount(void)
1229 {
1230 return ECSPI_SDMAGetCount(&ECSPI1_SDMADriverState);
1231 }
1232
ECSPI1_SDMAControl(uint32_t control,uint32_t arg)1233 static int32_t ECSPI1_SDMAControl(uint32_t control, uint32_t arg)
1234 {
1235 return ECSPI_SDMAControl(control, arg, &ECSPI1_SDMADriverState);
1236 }
1237
ECSPI1_SDMAGetStatus(void)1238 static ARM_SPI_STATUS ECSPI1_SDMAGetStatus(void)
1239 {
1240 return ECSPI_SDMAGetStatus(&ECSPI1_SDMADriverState);
1241 }
1242
1243 #else
1244
1245 static ecspi_master_handle_t ECSPI1_Handle;
1246
1247 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1248 ARMCC_SECTION("ecspi1_interrupt_driver_state")
1249 static cmsis_ecspi_interrupt_driver_state_t ECSPI1_InterruptDriverState = {
1250 #else
1251 static cmsis_ecspi_interrupt_driver_state_t ECSPI1_InterruptDriverState = {
1252 #endif
1253 &ECSPI1_Resource,
1254 &ECSPI1_Handle,
1255 };
1256
ECSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1257 static int32_t ECSPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1258 {
1259 #ifdef RTE_SPI1_PIN_INIT
1260 RTE_SPI1_PIN_INIT();
1261 #endif
1262 return ECSPI_InterruptInitialize(cb_event, &ECSPI1_InterruptDriverState);
1263 }
1264
ECSPI1_InterruptUninitialize(void)1265 static int32_t ECSPI1_InterruptUninitialize(void)
1266 {
1267 #ifdef RTE_SPI1_PIN_DEINIT
1268 RTE_SPI1_PIN_DEINIT();
1269 #endif
1270 return ECSPI_InterruptUninitialize(&ECSPI1_InterruptDriverState);
1271 }
1272
ECSPI1_InterruptPowerControl(ARM_POWER_STATE state)1273 static int32_t ECSPI1_InterruptPowerControl(ARM_POWER_STATE state)
1274 {
1275 return ECSPI_InterruptPowerControl(state, &ECSPI1_InterruptDriverState);
1276 }
1277
ECSPI1_InterruptSend(const void * data,uint32_t num)1278 static int32_t ECSPI1_InterruptSend(const void *data, uint32_t num)
1279 {
1280 return ECSPI_InterruptSend(data, num, &ECSPI1_InterruptDriverState);
1281 }
1282
ECSPI1_InterruptReceive(void * data,uint32_t num)1283 static int32_t ECSPI1_InterruptReceive(void *data, uint32_t num)
1284 {
1285 return ECSPI_InterruptReceive(data, num, &ECSPI1_InterruptDriverState);
1286 }
1287
ECSPI1_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1288 static int32_t ECSPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1289 {
1290 return ECSPI_InterruptTransfer(data_out, data_in, num, &ECSPI1_InterruptDriverState);
1291 }
1292
ECSPI1_InterruptGetCount(void)1293 static uint32_t ECSPI1_InterruptGetCount(void)
1294 {
1295 return ECSPI_InterruptGetCount(&ECSPI1_InterruptDriverState);
1296 }
1297
ECSPI1_InterruptControl(uint32_t control,uint32_t arg)1298 static int32_t ECSPI1_InterruptControl(uint32_t control, uint32_t arg)
1299 {
1300 return ECSPI_InterruptControl(control, arg, &ECSPI1_InterruptDriverState);
1301 }
1302
ECSPI1_InterruptGetStatus(void)1303 static ARM_SPI_STATUS ECSPI1_InterruptGetStatus(void)
1304 {
1305 return ECSPI_InterruptGetStatus(&ECSPI1_InterruptDriverState);
1306 }
1307
1308 #endif
1309
1310 ARM_DRIVER_SPI Driver_SPI1 = {
1311 ECSPIx_GetVersion, ECSPIx_GetCapabilities,
1312 #if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN
1313 ECSPI1_SDMAInitialize, ECSPI1_SDMAUninitialize, ECSPI1_SDMAPowerControl, ECSPI1_SDMASend, ECSPI1_SDMAReceive,
1314 ECSPI1_SDMATransfer, ECSPI1_SDMAGetCount, ECSPI1_SDMAControl, ECSPI1_SDMAGetStatus
1315 #else
1316 ECSPI1_InterruptInitialize, ECSPI1_InterruptUninitialize, ECSPI1_InterruptPowerControl, ECSPI1_InterruptSend,
1317 ECSPI1_InterruptReceive, ECSPI1_InterruptTransfer, ECSPI1_InterruptGetCount, ECSPI1_InterruptControl,
1318 ECSPI1_InterruptGetStatus
1319 #endif
1320 };
1321
1322 #endif /* ECSPI1 */
1323
1324 #if defined(ECSPI2) && defined(RTE_SPI2) && RTE_SPI2
1325
1326 /* User needs to provide the implementation for ECSPI2_GetFreq/InitPins/DeinitPins
1327 * in the application for enabling according instance.
1328 */
1329 extern uint32_t ECSPI2_GetFreq(void);
1330
1331 static cmsis_ecspi_resource_t ECSPI2_Resource = {ECSPI2, 2, ECSPI2_GetFreq};
1332
1333 #if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
1334
1335 AT_NONCACHEABLE_SECTION_ALIGN(static ecspi_sdma_handle_t ECSPI2_SdmaHandle, 4);
1336 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t ECSPI2_TxSdmaHandle, 4);
1337 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t ECSPI2_RxSdmaHandle, 4);
1338
1339 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t ECSPI2_TxSdmaContext, 4);
1340 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t ECSPI2_RxSdmaContext, 4);
1341
1342 static cmsis_ecspi_sdma_resource_t ECSPI2_SDMAResource = {
1343 RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, RTE_SPI2_DMA_TX_CH_REQUEST, RTE_SPI2_DMA_TX_CH_PRIORITY,
1344 &ECSPI2_TxSdmaContext, RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH, RTE_SPI2_DMA_RX_CH_REQUEST,
1345 RTE_SPI2_DMA_RX_CH_PRIORITY, &ECSPI2_RxSdmaContext};
1346
1347 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1348 ARMCC_SECTION("ecspi2_sdma_driver_state")
1349 static cmsis_ecspi_sdma_driver_state_t ECSPI2_SDMADriverState = {
1350 #else
1351 static cmsis_ecspi_sdma_driver_state_t ECSPI2_SDMADriverState = {
1352 #endif
1353 &ECSPI2_Resource, &ECSPI2_SDMAResource, &ECSPI2_SdmaHandle, &ECSPI2_TxSdmaHandle, &ECSPI2_RxSdmaHandle,
1354
1355 };
1356
ECSPI2_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event)1357 static int32_t ECSPI2_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1358 {
1359 #ifdef RTE_SPI2_PIN_INIT
1360 RTE_SPI2_PIN_INIT();
1361 #endif
1362 return ECSPI_SDMAInitialize(cb_event, &ECSPI2_SDMADriverState);
1363 }
1364
ECSPI2_SDMAUninitialize(void)1365 static int32_t ECSPI2_SDMAUninitialize(void)
1366 {
1367 #ifdef RTE_SPI2_PIN_DEINIT
1368 RTE_SPI2_PIN_DEINIT();
1369 #endif
1370 return ECSPI_SDMAUninitialize(&ECSPI2_SDMADriverState);
1371 }
1372
ECSPI2_SDMAPowerControl(ARM_POWER_STATE state)1373 static int32_t ECSPI2_SDMAPowerControl(ARM_POWER_STATE state)
1374 {
1375 return ECSPI_SDMAPowerControl(state, &ECSPI2_SDMADriverState);
1376 }
1377
ECSPI2_SDMASend(const void * data,uint32_t num)1378 static int32_t ECSPI2_SDMASend(const void *data, uint32_t num)
1379 {
1380 return ECSPI_SDMASend(data, num, &ECSPI2_SDMADriverState);
1381 }
1382
ECSPI2_SDMAReceive(void * data,uint32_t num)1383 static int32_t ECSPI2_SDMAReceive(void *data, uint32_t num)
1384 {
1385 return ECSPI_SDMAReceive(data, num, &ECSPI2_SDMADriverState);
1386 }
1387
ECSPI2_SDMATransfer(const void * data_out,void * data_in,uint32_t num)1388 static int32_t ECSPI2_SDMATransfer(const void *data_out, void *data_in, uint32_t num)
1389 {
1390 return ECSPI_SDMATransfer(data_out, data_in, num, &ECSPI2_SDMADriverState);
1391 }
1392
ECSPI2_SDMAGetCount(void)1393 static uint32_t ECSPI2_SDMAGetCount(void)
1394 {
1395 return ECSPI_SDMAGetCount(&ECSPI2_SDMADriverState);
1396 }
1397
ECSPI2_SDMAControl(uint32_t control,uint32_t arg)1398 static int32_t ECSPI2_SDMAControl(uint32_t control, uint32_t arg)
1399 {
1400 return ECSPI_SDMAControl(control, arg, &ECSPI2_SDMADriverState);
1401 }
1402
ECSPI2_SDMAGetStatus(void)1403 static ARM_SPI_STATUS ECSPI2_SDMAGetStatus(void)
1404 {
1405 return ECSPI_SDMAGetStatus(&ECSPI2_SDMADriverState);
1406 }
1407
1408 #else
1409
1410 static ecspi_master_handle_t ECSPI2_Handle;
1411
1412 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1413 ARMCC_SECTION("ecspi2_interrupt_driver_state")
1414 static cmsis_ecspi_interrupt_driver_state_t ECSPI2_InterruptDriverState = {
1415 #else
1416 static cmsis_ecspi_interrupt_driver_state_t ECSPI2_InterruptDriverState = {
1417 #endif
1418 &ECSPI2_Resource,
1419 &ECSPI2_Handle,
1420 };
1421
ECSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1422 static int32_t ECSPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1423 {
1424 #ifdef RTE_SPI2_PIN_INIT
1425 RTE_SPI2_PIN_INIT();
1426 #endif
1427 return ECSPI_InterruptInitialize(cb_event, &ECSPI2_InterruptDriverState);
1428 }
1429
ECSPI2_InterruptUninitialize(void)1430 static int32_t ECSPI2_InterruptUninitialize(void)
1431 {
1432 #ifdef RTE_SPI2_PIN_DEINIT
1433 RTE_SPI2_PIN_DEINIT();
1434 #endif
1435 return ECSPI_InterruptUninitialize(&ECSPI2_InterruptDriverState);
1436 }
1437
ECSPI2_InterruptPowerControl(ARM_POWER_STATE state)1438 static int32_t ECSPI2_InterruptPowerControl(ARM_POWER_STATE state)
1439 {
1440 return ECSPI_InterruptPowerControl(state, &ECSPI2_InterruptDriverState);
1441 }
1442
ECSPI2_InterruptSend(const void * data,uint32_t num)1443 static int32_t ECSPI2_InterruptSend(const void *data, uint32_t num)
1444 {
1445 return ECSPI_InterruptSend(data, num, &ECSPI2_InterruptDriverState);
1446 }
1447
ECSPI2_InterruptReceive(void * data,uint32_t num)1448 static int32_t ECSPI2_InterruptReceive(void *data, uint32_t num)
1449 {
1450 return ECSPI_InterruptReceive(data, num, &ECSPI2_InterruptDriverState);
1451 }
1452
ECSPI2_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1453 static int32_t ECSPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1454 {
1455 return ECSPI_InterruptTransfer(data_out, data_in, num, &ECSPI2_InterruptDriverState);
1456 }
1457
ECSPI2_InterruptGetCount(void)1458 static uint32_t ECSPI2_InterruptGetCount(void)
1459 {
1460 return ECSPI_InterruptGetCount(&ECSPI2_InterruptDriverState);
1461 }
1462
ECSPI2_InterruptControl(uint32_t control,uint32_t arg)1463 static int32_t ECSPI2_InterruptControl(uint32_t control, uint32_t arg)
1464 {
1465 return ECSPI_InterruptControl(control, arg, &ECSPI2_InterruptDriverState);
1466 }
1467
ECSPI2_InterruptGetStatus(void)1468 static ARM_SPI_STATUS ECSPI2_InterruptGetStatus(void)
1469 {
1470 return ECSPI_InterruptGetStatus(&ECSPI2_InterruptDriverState);
1471 }
1472
1473 #endif
1474
1475 ARM_DRIVER_SPI Driver_SPI2 = {
1476 ECSPIx_GetVersion, ECSPIx_GetCapabilities,
1477 #if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN
1478 ECSPI2_SDMAInitialize, ECSPI2_SDMAUninitialize, ECSPI2_SDMAPowerControl, ECSPI2_SDMASend, ECSPI2_SDMAReceive,
1479 ECSPI2_SDMATransfer, ECSPI2_SDMAGetCount, ECSPI2_SDMAControl, ECSPI2_SDMAGetStatus
1480 #else
1481 ECSPI2_InterruptInitialize, ECSPI2_InterruptUninitialize, ECSPI2_InterruptPowerControl, ECSPI2_InterruptSend,
1482 ECSPI2_InterruptReceive, ECSPI2_InterruptTransfer, ECSPI2_InterruptGetCount, ECSPI2_InterruptControl,
1483 ECSPI2_InterruptGetStatus
1484 #endif
1485 };
1486
1487 #endif /* ECSPI2 */
1488
1489 #if defined(ECSPI3) && defined(RTE_SPI3) && RTE_SPI3
1490
1491 /* User needs to provide the implementation for ECSPI3_GetFreq/InitPins/DeinitPins
1492 * in the application for enabling according instance.
1493 */
1494 extern uint32_t ECSPI3_GetFreq(void);
1495
1496 static cmsis_ecspi_resource_t ECSPI3_Resource = {ECSPI3, 3, ECSPI3_GetFreq};
1497
1498 #if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN)
1499
1500 AT_NONCACHEABLE_SECTION_ALIGN(static ecspi_sdma_handle_t ECSPI3_SdmaHandle, 4);
1501 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t ECSPI3_TxSdmaHandle, 4);
1502 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_handle_t ECSPI3_RxSdmaHandle, 4);
1503
1504 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t ECSPI3_TxSdmaContext, 4);
1505 AT_NONCACHEABLE_SECTION_ALIGN(static sdma_context_data_t ECSPI3_RxSdmaContext, 4);
1506
1507 static cmsis_ecspi_sdma_resource_t ECSPI3_SDMAResource = {
1508 RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, RTE_SPI3_DMA_TX_CH_REQUEST, RTE_SPI3_DMA_TX_CH_PRIORITY,
1509 &ECSPI3_TxSdmaContext, RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH, RTE_SPI3_DMA_RX_CH_REQUEST,
1510 RTE_SPI3_DMA_RX_CH_PRIORITY, &ECSPI3_RxSdmaContext};
1511
1512 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1513 ARMCC_SECTION("ecspi3_sdma_driver_state")
1514 static cmsis_ecspi_sdma_driver_state_t ECSPI3_SDMADriverState = {
1515 #else
1516 static cmsis_ecspi_sdma_driver_state_t ECSPI3_SDMADriverState = {
1517 #endif
1518 &ECSPI3_Resource, &ECSPI3_SDMAResource, &ECSPI3_SdmaHandle, &ECSPI3_TxSdmaHandle, &ECSPI3_RxSdmaHandle,
1519
1520 };
1521
ECSPI3_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event)1522 static int32_t ECSPI3_SDMAInitialize(ARM_SPI_SignalEvent_t cb_event)
1523 {
1524 #ifdef RTE_SPI3_PIN_INIT
1525 RTE_SPI3_PIN_INIT();
1526 #endif
1527 return ECSPI_SDMAInitialize(cb_event, &ECSPI3_SDMADriverState);
1528 }
1529
ECSPI3_SDMAUninitialize(void)1530 static int32_t ECSPI3_SDMAUninitialize(void)
1531 {
1532 #ifdef RTE_SPI3_PIN_DEINIT
1533 RTE_SPI3_PIN_DEINIT();
1534 #endif
1535 return ECSPI_SDMAUninitialize(&ECSPI3_SDMADriverState);
1536 }
1537
ECSPI3_SDMAPowerControl(ARM_POWER_STATE state)1538 static int32_t ECSPI3_SDMAPowerControl(ARM_POWER_STATE state)
1539 {
1540 return ECSPI_SDMAPowerControl(state, &ECSPI3_SDMADriverState);
1541 }
1542
ECSPI3_SDMASend(const void * data,uint32_t num)1543 static int32_t ECSPI3_SDMASend(const void *data, uint32_t num)
1544 {
1545 return ECSPI_SDMASend(data, num, &ECSPI3_SDMADriverState);
1546 }
1547
ECSPI3_SDMAReceive(void * data,uint32_t num)1548 static int32_t ECSPI3_SDMAReceive(void *data, uint32_t num)
1549 {
1550 return ECSPI_SDMAReceive(data, num, &ECSPI3_SDMADriverState);
1551 }
1552
ECSPI3_SDMATransfer(const void * data_out,void * data_in,uint32_t num)1553 static int32_t ECSPI3_SDMATransfer(const void *data_out, void *data_in, uint32_t num)
1554 {
1555 return ECSPI_SDMATransfer(data_out, data_in, num, &ECSPI3_SDMADriverState);
1556 }
1557
ECSPI3_SDMAGetCount(void)1558 static uint32_t ECSPI3_SDMAGetCount(void)
1559 {
1560 return ECSPI_SDMAGetCount(&ECSPI3_SDMADriverState);
1561 }
1562
ECSPI3_SDMAControl(uint32_t control,uint32_t arg)1563 static int32_t ECSPI3_SDMAControl(uint32_t control, uint32_t arg)
1564 {
1565 return ECSPI_SDMAControl(control, arg, &ECSPI3_SDMADriverState);
1566 }
1567
ECSPI3_SDMAGetStatus(void)1568 static ARM_SPI_STATUS ECSPI3_SDMAGetStatus(void)
1569 {
1570 return ECSPI_SDMAGetStatus(&ECSPI3_SDMADriverState);
1571 }
1572
1573 #else
1574
1575 static ecspi_master_handle_t ECSPI3_Handle;
1576
1577 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
1578 ARMCC_SECTION("ecspi3_interrupt_driver_state")
1579 static cmsis_ecspi_interrupt_driver_state_t ECSPI3_InterruptDriverState = {
1580 #else
1581 static cmsis_ecspi_interrupt_driver_state_t ECSPI3_InterruptDriverState = {
1582 #endif
1583 &ECSPI3_Resource,
1584 &ECSPI3_Handle,
1585 };
1586
ECSPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)1587 static int32_t ECSPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event)
1588 {
1589 #ifdef RTE_SPI3_PIN_INIT
1590 RTE_SPI3_PIN_INIT();
1591 #endif
1592 return ECSPI_InterruptInitialize(cb_event, &ECSPI3_InterruptDriverState);
1593 }
1594
ECSPI3_InterruptUninitialize(void)1595 static int32_t ECSPI3_InterruptUninitialize(void)
1596 {
1597 #ifdef RTE_SPI3_PIN_DEINIT
1598 RTE_SPI3_PIN_DEINIT();
1599 #endif
1600 return ECSPI_InterruptUninitialize(&ECSPI3_InterruptDriverState);
1601 }
1602
ECSPI3_InterruptPowerControl(ARM_POWER_STATE state)1603 static int32_t ECSPI3_InterruptPowerControl(ARM_POWER_STATE state)
1604 {
1605 return ECSPI_InterruptPowerControl(state, &ECSPI3_InterruptDriverState);
1606 }
1607
ECSPI3_InterruptSend(const void * data,uint32_t num)1608 static int32_t ECSPI3_InterruptSend(const void *data, uint32_t num)
1609 {
1610 return ECSPI_InterruptSend(data, num, &ECSPI3_InterruptDriverState);
1611 }
1612
ECSPI3_InterruptReceive(void * data,uint32_t num)1613 static int32_t ECSPI3_InterruptReceive(void *data, uint32_t num)
1614 {
1615 return ECSPI_InterruptReceive(data, num, &ECSPI3_InterruptDriverState);
1616 }
1617
ECSPI3_InterruptTransfer(const void * data_out,void * data_in,uint32_t num)1618 static int32_t ECSPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num)
1619 {
1620 return ECSPI_InterruptTransfer(data_out, data_in, num, &ECSPI3_InterruptDriverState);
1621 }
1622
ECSPI3_InterruptGetCount(void)1623 static uint32_t ECSPI3_InterruptGetCount(void)
1624 {
1625 return ECSPI_InterruptGetCount(&ECSPI3_InterruptDriverState);
1626 }
1627
ECSPI3_InterruptControl(uint32_t control,uint32_t arg)1628 static int32_t ECSPI3_InterruptControl(uint32_t control, uint32_t arg)
1629 {
1630 return ECSPI_InterruptControl(control, arg, &ECSPI3_InterruptDriverState);
1631 }
1632
ECSPI3_InterruptGetStatus(void)1633 static ARM_SPI_STATUS ECSPI3_InterruptGetStatus(void)
1634 {
1635 return ECSPI_InterruptGetStatus(&ECSPI3_InterruptDriverState);
1636 }
1637
1638 #endif
1639
1640 ARM_DRIVER_SPI Driver_SPI3 = {
1641 ECSPIx_GetVersion, ECSPIx_GetCapabilities,
1642 #if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN
1643 ECSPI3_SDMAInitialize, ECSPI3_SDMAUninitialize, ECSPI3_SDMAPowerControl, ECSPI3_SDMASend, ECSPI3_SDMAReceive,
1644 ECSPI3_SDMATransfer, ECSPI3_SDMAGetCount, ECSPI3_SDMAControl, ECSPI3_SDMAGetStatus
1645 #else
1646 ECSPI3_InterruptInitialize, ECSPI3_InterruptUninitialize, ECSPI3_InterruptPowerControl, ECSPI3_InterruptSend,
1647 ECSPI3_InterruptReceive, ECSPI3_InterruptTransfer, ECSPI3_InterruptGetCount, ECSPI3_InterruptControl,
1648 ECSPI3_InterruptGetStatus
1649 #endif
1650 };
1651
1652 #endif /* ECSPI3 */
1653
