1 /**
2 ******************************************************************************
3 * @file system_stm32l4xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32l4xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | MSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 4000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * PLL_M | 1
41 *-----------------------------------------------------------------------------
42 * PLL_N | 8
43 *-----------------------------------------------------------------------------
44 * PLL_P | 7
45 *-----------------------------------------------------------------------------
46 * PLL_Q | 2
47 *-----------------------------------------------------------------------------
48 * PLL_R | 2
49 *-----------------------------------------------------------------------------
50 * PLLSAI1_P | NA
51 *-----------------------------------------------------------------------------
52 * PLLSAI1_Q | NA
53 *-----------------------------------------------------------------------------
54 * PLLSAI1_R | NA
55 *-----------------------------------------------------------------------------
56 * PLLSAI2_P | NA
57 *-----------------------------------------------------------------------------
58 * PLLSAI2_Q | NA
59 *-----------------------------------------------------------------------------
60 * PLLSAI2_R | NA
61 *-----------------------------------------------------------------------------
62 * Require 48MHz for USB OTG FS, | Disabled
63 * SDIO and RNG clock |
64 *-----------------------------------------------------------------------------
65 *=============================================================================
66 ******************************************************************************
67 * @attention
68 *
69 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
70 *
71 * Redistribution and use in source and binary forms, with or without modification,
72 * are permitted provided that the following conditions are met:
73 * 1. Redistributions of source code must retain the above copyright notice,
74 * this list of conditions and the following disclaimer.
75 * 2. Redistributions in binary form must reproduce the above copyright notice,
76 * this list of conditions and the following disclaimer in the documentation
77 * and/or other materials provided with the distribution.
78 * 3. Neither the name of STMicroelectronics nor the names of its contributors
79 * may be used to endorse or promote products derived from this software
80 * without specific prior written permission.
81 *
82 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
83 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
84 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
85 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
86 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
87 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
88 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
89 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
90 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
91 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
92 *
93 ******************************************************************************
94 */
95
96 /** @addtogroup CMSIS
97 * @{
98 */
99
100 /** @addtogroup stm32l4xx_system
101 * @{
102 */
103
104 /** @addtogroup STM32L4xx_System_Private_Includes
105 * @{
106 */
107
108 #include "stm32l4xx.h"
109
110 #if !defined (HSE_VALUE)
111 #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
112 #endif /* HSE_VALUE */
113
114 #if !defined (MSI_VALUE)
115 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
116 #endif /* MSI_VALUE */
117
118 #if !defined (HSI_VALUE)
119 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
120 #endif /* HSI_VALUE */
121
122 /**
123 * @}
124 */
125
126 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
127 * @{
128 */
129
130 /**
131 * @}
132 */
133
134 /** @addtogroup STM32L4xx_System_Private_Defines
135 * @{
136 */
137
138 /************************* Miscellaneous Configuration ************************/
139 /*!< Uncomment the following line if you need to relocate your vector Table in
140 Internal SRAM. */
141 /* #define VECT_TAB_SRAM */
142 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
143 This value must be a multiple of 0x200. */
144 /******************************************************************************/
145 /**
146 * @}
147 */
148
149 /** @addtogroup STM32L4xx_System_Private_Macros
150 * @{
151 */
152
153 /**
154 * @}
155 */
156
157 /** @addtogroup STM32L4xx_System_Private_Variables
158 * @{
159 */
160 /* The SystemCoreClock variable is updated in three ways:
161 1) by calling CMSIS function SystemCoreClockUpdate()
162 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
163 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
164 Note: If you use this function to configure the system clock; then there
165 is no need to call the 2 first functions listed above, since SystemCoreClock
166 variable is updated automatically.
167 */
168 uint32_t SystemCoreClock = 4000000U;
169
170 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
171 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
172 const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
173 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
174 /**
175 * @}
176 */
177
178 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
179 * @{
180 */
181
182 /**
183 * @}
184 */
185
186 /** @addtogroup STM32L4xx_System_Private_Functions
187 * @{
188 */
189
190 /**
191 * @brief Setup the microcontroller system.
192 * @param None
193 * @retval None
194 */
195
SystemInit(void)196 void SystemInit(void)
197 {
198 /* FPU settings ------------------------------------------------------------*/
199 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
200 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
201 #endif
202
203 /* Reset the RCC clock configuration to the default reset state ------------*/
204 /* Set MSION bit */
205 RCC->CR |= RCC_CR_MSION;
206
207 /* Reset CFGR register */
208 RCC->CFGR = 0x00000000U;
209
210 /* Reset HSEON, CSSON , HSION, and PLLON bits */
211 RCC->CR &= 0xEAF6FFFFU;
212
213 /* Reset PLLCFGR register */
214 RCC->PLLCFGR = 0x00001000U;
215
216 /* Reset HSEBYP bit */
217 RCC->CR &= 0xFFFBFFFFU;
218
219 /* Disable all interrupts */
220 RCC->CIER = 0x00000000U;
221
222 /* Configure the Vector Table location add offset address ------------------*/
223 #ifdef VECT_TAB_SRAM
224 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
225 #else
226 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
227 #endif
228 }
229
230 /**
231 * @brief Update SystemCoreClock variable according to Clock Register Values.
232 * The SystemCoreClock variable contains the core clock (HCLK), it can
233 * be used by the user application to setup the SysTick timer or configure
234 * other parameters.
235 *
236 * @note Each time the core clock (HCLK) changes, this function must be called
237 * to update SystemCoreClock variable value. Otherwise, any configuration
238 * based on this variable will be incorrect.
239 *
240 * @note - The system frequency computed by this function is not the real
241 * frequency in the chip. It is calculated based on the predefined
242 * constant and the selected clock source:
243 *
244 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
245 *
246 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
247 *
248 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
249 *
250 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
251 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
252 *
253 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
254 * 4 MHz) but the real value may vary depending on the variations
255 * in voltage and temperature.
256 *
257 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
258 * 16 MHz) but the real value may vary depending on the variations
259 * in voltage and temperature.
260 *
261 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
262 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
263 * frequency of the crystal used. Otherwise, this function may
264 * have wrong result.
265 *
266 * - The result of this function could be not correct when using fractional
267 * value for HSE crystal.
268 *
269 * @param None
270 * @retval None
271 */
SystemCoreClockUpdate(void)272 void SystemCoreClockUpdate(void)
273 {
274 uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
275
276 /* Get MSI Range frequency--------------------------------------------------*/
277 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
278 { /* MSISRANGE from RCC_CSR applies */
279 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
280 }
281 else
282 { /* MSIRANGE from RCC_CR applies */
283 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
284 }
285 /*MSI frequency range in HZ*/
286 msirange = MSIRangeTable[msirange];
287
288 /* Get SYSCLK source -------------------------------------------------------*/
289 switch (RCC->CFGR & RCC_CFGR_SWS)
290 {
291 case 0x00: /* MSI used as system clock source */
292 SystemCoreClock = msirange;
293 break;
294
295 case 0x04: /* HSI used as system clock source */
296 SystemCoreClock = HSI_VALUE;
297 break;
298
299 case 0x08: /* HSE used as system clock source */
300 SystemCoreClock = HSE_VALUE;
301 break;
302
303 case 0x0C: /* PLL used as system clock source */
304 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
305 SYSCLK = PLL_VCO / PLLR
306 */
307 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
308 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
309
310 switch (pllsource)
311 {
312 case 0x02: /* HSI used as PLL clock source */
313 pllvco = (HSI_VALUE / pllm);
314 break;
315
316 case 0x03: /* HSE used as PLL clock source */
317 pllvco = (HSE_VALUE / pllm);
318 break;
319
320 default: /* MSI used as PLL clock source */
321 pllvco = (msirange / pllm);
322 break;
323 }
324 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
325 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
326 SystemCoreClock = pllvco/pllr;
327 break;
328
329 default:
330 SystemCoreClock = msirange;
331 break;
332 }
333 /* Compute HCLK clock frequency --------------------------------------------*/
334 /* Get HCLK prescaler */
335 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
336 /* HCLK clock frequency */
337 SystemCoreClock >>= tmp;
338 }
339
340
341 /**
342 * @}
343 */
344
345 /**
346 * @}
347 */
348
349 /**
350 * @}
351 */
352
353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
354
