1/** 2 ****************************************************************************** 3 * @file startup_stm32l476xx.s 4 * @author MCD Application Team 5 * @brief STM32L476xx devices vector table GCC toolchain. 6 * This module performs: 7 * - Set the initial SP 8 * - Set the initial PC == Reset_Handler, 9 * - Set the vector table entries with the exceptions ISR address, 10 * - Configure the clock system 11 * - Branches to main in the C library (which eventually 12 * calls main()). 13 * After Reset the Cortex-M4 processor is in Thread mode, 14 * priority is Privileged, and the Stack is set to Main. 15 ****************************************************************************** 16 * @attention 17 * 18 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 19 * 20 * Redistribution and use in source and binary forms, with or without modification, 21 * are permitted provided that the following conditions are met: 22 * 1. Redistributions of source code must retain the above copyright notice, 23 * this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright notice, 25 * this list of conditions and the following disclaimer in the documentation 26 * and/or other materials provided with the distribution. 27 * 3. Neither the name of STMicroelectronics nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 ****************************************************************************** 43 */ 44 45 .syntax unified 46 .cpu cortex-m4 47 .fpu softvfp 48 .thumb 49 50.global g_pfnVectors 51.global Default_Handler 52 53/* start address for the initialization values of the .data section. 54defined in linker script */ 55.word _sidata 56/* start address for the .data section. defined in linker script */ 57.word _sdata 58/* end address for the .data section. defined in linker script */ 59.word _edata 60/* start address for the .bss section. defined in linker script */ 61.word _sbss 62/* end address for the .bss section. defined in linker script */ 63.word _ebss 64 65.equ BootRAM, 0xF1E0F85F 66/** 67 * @brief This is the code that gets called when the processor first 68 * starts execution following a reset event. Only the absolutely 69 * necessary set is performed, after which the application 70 * supplied main() routine is called. 71 * @param None 72 * @retval : None 73*/ 74 75 .section .text.Reset_Handler 76 .weak Reset_Handler 77 .type Reset_Handler, %function 78Reset_Handler: 79 ldr sp, =_estack /* Atollic update: set stack pointer */ 80 81/* Copy the data segment initializers from flash to SRAM */ 82 movs r1, #0 83 b LoopCopyDataInit 84 85CopyDataInit: 86 ldr r3, =_sidata 87 ldr r3, [r3, r1] 88 str r3, [r0, r1] 89 adds r1, r1, #4 90 91LoopCopyDataInit: 92 ldr r0, =_sdata 93 ldr r3, =_edata 94 adds r2, r0, r1 95 cmp r2, r3 96 bcc CopyDataInit 97 ldr r2, =_sbss 98 b LoopFillZerobss 99/* Zero fill the bss segment. */ 100FillZerobss: 101 movs r3, #0 102 str r3, [r2], #4 103 104LoopFillZerobss: 105 ldr r3, = _ebss 106 cmp r2, r3 107 bcc FillZerobss 108 109/* Call the clock system intitialization function.*/ 110 bl SystemInit 111/* Call static constructors */ 112 bl __libc_init_array 113/* Call the application's entry point.*/ 114 bl main 115 116LoopForever: 117 b LoopForever 118 119.size Reset_Handler, .-Reset_Handler 120 121/** 122 * @brief This is the code that gets called when the processor receives an 123 * unexpected interrupt. This simply enters an infinite loop, preserving 124 * the system state for examination by a debugger. 125 * 126 * @param None 127 * @retval : None 128*/ 129 .section .text.Default_Handler,"ax",%progbits 130Default_Handler: 131Infinite_Loop: 132 b Infinite_Loop 133 .size Default_Handler, .-Default_Handler 134/****************************************************************************** 135* 136* The minimal vector table for a Cortex-M4. Note that the proper constructs 137* must be placed on this to ensure that it ends up at physical address 138* 0x0000.0000. 139* 140******************************************************************************/ 141 .section .isr_vector,"a",%progbits 142 .type g_pfnVectors, %object 143 .size g_pfnVectors, .-g_pfnVectors 144 145 146g_pfnVectors: 147 .word _estack 148 .word Reset_Handler 149 .word NMI_Handler 150 .word HardFault_Handler 151 .word MemManage_Handler 152 .word BusFault_Handler 153 .word UsageFault_Handler 154 .word 0 155 .word 0 156 .word 0 157 .word 0 158 .word SVC_Handler 159 .word DebugMon_Handler 160 .word 0 161 .word PendSV_Handler 162 .word SysTick_Handler 163 .word WWDG_IRQHandler 164 .word PVD_PVM_IRQHandler 165 .word TAMP_STAMP_IRQHandler 166 .word RTC_WKUP_IRQHandler 167 .word FLASH_IRQHandler 168 .word RCC_IRQHandler 169 .word EXTI0_IRQHandler 170 .word EXTI1_IRQHandler 171 .word EXTI2_IRQHandler 172 .word EXTI3_IRQHandler 173 .word EXTI4_IRQHandler 174 .word DMA1_Channel1_IRQHandler 175 .word DMA1_Channel2_IRQHandler 176 .word DMA1_Channel3_IRQHandler 177 .word DMA1_Channel4_IRQHandler 178 .word DMA1_Channel5_IRQHandler 179 .word DMA1_Channel6_IRQHandler 180 .word DMA1_Channel7_IRQHandler 181 .word ADC1_2_IRQHandler 182 .word CAN1_TX_IRQHandler 183 .word CAN1_RX0_IRQHandler 184 .word CAN1_RX1_IRQHandler 185 .word CAN1_SCE_IRQHandler 186 .word EXTI9_5_IRQHandler 187 .word TIM1_BRK_TIM15_IRQHandler 188 .word TIM1_UP_TIM16_IRQHandler 189 .word TIM1_TRG_COM_TIM17_IRQHandler 190 .word TIM1_CC_IRQHandler 191 .word TIM2_IRQHandler 192 .word TIM3_IRQHandler 193 .word TIM4_IRQHandler 194 .word I2C1_EV_IRQHandler 195 .word I2C1_ER_IRQHandler 196 .word I2C2_EV_IRQHandler 197 .word I2C2_ER_IRQHandler 198 .word SPI1_IRQHandler 199 .word SPI2_IRQHandler 200 .word USART1_IRQHandler 201 .word USART2_IRQHandler 202 .word USART3_IRQHandler 203 .word EXTI15_10_IRQHandler 204 .word RTC_Alarm_IRQHandler 205 .word DFSDM1_FLT3_IRQHandler 206 .word TIM8_BRK_IRQHandler 207 .word TIM8_UP_IRQHandler 208 .word TIM8_TRG_COM_IRQHandler 209 .word TIM8_CC_IRQHandler 210 .word ADC3_IRQHandler 211 .word FMC_IRQHandler 212 .word SDMMC1_IRQHandler 213 .word TIM5_IRQHandler 214 .word SPI3_IRQHandler 215 .word UART4_IRQHandler 216 .word UART5_IRQHandler 217 .word TIM6_DAC_IRQHandler 218 .word TIM7_IRQHandler 219 .word DMA2_Channel1_IRQHandler 220 .word DMA2_Channel2_IRQHandler 221 .word DMA2_Channel3_IRQHandler 222 .word DMA2_Channel4_IRQHandler 223 .word DMA2_Channel5_IRQHandler 224 .word DFSDM1_FLT0_IRQHandler 225 .word DFSDM1_FLT1_IRQHandler 226 .word DFSDM1_FLT2_IRQHandler 227 .word COMP_IRQHandler 228 .word LPTIM1_IRQHandler 229 .word LPTIM2_IRQHandler 230 .word OTG_FS_IRQHandler 231 .word DMA2_Channel6_IRQHandler 232 .word DMA2_Channel7_IRQHandler 233 .word LPUART1_IRQHandler 234 .word QUADSPI_IRQHandler 235 .word I2C3_EV_IRQHandler 236 .word I2C3_ER_IRQHandler 237 .word SAI1_IRQHandler 238 .word SAI2_IRQHandler 239 .word SWPMI1_IRQHandler 240 .word TSC_IRQHandler 241 .word LCD_IRQHandler 242 .word 0 243 .word RNG_IRQHandler 244 .word FPU_IRQHandler 245 246 247/******************************************************************************* 248* 249* Provide weak aliases for each Exception handler to the Default_Handler. 250* As they are weak aliases, any function with the same name will override 251* this definition. 252* 253*******************************************************************************/ 254 255 .weak NMI_Handler 256 .thumb_set NMI_Handler,Default_Handler 257 258 .weak HardFault_Handler 259 .thumb_set HardFault_Handler,Default_Handler 260 261 .weak MemManage_Handler 262 .thumb_set MemManage_Handler,Default_Handler 263 264 .weak BusFault_Handler 265 .thumb_set BusFault_Handler,Default_Handler 266 267 .weak UsageFault_Handler 268 .thumb_set UsageFault_Handler,Default_Handler 269 270 .weak SVC_Handler 271 .thumb_set SVC_Handler,Default_Handler 272 273 .weak DebugMon_Handler 274 .thumb_set DebugMon_Handler,Default_Handler 275 276 .weak PendSV_Handler 277 .thumb_set PendSV_Handler,Default_Handler 278 279 .weak SysTick_Handler 280 .thumb_set SysTick_Handler,Default_Handler 281 282 .weak WWDG_IRQHandler 283 .thumb_set WWDG_IRQHandler,Default_Handler 284 285 .weak PVD_PVM_IRQHandler 286 .thumb_set PVD_PVM_IRQHandler,Default_Handler 287 288 .weak TAMP_STAMP_IRQHandler 289 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler 290 291 .weak RTC_WKUP_IRQHandler 292 .thumb_set RTC_WKUP_IRQHandler,Default_Handler 293 294 .weak FLASH_IRQHandler 295 .thumb_set FLASH_IRQHandler,Default_Handler 296 297 .weak RCC_IRQHandler 298 .thumb_set RCC_IRQHandler,Default_Handler 299 300 .weak EXTI0_IRQHandler 301 .thumb_set EXTI0_IRQHandler,Default_Handler 302 303 .weak EXTI1_IRQHandler 304 .thumb_set EXTI1_IRQHandler,Default_Handler 305 306 .weak EXTI2_IRQHandler 307 .thumb_set EXTI2_IRQHandler,Default_Handler 308 309 .weak EXTI3_IRQHandler 310 .thumb_set EXTI3_IRQHandler,Default_Handler 311 312 .weak EXTI4_IRQHandler 313 .thumb_set EXTI4_IRQHandler,Default_Handler 314 315 .weak DMA1_Channel1_IRQHandler 316 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 317 318 .weak DMA1_Channel2_IRQHandler 319 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 320 321 .weak DMA1_Channel3_IRQHandler 322 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 323 324 .weak DMA1_Channel4_IRQHandler 325 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 326 327 .weak DMA1_Channel5_IRQHandler 328 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 329 330 .weak DMA1_Channel6_IRQHandler 331 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 332 333 .weak DMA1_Channel7_IRQHandler 334 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 335 336 .weak ADC1_2_IRQHandler 337 .thumb_set ADC1_2_IRQHandler,Default_Handler 338 339 .weak CAN1_TX_IRQHandler 340 .thumb_set CAN1_TX_IRQHandler,Default_Handler 341 342 .weak CAN1_RX0_IRQHandler 343 .thumb_set CAN1_RX0_IRQHandler,Default_Handler 344 345 .weak CAN1_RX1_IRQHandler 346 .thumb_set CAN1_RX1_IRQHandler,Default_Handler 347 348 .weak CAN1_SCE_IRQHandler 349 .thumb_set CAN1_SCE_IRQHandler,Default_Handler 350 351 .weak EXTI9_5_IRQHandler 352 .thumb_set EXTI9_5_IRQHandler,Default_Handler 353 354 .weak TIM1_BRK_TIM15_IRQHandler 355 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler 356 357 .weak TIM1_UP_TIM16_IRQHandler 358 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler 359 360 .weak TIM1_TRG_COM_TIM17_IRQHandler 361 .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler 362 363 .weak TIM1_CC_IRQHandler 364 .thumb_set TIM1_CC_IRQHandler,Default_Handler 365 366 .weak TIM2_IRQHandler 367 .thumb_set TIM2_IRQHandler,Default_Handler 368 369 .weak TIM3_IRQHandler 370 .thumb_set TIM3_IRQHandler,Default_Handler 371 372 .weak TIM4_IRQHandler 373 .thumb_set TIM4_IRQHandler,Default_Handler 374 375 .weak I2C1_EV_IRQHandler 376 .thumb_set I2C1_EV_IRQHandler,Default_Handler 377 378 .weak I2C1_ER_IRQHandler 379 .thumb_set I2C1_ER_IRQHandler,Default_Handler 380 381 .weak I2C2_EV_IRQHandler 382 .thumb_set I2C2_EV_IRQHandler,Default_Handler 383 384 .weak I2C2_ER_IRQHandler 385 .thumb_set I2C2_ER_IRQHandler,Default_Handler 386 387 .weak SPI1_IRQHandler 388 .thumb_set SPI1_IRQHandler,Default_Handler 389 390 .weak SPI2_IRQHandler 391 .thumb_set SPI2_IRQHandler,Default_Handler 392 393 .weak USART1_IRQHandler 394 .thumb_set USART1_IRQHandler,Default_Handler 395 396 .weak USART2_IRQHandler 397 .thumb_set USART2_IRQHandler,Default_Handler 398 399 .weak USART3_IRQHandler 400 .thumb_set USART3_IRQHandler,Default_Handler 401 402 .weak EXTI15_10_IRQHandler 403 .thumb_set EXTI15_10_IRQHandler,Default_Handler 404 405 .weak RTC_Alarm_IRQHandler 406 .thumb_set RTC_Alarm_IRQHandler,Default_Handler 407 408 .weak DFSDM1_FLT3_IRQHandler 409 .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler 410 411 .weak TIM8_BRK_IRQHandler 412 .thumb_set TIM8_BRK_IRQHandler,Default_Handler 413 414 .weak TIM8_UP_IRQHandler 415 .thumb_set TIM8_UP_IRQHandler,Default_Handler 416 417 .weak TIM8_TRG_COM_IRQHandler 418 .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler 419 420 .weak TIM8_CC_IRQHandler 421 .thumb_set TIM8_CC_IRQHandler,Default_Handler 422 423 .weak ADC3_IRQHandler 424 .thumb_set ADC3_IRQHandler,Default_Handler 425 426 .weak FMC_IRQHandler 427 .thumb_set FMC_IRQHandler,Default_Handler 428 429 .weak SDMMC1_IRQHandler 430 .thumb_set SDMMC1_IRQHandler,Default_Handler 431 432 .weak TIM5_IRQHandler 433 .thumb_set TIM5_IRQHandler,Default_Handler 434 435 .weak SPI3_IRQHandler 436 .thumb_set SPI3_IRQHandler,Default_Handler 437 438 .weak UART4_IRQHandler 439 .thumb_set UART4_IRQHandler,Default_Handler 440 441 .weak UART5_IRQHandler 442 .thumb_set UART5_IRQHandler,Default_Handler 443 444 .weak TIM6_DAC_IRQHandler 445 .thumb_set TIM6_DAC_IRQHandler,Default_Handler 446 447 .weak TIM7_IRQHandler 448 .thumb_set TIM7_IRQHandler,Default_Handler 449 450 .weak DMA2_Channel1_IRQHandler 451 .thumb_set DMA2_Channel1_IRQHandler,Default_Handler 452 453 .weak DMA2_Channel2_IRQHandler 454 .thumb_set DMA2_Channel2_IRQHandler,Default_Handler 455 456 .weak DMA2_Channel3_IRQHandler 457 .thumb_set DMA2_Channel3_IRQHandler,Default_Handler 458 459 .weak DMA2_Channel4_IRQHandler 460 .thumb_set DMA2_Channel4_IRQHandler,Default_Handler 461 462 .weak DMA2_Channel5_IRQHandler 463 .thumb_set DMA2_Channel5_IRQHandler,Default_Handler 464 465 .weak DFSDM1_FLT0_IRQHandler 466 .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler 467 468 .weak DFSDM1_FLT1_IRQHandler 469 .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler 470 471 .weak DFSDM1_FLT2_IRQHandler 472 .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler 473 474 .weak COMP_IRQHandler 475 .thumb_set COMP_IRQHandler,Default_Handler 476 477 .weak LPTIM1_IRQHandler 478 .thumb_set LPTIM1_IRQHandler,Default_Handler 479 480 .weak LPTIM2_IRQHandler 481 .thumb_set LPTIM2_IRQHandler,Default_Handler 482 483 .weak OTG_FS_IRQHandler 484 .thumb_set OTG_FS_IRQHandler,Default_Handler 485 486 .weak DMA2_Channel6_IRQHandler 487 .thumb_set DMA2_Channel6_IRQHandler,Default_Handler 488 489 .weak DMA2_Channel7_IRQHandler 490 .thumb_set DMA2_Channel7_IRQHandler,Default_Handler 491 492 .weak LPUART1_IRQHandler 493 .thumb_set LPUART1_IRQHandler,Default_Handler 494 495 .weak QUADSPI_IRQHandler 496 .thumb_set QUADSPI_IRQHandler,Default_Handler 497 498 .weak I2C3_EV_IRQHandler 499 .thumb_set I2C3_EV_IRQHandler,Default_Handler 500 501 .weak I2C3_ER_IRQHandler 502 .thumb_set I2C3_ER_IRQHandler,Default_Handler 503 504 .weak SAI1_IRQHandler 505 .thumb_set SAI1_IRQHandler,Default_Handler 506 507 .weak SAI2_IRQHandler 508 .thumb_set SAI2_IRQHandler,Default_Handler 509 510 .weak SWPMI1_IRQHandler 511 .thumb_set SWPMI1_IRQHandler,Default_Handler 512 513 .weak TSC_IRQHandler 514 .thumb_set TSC_IRQHandler,Default_Handler 515 516 .weak LCD_IRQHandler 517 .thumb_set LCD_IRQHandler,Default_Handler 518 519 .weak RNG_IRQHandler 520 .thumb_set RNG_IRQHandler,Default_Handler 521 522 .weak FPU_IRQHandler 523 .thumb_set FPU_IRQHandler,Default_Handler 524/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 525
