1 /* 2 * Copyright 2023 NXP 3 * All rights reserved. 4 * 5 * SPDXLicense-Identifier: BSD-3-Clause 6 */ 7 #include "flash_config.h" 8 9 /* Component ID definition, used by tools. */ 10 #ifndef FSL_COMPONENT_ID 11 #define FSL_COMPONENT_ID "platform.drivers.flash_config" 12 #endif 13 14 /******************************************************************************* 15 * Code 16 ******************************************************************************/ 17 #if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) 18 #if defined(__ARMCC_VERSION) || defined(__GNUC__) 19 __attribute__((section(".flash_conf"), used)) 20 #elif defined(__ICCARM__) 21 #pragma location = ".flash_conf" 22 #endif 23 24 const fc_static_platform_config_t flash_config = { 25 .xspi_fcb_block = { 26 .memConfig = 27 { 28 .tag = FC_XSPI_CFG_BLK_TAG, 29 .version = FC_XSPI_CFG_BLK_VERSION, 30 .readSampleClkSrc = kXSPIReadSampleClk_ExternalInputFromDqsPad, 31 .csHoldTime = 3, 32 .csSetupTime = 3, 33 .deviceModeCfgEnable = 1, 34 .deviceModeType = 2, 35 .waitTimeCfgCommands = 1, 36 .deviceModeSeq = 37 { 38 .seqNum = 1, 39 .seqId = 6, /* See Lookup table for more details */ 40 .reserved = 0, 41 }, 42 .deviceModeArg = 2, /* Enable OPI DDR mode */ 43 .controllerMiscOption = 44 (1u << Fc_XspiMiscOffset_SafeConfigFreqEnable) | (1u << Fc_XspiMiscOffset_DdrModeEnable), 45 .deviceType = 1, 46 .sflashPadType = 8, 47 .serialClkFreq = Fc_XspiSerialClk_200MHz, 48 .sflashA1Size = 64ul * 1024u * 1024u, 49 .busyOffset = 0u, 50 .busyBitPolarity = 0u, 51 .lookupTable = 52 { 53 /*Read*/ 54 [0] = 55 FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0xEE, FC_CMD_DDR, FC_XSPI_8PAD, 0x11), 56 [1] = 57 FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x12), 58 [2] = 59 FC_XSPI_LUT_SEQ(FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x2, FC_CMD_READ_DDR, FC_XSPI_8PAD, 0x4), 60 [3] = 61 FC_XSPI_LUT_SEQ(FC_CMD_STOP, FC_XSPI_8PAD, 0x0, 0, 0, 0), 62 63 /*Read status SPI*/ 64 [5 * 1 + 0] = 65 FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x05, FC_CMD_READ_SDR, FC_XSPI_1PAD, 0x04), 66 67 /* Read Status OPI */ 68 [5 * 2 + 0] = 69 FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x05, FC_CMD_DDR, FC_XSPI_8PAD, 0xFA), 70 [5 * 2 + 1] = 71 FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x12), 72 [5 * 2 + 2] = 73 FC_XSPI_LUT_SEQ(FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x2, FC_CMD_READ_DDR, FC_XSPI_8PAD, 0x4), 74 [5 * 2 + 3] = 75 FC_XSPI_LUT_SEQ(FC_CMD_STOP, FC_XSPI_8PAD, 0x0, 0, 0, 0), 76 77 /*Write enable*/ 78 [5 * 3 + 0] = 79 FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x06, FC_CMD_STOP, FC_XSPI_1PAD, 0x04), 80 81 /* Write Enable - OPI */ 82 [5 * 4 + 0] = 83 FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x06, FC_CMD_DDR, FC_XSPI_8PAD, 0xF9), 84 85 /* Erase Sector */ 86 [5 * 5 + 0] = 87 FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x21, FC_CMD_DDR, FC_XSPI_8PAD, 0xDE), 88 [5 * 5 + 1] = 89 FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_STOP, FC_XSPI_8PAD, 0x0), 90 91 /* Enable OPI DDR mode */ 92 [5 * 6 + 0] = 93 FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x72, FC_CMD_SDR, FC_XSPI_1PAD, 0x00), 94 [5 * 6 + 1] = 95 FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x00, FC_CMD_SDR, FC_XSPI_1PAD, 0x00), 96 [5 * 6 + 2] = 97 FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x00, FC_CMD_WRITE_SDR, FC_XSPI_1PAD, 0x01), 98 99 /* Page program */ 100 [5 * 9 + 0] = 101 FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x12, FC_CMD_DDR, FC_XSPI_8PAD, 0xED), 102 [5 * 9 + 1] = 103 FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_WRITE_DDR, FC_XSPI_8PAD, 0x4), 104 105 /* Erase Chip */ 106 [5 * 11 + 0] = 107 FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x60, FC_CMD_DDR, FC_XSPI_8PAD, 0x9F), 108 }, 109 }, 110 .pageSize = 256u, 111 .sectorSize = 4u * 1024u, 112 .ipcmdSerialClkFreq = 1u, 113 .serialNorType = 2u, 114 .blockSize = 64u * 1024u, 115 .flashStateCtx = 0x07008200u, 116 }, 117 #ifdef BOOT_ENABLE_XSPI1_PSRAM 118 .psram_config_block = { 119 .xmcdHeader = 0xC0010008, 120 .xmcdOpt0 = 0xC0000700, 121 }, 122 #endif 123 }; 124 125 #endif /* BOOT_HEADER_ENABLE */ 126
