1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_msp.c
4 * @author MCD Application Team
5 * @brief HAL MSP module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "boot_hal_cfg.h"
22
23 /** @addtogroup STM32H5xx_HAL_Examples
24 * @{
25 */
26
27 /** @defgroup RTC_ActiveTamper
28 * @{
29 */
30
31 /* Private typedef -----------------------------------------------------------*/
32 /* Private define ------------------------------------------------------------*/
33 /* Private macro -------------------------------------------------------------*/
34 /* Private variables ---------------------------------------------------------*/
35 /* Private constant ----------------------------------------------------------*/
36 /** @defgroup HAL_MSP_Private_Constant
37 * @{
38 */
39 const RCC_OscInitTypeDef RCC_OscInitStruct_RTC =
40 {
41 .OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE,
42 .HSEState = 0,
43 #if defined(RTC_CLOCK_SOURCE_LSE)
44 .LSEState = RCC_LSE_ON,
45 .LSIState = RCC_LSI_OFF,
46 #elif defined (RTC_CLOCK_SOURCE_LSI)
47 .LSEState = RCC_LSE_OFF,
48 .LSIState = RCC_LSI_ON,
49 #else
50 #error
51 #endif /* defined (RTC_CLOCK_SOURCE_LSI) */
52 .HSIState = 0,
53 .HSIDiv = 0,
54 .HSICalibrationValue = 0,
55 .CSIState = 0,
56 .CSICalibrationValue = 0,
57 .HSI48State = 0,
58 .PLL = {
59 .PLLState = RCC_PLL_NONE,
60 .PLLSource = 0,
61 .PLLM = 0,
62 .PLLN = 0,
63 .PLLP = 0,
64 .PLLQ = 0,
65 .PLLR = 0,
66 .PLLRGE = 0,
67 .PLLVCOSEL = 0,
68 .PLLFRACN = 0
69 }
70 };
71
72 const RCC_PeriphCLKInitTypeDef PeriphClkInitStruct_RTC =
73 {
74 .PeriphClockSelection = RCC_PERIPHCLK_RTC,
75 .PLL2 = {0},
76 #if defined(RCC_CR_PLL3ON)
77 .PLL3 = {0},
78 #endif /* RCC_CR_PLL3ON */
79 .CkperClockSelection = 0,
80 .Usart1ClockSelection = 0,
81 .Usart2ClockSelection = 0,
82 .Usart3ClockSelection = 0,
83 #if defined(UART4)
84 .Uart4ClockSelection = 0,
85 #endif /* UART4 */
86 #if defined(UART5)
87 .Uart5ClockSelection = 0,
88 #endif /* UART5 */
89 #if defined(USART6)
90 .Usart6ClockSelection = 0,
91 #endif /* UART6 */
92 #if defined(UART7)
93 .Uart7ClockSelection = 0,
94 #endif /* UART7 */
95 #if defined(UART8)
96 .Uart8ClockSelection = 0,
97 #endif /* UART8 */
98 #if defined(UART9)
99 .Uart9ClockSelection = 0,
100 #endif /* UART9 */
101 #if defined(USART10)
102 .Usart10ClockSelection = 0,
103 #endif /* UART10 */
104 #if defined(USART11)
105 .Usart11ClockSelection = 0,
106 #endif /* UART11 */
107 #if defined(USART12)
108 .Uart12ClockSelection = 0,
109 #endif /* UART12 */
110 .Lpuart1ClockSelection = 0,
111 .I2c1ClockSelection = 0,
112 .I2c2ClockSelection = 0,
113 #if defined(I2C3)
114 .I2c3ClockSelection = 0,
115 #endif /* I2C3 */
116 #if defined(I2C4)
117 .I2c4ClockSelection = 0,
118 #endif /* I2C4 */
119 .I3c1ClockSelection = 0,
120 #if defined(I3C2)
121 .I3c2ClockSelection = 0,
122 #endif /* I3C2 */
123 .Lptim1ClockSelection = 0,
124 .Lptim2ClockSelection = 0,
125 #if defined(LPTIM3)
126 .Lptim3ClockSelection = 0,
127 #endif /* LPTIM3 */
128 #if defined(LPTIM4)
129 .Lptim4ClockSelection = 0,
130 #endif /* LPTIM4 */
131 #if defined(LPTIM5)
132 .Lptim5ClockSelection = 0,
133 #endif /* LPTIM5 */
134 #if defined(LPTIM6)
135 .Lptim6ClockSelection = 0,
136 #endif /* LPTIM6 */
137 #if defined(FDCAN2)
138 .Fdcan12ClockSelection = 0,
139 #else
140 .Fdcan1ClockSelection = 0,
141 #endif /* FDCAN2 */
142 #if defined(SAI1)
143 .Sai1ClockSelection = 0,
144 #endif /* SAI1 */
145 #if defined(SAI2)
146 .Sai2ClockSelection = 0,
147 #endif /* SAI2 */
148 .RngClockSelection = 0,
149 #if defined(SDMMC1)
150 .Sdmmc1ClockSelection = 0,
151 #endif /* SDMMC1 */
152 #if defined(SDMMC2)
153 .Sdmmc2ClockSelection = 0,
154 #endif /* SDMMC2 */
155 .AdcDacClockSelection = 0,
156 .DacLowPowerClockSelection = 0,
157 #if defined(OCTOSPI1)
158 .OspiClockSelection = 0,
159 #endif
160 .Spi1ClockSelection = 0,
161 .Spi2ClockSelection = 0,
162 .Spi3ClockSelection = 0,
163 #if defined(SPI4)
164 .Spi4ClockSelection = 0,
165 #endif /* SPI4 */
166 #if defined(SPI5)
167 .Spi5ClockSelection = 0,
168 #endif /* SPI5 */
169 #if defined(SPI6)
170 .Spi6ClockSelection = 0,
171 #endif /* SPI6 */
172 #if defined(RTC_CLOCK_SOURCE_LSE)
173 .RTCClockSelection = RCC_RTCCLKSOURCE_LSE,
174 #elif defined (RTC_CLOCK_SOURCE_LSI)
175 .RTCClockSelection = RCC_RTCCLKSOURCE_LSI,
176 #else
177 #error
178 #endif /* RTC_CLOCK_SOURCE_LSE */
179 #if defined(CEC)
180 .CecClockSelection = 0,
181 #endif /* CEC */
182 .UsbClockSelection = 0,
183 .TimPresSelection = 0
184 };
185 /**
186 * @}
187 */
188
189 /* Private function prototypes -----------------------------------------------*/
190 HAL_StatusTypeDef RCC_OscConfig(const RCC_OscInitTypeDef *pOscInitStruct);
191 HAL_StatusTypeDef RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit);
192 /* Private functions ---------------------------------------------------------*/
193
194 /** @defgroup HAL_MSP_Private_Functions
195 * @{
196 */
197
198 /**
199 * @brief Initialize the RCC Oscillators according to the specified parameters in the
200 * RCC_OscInitTypeDef.
201 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
202 * contains the configuration information for the RCC Oscillators.
203 * @retval HAL status
204 */
RCC_OscConfig(const RCC_OscInitTypeDef * pOscInitStruct)205 HAL_StatusTypeDef RCC_OscConfig(const RCC_OscInitTypeDef *pOscInitStruct)
206 {
207 uint32_t tickstart = 0;
208
209 /* Check Null pointer */
210 if (pOscInitStruct == NULL)
211 {
212 return HAL_ERROR;
213 }
214
215 /* Check the parameters */
216 assert_param(IS_RCC_OSCILLATORTYPE(pOscInitStruct->OscillatorType));
217
218 #if defined (RTC_CLOCK_SOURCE_LSI)
219 /*------------------------------ LSI Configuration -------------------------*/
220 if (((pOscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
221 {
222
223 /* Check the parameters */
224 assert_param(IS_RCC_LSI(pOscInitStruct->LSIState));
225
226 /* Update LSI configuration in Backup Domain control register */
227
228 /* Check the LSI State */
229 if (pOscInitStruct->LSIState != RCC_LSI_OFF)
230 {
231 /* Enable the Internal Low Speed oscillator (LSI). */
232 __HAL_RCC_LSI_ENABLE();
233
234 /* Get Start Tick*/
235 tickstart = HAL_GetTick();
236
237 /* Wait till LSI is ready */
238 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == 0U)
239 {
240 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
241 {
242 return HAL_TIMEOUT;
243 }
244 }
245 }
246 else
247 {
248 /* Disable the Internal Low Speed oscillator (LSI). */
249 __HAL_RCC_LSI_DISABLE();
250
251 /* Get Start Tick*/
252 tickstart = HAL_GetTick();
253
254 /* Wait till LSI is disabled */
255 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U)
256 {
257 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
258 {
259 return HAL_TIMEOUT;
260 }
261 }
262 }
263 }
264 #endif /* RTC_CLOCK_SOURCE_LSI */
265
266 #if defined(RTC_CLOCK_SOURCE_LSE)
267 /*------------------------------ LSE Configuration -------------------------*/
268 if (((pOscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
269 {
270 /* Check the parameters */
271 assert_param(IS_RCC_LSE(pOscInitStruct->LSEState));
272
273 /* Update LSE configuration in Backup Domain control register */
274 /* Requires to enable write access to Backup Domain */
275 if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
276 {
277 /* Enable write access to Backup domain */
278 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
279
280 /* Wait for Backup domain Write protection disable */
281 tickstart = HAL_GetTick();
282
283 while (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
284 {
285 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
286 {
287 return HAL_TIMEOUT;
288 }
289 }
290 }
291
292 /* Set the new LSE configuration -----------------------------------------*/
293 __HAL_RCC_LSE_CONFIG(pOscInitStruct->LSEState);
294
295 /* Check the LSE State */
296 if (pOscInitStruct->LSEState != RCC_LSE_OFF)
297 {
298 /* Get Start Tick*/
299 tickstart = HAL_GetTick();
300
301 /* Wait till LSE is ready */
302 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
303 {
304 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
305 {
306 return HAL_TIMEOUT;
307 }
308 }
309 }
310 else
311 {
312 /* Get Start Tick*/
313 tickstart = HAL_GetTick();
314
315 /* Wait till LSE is disabled */
316 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
317 {
318 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
319 {
320 return HAL_TIMEOUT;
321 }
322 }
323 }
324 }
325 #endif /* RTC_CLOCK_SOURCE_LSE */
326
327 return HAL_OK;
328 }
329
330 /**
331 * @brief Initialize the RCC extended peripherals clocks according to the specified
332 * parameters in the RCC_PeriphCLKInitTypeDef.
333 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
334 * contains a field PeriphClockSelection which can be one of the following values:
335 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
336 *
337 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
338 * the RTC clock source: in this case the access to Backup domain is enabled.
339 *
340 * @retval HAL status
341 */
RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * pPeriphClkInit)342 HAL_StatusTypeDef RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
343 {
344 uint32_t tmpregister;
345 uint32_t tickstart;
346 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
347 HAL_StatusTypeDef status = HAL_OK; /* Final status */
348
349 /* Check the parameters */
350 assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
351
352 /*-------------------------- RTC clock source configuration ----------------------*/
353 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
354 {
355
356 /* Check for RTC Parameters used to output RTCCLK */
357 assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
358
359 /* Enable write access to Backup domain */
360 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
361
362 /* Wait for Backup domain Write protection disable */
363 tickstart = HAL_GetTick();
364
365 while (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
366 {
367 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
368 {
369 ret = HAL_TIMEOUT;
370 break;
371 }
372 }
373
374 if (ret == HAL_OK)
375 {
376 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
377 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
378
379 if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
380 {
381 /* Store the content of BDCR register before the reset of Backup Domain */
382 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
383 /* RTC Clock selection can be changed only if the Backup Domain is reset */
384 __HAL_RCC_BACKUPRESET_FORCE();
385 __HAL_RCC_BACKUPRESET_RELEASE();
386 /* Restore the Content of BDCR register */
387 RCC->BDCR = tmpregister;
388 }
389
390 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
391 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
392 {
393 /* Get Start Tick*/
394 tickstart = HAL_GetTick();
395
396 /* Wait till LSE is ready */
397 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
398 {
399 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
400 {
401 ret = HAL_TIMEOUT;
402 break;
403 }
404 }
405 }
406
407 if (ret == HAL_OK)
408 {
409 /* Apply new RTC clock source selection */
410 __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
411 }
412 else
413 {
414 /* set overall return value */
415 status = ret;
416 }
417 }
418 else
419 {
420 /* set overall return value */
421 status = ret;
422 }
423
424 }
425 return status;
426 }
427
428 /**
429 * @brief RTC MSP Initialization
430 * This function configures the hardware resources used in this example:
431 * - Peripheral's clock enable
432 * @param hrtc: RTC handle pointer
433 * @retval None
434 */
HAL_RTC_MspInit(RTC_HandleTypeDef * hrtc)435 void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
436 {
437 HAL_PWR_EnableBkUpAccess();
438 /* not required to be removed */
439 __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
440 /* Reset the whole backup domain, RTC included */
441 if (RCC_OscConfig((RCC_OscInitTypeDef *)&RCC_OscInitStruct_RTC) != HAL_OK)
442 {
443 Error_Handler();
444 }
445 if (RCCEx_PeriphCLKConfig((RCC_PeriphCLKInitTypeDef *)&PeriphClkInitStruct_RTC) != HAL_OK)
446 {
447 Error_Handler();
448 }
449 /* Enable RTC */
450 __HAL_RCC_RTC_ENABLE();
451
452 /* Enable RTC clock */
453 __HAL_RCC_RTC_CLK_ENABLE();
454
455 HAL_NVIC_SetPriority(TAMP_IRQn, 0x4, 0);
456 HAL_NVIC_EnableIRQ(TAMP_IRQn);
457 }
458
459 /**
460 * @brief RTC MSP De-Initialization
461 * This function freeze the hardware resources used in this example:
462 * - Disable the Peripheral's clock
463 * @param hrtc: RTC handle pointer
464 * @retval None
465 */
HAL_RTC_MspDeInit(RTC_HandleTypeDef * hrtc)466 void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
467 {
468 /*##-1- Reset peripherals ##################################################*/
469 __HAL_RCC_RTC_DISABLE();
470 }
471
472 /**
473 * @}
474 */
475
476 /**
477 * @}
478 */
479
480 /**
481 * @}
482 */
483
