1 /*
2 * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <common/debug.h>
10 #include <common/runtime_svc.h>
11 #include <drivers/generic_delay_timer.h>
12 #include <lib/mmio.h>
13 #include <lib/xlat_tables/xlat_tables_v2.h>
14 #include <plat/common/platform.h>
15 #include <plat_common.h>
16 #include <plat_ipi.h>
17
18 #include <plat_private.h>
19 #include <versal_net_def.h>
20
21 uint32_t platform_id, platform_version;
22
23 /*
24 * Table of regions to map using the MMU.
25 * This doesn't include TZRAM as the 'mem_layout' argument passed to
26 * configure_mmu_elx() will give the available subset of that,
27 */
28 const mmap_region_t plat_versal_net_mmap[] = {
29 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
31 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
32 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
33 MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
34 { 0 }
35 };
36
plat_get_mmap(void)37 const mmap_region_t *plat_get_mmap(void)
38 {
39 return plat_versal_net_mmap;
40 }
41
42 /* For saving cpu clock for certain platform */
43 uint32_t cpu_clock;
44
board_name_decode(void)45 char *board_name_decode(void)
46 {
47 switch (platform_id) {
48 case VERSAL_NET_SPP:
49 return "IPP";
50 case VERSAL_NET_EMU:
51 return "EMU";
52 case VERSAL_NET_SILICON:
53 return "Silicon";
54 case VERSAL_NET_QEMU:
55 return "QEMU";
56 default:
57 return "Unknown";
58 }
59 }
60
board_detection(void)61 void board_detection(void)
62 {
63 uint32_t version;
64
65 version = mmio_read_32(PMC_TAP_VERSION);
66 platform_id = FIELD_GET(PLATFORM_MASK, version);
67 platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
68
69 if (platform_id == VERSAL_NET_QEMU_COSIM) {
70 platform_id = VERSAL_NET_QEMU;
71 }
72
73 if ((platform_id == VERSAL_NET_SPP) ||
74 (platform_id == VERSAL_NET_EMU) ||
75 (platform_id == VERSAL_NET_QEMU)) {
76 /*
77 * 9 is diff for
78 * 0 means 0.9 version
79 * 1 means 1.0 version
80 * 2 means 1.1 version
81 * etc,
82 */
83 platform_version += 9U;
84 }
85
86 /* Make sure that console is setup to see this message */
87 VERBOSE("Platform id: %d version: %d.%d\n", platform_id,
88 platform_version / 10U, platform_version % 10U);
89 }
90
get_uart_clk(void)91 uint32_t get_uart_clk(void)
92 {
93 uint32_t uart_clock;
94
95 switch (platform_id) {
96 case VERSAL_NET_SPP:
97 uart_clock = 1000000;
98 break;
99 case VERSAL_NET_EMU:
100 uart_clock = 25000000;
101 break;
102 case VERSAL_NET_QEMU:
103 uart_clock = 25000000;
104 break;
105 case VERSAL_NET_SILICON:
106 uart_clock = 100000000;
107 break;
108 default:
109 panic();
110 }
111
112 return uart_clock;
113 }
114
versal_net_config_setup(void)115 void versal_net_config_setup(void)
116 {
117 uint32_t val;
118 uintptr_t crl_base, iou_scntrs_base, psx_base;
119
120 crl_base = VERSAL_NET_CRL;
121 iou_scntrs_base = VERSAL_NET_IOU_SCNTRS;
122 psx_base = PSX_CRF;
123
124 /* Reset for system timestamp generator in FPX */
125 mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0);
126
127 /* Global timer init - Program time stamp reference clk */
128 val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET);
129 val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
130 mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val);
131
132 /* Clear reset of timestamp reg */
133 mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0);
134
135 /* Program freq register in System counter and enable system counter. */
136 mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET,
137 cpu_clock);
138 mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
139 VERSAL_NET_IOU_SCNTRS_CONTROL_EN);
140
141 generic_delay_timer_init();
142
143 #if (TFA_NO_PM == 0)
144 /* Configure IPI data for versal_net */
145 versal_net_ipi_config_table_init();
146 #endif
147 }
148
plat_get_syscnt_freq2(void)149 uint32_t plat_get_syscnt_freq2(void)
150 {
151 return cpu_clock;
152 }
153
