1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "tmr.h"
22 #include "tmr_revb.h"
23 #include "tmr_common.h"
24 #include "stdbool.h"
25
MXC_TMR_Init(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg,bool init_pins)26 int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
27 {
28 uint8_t tmr_id = MXC_TMR_GET_IDX(tmr);
29 uint8_t clockSource = MXC_TMR_CLK0;
30
31 if (cfg == NULL) {
32 return E_NULL_PTR;
33 }
34
35 MXC_ASSERT(tmr_id >= 0);
36
37 switch (cfg->clock) {
38 case MXC_TMR_EXT_CLK:
39 clockSource = MXC_TMR_CLK1;
40 MXC_GPIO_Config(&gpio_cfg_extclk);
41 break;
42
43 case MXC_TMR_ERTCO_CLK:
44 if (tmr_id < 4) { // Timers 0-3 do not support this clock source
45 return E_NOT_SUPPORTED;
46 }
47
48 clockSource = MXC_TMR_CLK2;
49 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO);
50 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ);
51 break;
52
53 case MXC_TMR_INRO_CLK:
54 if (tmr_id < 4) { // Timers 0-3 do not support this clock source
55 return E_NOT_SUPPORTED;
56 }
57
58 clockSource = MXC_TMR_CLK3;
59 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO);
60 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, INRO_FREQ);
61 break;
62
63 case MXC_TMR_IBRO_CLK:
64 if (tmr_id > 3) { // TImers 4-5 do not support this clock source
65 return E_NOT_SUPPORTED;
66 }
67
68 clockSource = MXC_TMR_CLK2;
69 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
70 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, IBRO_FREQ);
71 break;
72
73 case MXC_TMR_ERFO_CLK:
74 if (tmr_id > 3) { // Timers 4-5 do not support this clock source
75 return E_NOT_SUPPORTED;
76 }
77
78 clockSource = MXC_TMR_CLK3;
79 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO);
80 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERFO_FREQ);
81 break;
82
83 default:
84 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, PeripheralClock);
85 break;
86 }
87
88 #ifndef MSDK_NO_GPIO_CLK_INIT
89 //enable peripheral clock and configure gpio pins
90 switch (tmr_id) {
91 case 0:
92 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR0);
93 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0);
94
95 if (init_pins) {
96 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
97 MXC_GPIO_Config(&gpio_cfg_tmr0a);
98 }
99 }
100
101 break;
102
103 case 1:
104 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR1);
105 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1);
106
107 if (init_pins) {
108 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
109 MXC_GPIO_Config(&gpio_cfg_tmr1a);
110 }
111 }
112
113 break;
114
115 case 2:
116 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR2);
117 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2);
118
119 if (init_pins) {
120 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
121 MXC_GPIO_Config(&gpio_cfg_tmr2a);
122 }
123 }
124
125 break;
126
127 case 3:
128 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR3);
129 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR3);
130
131 if (init_pins) {
132 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
133 MXC_GPIO_Config(&gpio_cfg_tmr3a);
134 }
135 }
136
137 break;
138
139 case 4:
140 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4);
141 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4);
142
143 if (init_pins) {
144 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
145 MXC_GPIO_Config(&gpio_cfg_lptmr0);
146 } else {
147 return E_NOT_SUPPORTED;
148 break;
149 }
150 }
151
152 break;
153
154 case 5:
155 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5);
156 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5);
157
158 if (init_pins) {
159 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
160 MXC_GPIO_Config(&gpio_cfg_lptmr1);
161 } else {
162 return E_NOT_SUPPORTED;
163 break;
164 }
165 }
166
167 break;
168
169 default:
170 return E_NOT_SUPPORTED;
171 }
172 #else
173 (void)init_pins;
174 #endif
175
176 return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource);
177 }
178
MXC_TMR_Shutdown(mxc_tmr_regs_t * tmr)179 void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
180 {
181 uint8_t tmr_id = MXC_TMR_GET_IDX(tmr);
182
183 MXC_ASSERT(tmr_id >= 0);
184
185 MXC_TMR_RevB_Shutdown((mxc_tmr_revb_regs_t *)tmr);
186
187 // System settigns
188 //diasble peripheral clock
189 switch (tmr_id) {
190 case 0:
191 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0);
192 break;
193
194 case 1:
195 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1);
196 break;
197
198 case 2:
199 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
200 break;
201
202 case 3:
203 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR3);
204 break;
205
206 case 4:
207 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR4);
208 break;
209
210 case 5:
211 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR5);
212 break;
213 }
214 }
215
MXC_TMR_Start(mxc_tmr_regs_t * tmr)216 void MXC_TMR_Start(mxc_tmr_regs_t *tmr)
217 {
218 MXC_TMR_RevB_Start((mxc_tmr_revb_regs_t *)tmr);
219 }
220
MXC_TMR_Stop(mxc_tmr_regs_t * tmr)221 void MXC_TMR_Stop(mxc_tmr_regs_t *tmr)
222 {
223 MXC_TMR_RevB_Stop((mxc_tmr_revb_regs_t *)tmr);
224 }
225
MXC_TMR_SetPWM(mxc_tmr_regs_t * tmr,uint32_t pwm)226 int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm)
227 {
228 return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t *)tmr, pwm);
229 }
230
MXC_TMR_GetCompare(mxc_tmr_regs_t * tmr)231 uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr)
232 {
233 return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr);
234 }
235
MXC_TMR_GetCapture(mxc_tmr_regs_t * tmr)236 uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr)
237 {
238 return MXC_TMR_RevB_GetCapture((mxc_tmr_revb_regs_t *)tmr);
239 }
240
MXC_TMR_GetPeriod(mxc_tmr_regs_t * tmr,mxc_tmr_clock_t clock,uint32_t prescalar,uint32_t frequency)241 uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar,
242 uint32_t frequency)
243 {
244 uint32_t clockFrequency = PeripheralClock;
245 uint8_t tmr_id = MXC_TMR_GET_IDX(tmr);
246
247 MXC_ASSERT(tmr_id >= 0);
248
249 if (tmr_id > 3) {
250 switch (clock) {
251 case MXC_TMR_APB_CLK:
252 clockFrequency = (PeripheralClock / 4);
253 break;
254
255 case MXC_TMR_ERTCO_CLK:
256 clockFrequency = ERTCO_FREQ;
257 break;
258
259 case MXC_TMR_INRO_CLK:
260 clockFrequency = INRO_FREQ;
261 break;
262
263 default:
264 break;
265 }
266 } else {
267 switch (clock) {
268 case MXC_TMR_APB_CLK:
269 clockFrequency = PeripheralClock;
270 break;
271
272 case MXC_TMR_IBRO_CLK:
273 clockFrequency = IBRO_FREQ;
274 break;
275
276 case MXC_TMR_ERFO_CLK:
277 clockFrequency = ERFO_FREQ; // Note: Could vary between 16-32Mhz. ERFO_FREQ should be
278 // overridden for custom designs.
279 break;
280
281 default:
282 break;
283 }
284 }
285
286 return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t *)tmr, clockFrequency, prescalar, frequency);
287 }
288
MXC_TMR_GetCount(mxc_tmr_regs_t * tmr)289 uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr)
290 {
291 return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t *)tmr);
292 }
293
MXC_TMR_ClearFlags(mxc_tmr_regs_t * tmr)294 void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr)
295 {
296 MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t *)tmr);
297 }
298
MXC_TMR_GetFlags(mxc_tmr_regs_t * tmr)299 uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr)
300 {
301 return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t *)tmr);
302 }
303
MXC_TMR_EnableInt(mxc_tmr_regs_t * tmr)304 void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr)
305 {
306 MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t *)tmr);
307 }
308
MXC_TMR_DisableInt(mxc_tmr_regs_t * tmr)309 void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr)
310 {
311 MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t *)tmr);
312 }
313
MXC_TMR_EnableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)314 void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
315 {
316 MXC_TMR_RevB_EnableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
317 }
318
MXC_TMR_DisableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)319 void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
320 {
321 MXC_TMR_RevB_DisableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
322 }
323
MXC_TMR_SetCompare(mxc_tmr_regs_t * tmr,uint32_t cmp_cnt)324 void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
325 {
326 MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t *)tmr, cmp_cnt);
327 }
328
MXC_TMR_SetCount(mxc_tmr_regs_t * tmr,uint32_t cnt)329 void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
330 {
331 MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t *)tmr, cnt);
332 }
333
MXC_TMR_Delay(mxc_tmr_regs_t * tmr,uint32_t us)334 void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
335 {
336 MXC_TMR_Common_Delay(tmr, us);
337 }
338
MXC_TMR_TO_Start(mxc_tmr_regs_t * tmr,uint32_t us)339 void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us)
340 {
341 MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t *)tmr, us);
342 }
343
MXC_TMR_TO_Check(mxc_tmr_regs_t * tmr)344 int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr)
345 {
346 return MXC_TMR_Common_TO_Check(tmr);
347 }
348
MXC_TMR_TO_Stop(mxc_tmr_regs_t * tmr)349 void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr)
350 {
351 MXC_TMR_Common_TO_Stop(tmr);
352 }
353
MXC_TMR_TO_Clear(mxc_tmr_regs_t * tmr)354 void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr)
355 {
356 MXC_TMR_Common_TO_Clear(tmr);
357 }
358
MXC_TMR_TO_Elapsed(mxc_tmr_regs_t * tmr)359 unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr)
360 {
361 return MXC_TMR_Common_TO_Elapsed(tmr);
362 }
363
MXC_TMR_TO_Remaining(mxc_tmr_regs_t * tmr)364 unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr)
365 {
366 return MXC_TMR_Common_TO_Remaining(tmr);
367 }
368
MXC_TMR_SW_Start(mxc_tmr_regs_t * tmr)369 void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr)
370 {
371 MXC_TMR_Common_SW_Start(tmr);
372 }
373
MXC_TMR_SW_Stop(mxc_tmr_regs_t * tmr)374 unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr)
375 {
376 return MXC_TMR_Common_SW_Stop(tmr);
377 }
378
MXC_TMR_GetTime(mxc_tmr_regs_t * tmr,uint32_t ticks,uint32_t * time,mxc_tmr_unit_t * units)379 int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
380 {
381 return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t *)tmr, ticks, time, units);
382 }
383