1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "tmr.h"
22 #include "tmr_revb.h"
23 #include "tmr_common.h"
24 #include "lpgcr_regs.h"
25 #include "stdbool.h"
26
MXC_TMR_Init(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg,bool init_pins)27 int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
28 {
29 int tmr_id = MXC_TMR_GET_IDX(tmr);
30 uint8_t clockSource = MXC_TMR_CLK0;
31
32 if (cfg == NULL) {
33 return E_NULL_PTR;
34 }
35
36 MXC_ASSERT(tmr_id >= 0);
37
38 switch (cfg->clock) {
39 case MXC_TMR_ISO_CLK:
40 if (tmr_id > 3) { // Timers 4-5 do not support this clock source
41 return E_NOT_SUPPORTED;
42 }
43
44 clockSource = MXC_TMR_CLK1;
45 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ISO);
46 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ISO_FREQ);
47 break;
48
49 case MXC_TMR_IBRO_CLK:
50 if (tmr_id > 3) { // Timers 4-5 do not support this clock source
51 return E_NOT_SUPPORTED;
52 }
53
54 clockSource = MXC_TMR_CLK2;
55 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
56 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, IBRO_FREQ);
57 break;
58
59 case MXC_TMR_IBRO_DIV8_CLK:
60 if (tmr_id != 5) { // Only timer 5 supports this clock source
61 return E_NOT_SUPPORTED;
62 }
63
64 clockSource = MXC_TMR_CLK1;
65 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
66 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, (IBRO_FREQ / 8));
67 break;
68
69 #if (TARGET_NUM != 32680)
70 case MXC_TMR_ERTCO_CLK:
71 if (tmr_id == 4) {
72 clockSource = MXC_TMR_CLK1;
73 } else if (tmr_id < 4) {
74 clockSource = MXC_TMR_CLK3;
75 } else { // Timers 5 do not support this clock source
76 return E_NOT_SUPPORTED;
77 }
78
79 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO);
80 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ);
81 break;
82 #endif
83
84 case MXC_TMR_INRO_CLK:
85 if (tmr_id < 4) { // Timers 0-3 do not support this clock source
86 return E_NOT_SUPPORTED;
87 }
88
89 clockSource = MXC_TMR_CLK2;
90 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO);
91 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, INRO_FREQ);
92 break;
93
94 default:
95 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, PeripheralClock);
96 break;
97 }
98
99 #ifndef MSDK_NO_GPIO_CLK_INIT
100 //enable peripheral clock and configure gpio pins
101 switch (tmr_id) {
102 case 0:
103 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR0);
104 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0);
105
106 if (init_pins) {
107 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
108 MXC_GPIO_Config(&gpio_cfg_tmr0);
109 } else {
110 MXC_GPIO_Config(&gpio_cfg_tmr0b);
111 }
112 }
113
114 break;
115
116 case 1:
117 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR1);
118 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1);
119
120 if (init_pins) {
121 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
122 MXC_GPIO_Config(&gpio_cfg_tmr1);
123 } else {
124 MXC_GPIO_Config(&gpio_cfg_tmr1b);
125 }
126 }
127
128 break;
129
130 case 2:
131 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR2);
132 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2);
133
134 if (init_pins) {
135 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
136 MXC_GPIO_Config(&gpio_cfg_tmr2);
137 } else {
138 MXC_GPIO_Config(&gpio_cfg_tmr2b);
139 }
140 }
141
142 break;
143
144 case 3:
145 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR3);
146 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR3);
147
148 if (init_pins) {
149 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
150 MXC_GPIO_Config(&gpio_cfg_tmr3);
151 } else {
152 MXC_GPIO_Config(&gpio_cfg_tmr3b);
153 }
154 }
155
156 break;
157
158 case 4:
159 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4);
160 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4);
161 break;
162
163 case 5:
164 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5);
165 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5);
166 break;
167 }
168 #else
169 (void)init_pins;
170 #endif
171
172 return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource);
173 }
174
MXC_TMR_Shutdown(mxc_tmr_regs_t * tmr)175 void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
176 {
177 MXC_ASSERT(MXC_TMR_GET_IDX(tmr) >= 0);
178
179 MXC_TMR_RevB_Shutdown((mxc_tmr_revb_regs_t *)tmr);
180
181 // System settigns
182 //diasble peripheral clock
183 if (tmr == MXC_TMR0) {
184 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0);
185 }
186
187 if (tmr == MXC_TMR1) {
188 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1);
189 }
190
191 if (tmr == MXC_TMR2) {
192 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
193 }
194
195 if (tmr == MXC_TMR3) {
196 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR3);
197 }
198
199 if (tmr == MXC_TMR4) {
200 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR4);
201 }
202
203 if (tmr == MXC_TMR5) {
204 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR5);
205 }
206 }
207
MXC_TMR_Start(mxc_tmr_regs_t * tmr)208 void MXC_TMR_Start(mxc_tmr_regs_t *tmr)
209 {
210 MXC_TMR_RevB_Start((mxc_tmr_revb_regs_t *)tmr);
211 }
212
MXC_TMR_Stop(mxc_tmr_regs_t * tmr)213 void MXC_TMR_Stop(mxc_tmr_regs_t *tmr)
214 {
215 MXC_TMR_RevB_Stop((mxc_tmr_revb_regs_t *)tmr);
216 }
217
MXC_TMR_SetPWM(mxc_tmr_regs_t * tmr,uint32_t pwm)218 int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm)
219 {
220 return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t *)tmr, pwm);
221 }
222
MXC_TMR_GetCompare(mxc_tmr_regs_t * tmr)223 uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr)
224 {
225 return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr);
226 }
227
MXC_TMR_GetCapture(mxc_tmr_regs_t * tmr)228 uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr)
229 {
230 return MXC_TMR_RevB_GetCapture((mxc_tmr_revb_regs_t *)tmr);
231 }
232
MXC_TMR_GetPeriod(mxc_tmr_regs_t * tmr,mxc_tmr_clock_t clock,uint32_t prescalar,uint32_t frequency)233 uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar,
234 uint32_t frequency)
235 {
236 uint32_t clockFrequency = PeripheralClock;
237 int tmr_id = MXC_TMR_GET_IDX(tmr);
238
239 MXC_ASSERT(tmr_id >= 0);
240
241 if (tmr_id > 3) {
242 switch (clock) {
243 case MXC_TMR_APB_CLK:
244 clockFrequency = IBRO_FREQ;
245 break;
246
247 #if (TARGET_NUM != 32680)
248 case MXC_TMR_ERTCO_CLK:
249 clockFrequency = ERTCO_FREQ;
250 break;
251 #endif
252
253 case MXC_TMR_INRO_CLK:
254 clockFrequency = INRO_FREQ;
255 break;
256
257 case MXC_TMR_IBRO_DIV8_CLK:
258 clockFrequency = IBRO_FREQ / 8;
259 break;
260
261 default:
262 break;
263 }
264 } else {
265 switch (clock) {
266 case MXC_TMR_APB_CLK:
267 clockFrequency = PeripheralClock;
268 break;
269
270 case MXC_TMR_ISO_CLK:
271 clockFrequency = ISO_FREQ;
272 break;
273
274 case MXC_TMR_IBRO_CLK:
275 clockFrequency = IBRO_FREQ;
276 break;
277
278 #if (TARGET_NUM != 32680)
279 case MXC_TMR_ERTCO_CLK:
280 clockFrequency = ERTCO_FREQ;
281 break;
282 #endif
283
284 default:
285 break;
286 }
287 }
288
289 return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t *)tmr, clockFrequency, prescalar, frequency);
290 }
291
MXC_TMR_GetCount(mxc_tmr_regs_t * tmr)292 uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr)
293 {
294 return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t *)tmr);
295 }
296
MXC_TMR_ClearFlags(mxc_tmr_regs_t * tmr)297 void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr)
298 {
299 MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t *)tmr);
300 }
301
MXC_TMR_GetFlags(mxc_tmr_regs_t * tmr)302 uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr)
303 {
304 return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t *)tmr);
305 }
306
MXC_TMR_EnableInt(mxc_tmr_regs_t * tmr)307 void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr)
308 {
309 MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t *)tmr);
310 }
311
MXC_TMR_DisableInt(mxc_tmr_regs_t * tmr)312 void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr)
313 {
314 MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t *)tmr);
315 }
316
MXC_TMR_EnableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)317 void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
318 {
319 MXC_TMR_RevB_EnableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
320 }
321
MXC_TMR_DisableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)322 void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
323 {
324 MXC_TMR_RevB_DisableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
325 }
326
MXC_TMR_SetCompare(mxc_tmr_regs_t * tmr,uint32_t cmp_cnt)327 void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
328 {
329 MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t *)tmr, cmp_cnt);
330 }
331
MXC_TMR_SetCount(mxc_tmr_regs_t * tmr,uint32_t cnt)332 void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
333 {
334 MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t *)tmr, cnt);
335 }
336
MXC_TMR_Delay(mxc_tmr_regs_t * tmr,uint32_t us)337 void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
338 {
339 MXC_TMR_Common_Delay(tmr, us);
340 }
341
MXC_TMR_TO_Start(mxc_tmr_regs_t * tmr,uint32_t us)342 void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us)
343 {
344 MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t *)tmr, us);
345 }
346
MXC_TMR_TO_Check(mxc_tmr_regs_t * tmr)347 int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr)
348 {
349 return MXC_TMR_Common_TO_Check(tmr);
350 }
351
MXC_TMR_TO_Stop(mxc_tmr_regs_t * tmr)352 void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr)
353 {
354 MXC_TMR_Common_TO_Stop(tmr);
355 }
356
MXC_TMR_TO_Clear(mxc_tmr_regs_t * tmr)357 void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr)
358 {
359 MXC_TMR_Common_TO_Clear(tmr);
360 }
361
MXC_TMR_TO_Elapsed(mxc_tmr_regs_t * tmr)362 unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr)
363 {
364 return MXC_TMR_Common_TO_Elapsed(tmr);
365 }
366
MXC_TMR_TO_Remaining(mxc_tmr_regs_t * tmr)367 unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr)
368 {
369 return MXC_TMR_Common_TO_Remaining(tmr);
370 }
371
MXC_TMR_SW_Start(mxc_tmr_regs_t * tmr)372 void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr)
373 {
374 MXC_TMR_Common_SW_Start(tmr);
375 }
376
MXC_TMR_SW_Stop(mxc_tmr_regs_t * tmr)377 unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr)
378 {
379 return MXC_TMR_Common_SW_Stop(tmr);
380 }
381
MXC_TMR_GetTime(mxc_tmr_regs_t * tmr,uint32_t ticks,uint32_t * time,mxc_tmr_unit_t * units)382 int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
383 {
384 return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t *)tmr, ticks, time, units);
385 }
386
MXC_TMR_GetTicks(mxc_tmr_regs_t * tmr,uint32_t time,mxc_tmr_unit_t units,uint32_t * ticks)387 int MXC_TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, uint32_t *ticks)
388 {
389 return MXC_TMR_RevB_GetTicks((mxc_tmr_revb_regs_t *)tmr, time, units, ticks);
390 }
391
