1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include <stdbool.h>
22 #include "tmr.h"
23 #include "tmr_revb.h"
24 #include "tmr_common.h"
25 #include "mcr_regs.h"
26
MXC_TMR_Init(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg,bool init_pins)27 int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
28 {
29 int tmr_id = MXC_TMR_GET_IDX(tmr);
30 uint8_t clockSource = MXC_TMR_CLK0;
31
32 if (cfg == NULL) {
33 return E_NULL_PTR;
34 }
35
36 MXC_ASSERT(tmr_id >= 0);
37
38 switch (cfg->clock) {
39 case MXC_TMR_EXT_CLK:
40 clockSource = MXC_TMR_CLK1;
41 #if TARGET_NUM != 32675
42 if (tmr_id < 4) {
43 MXC_GPIO_Config(&gpio_cfg_hfextclk);
44 } else {
45 MXC_GPIO_Config(&gpio_cfg_lpextclk);
46 }
47 #else
48 MXC_GPIO_Config(&gpio_cfg_extclk);
49 #endif
50 break;
51
52 case MXC_TMR_ERTCO_CLK:
53 if (tmr_id < 4) {
54 return E_NOT_SUPPORTED;
55 }
56 clockSource = MXC_TMR_CLK2;
57 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO);
58 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ);
59 break;
60
61 case MXC_TMR_INRO_CLK:
62 if (tmr_id < 4) {
63 return E_NOT_SUPPORTED;
64 }
65 clockSource = MXC_TMR_CLK3;
66 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO);
67 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, INRO_FREQ);
68 break;
69
70 case MXC_TMR_IBRO_CLK:
71 if (tmr_id > 3) {
72 return E_NOT_SUPPORTED;
73 }
74 clockSource = MXC_TMR_CLK2;
75 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
76 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, IBRO_FREQ);
77 break;
78
79 case MXC_TMR_ERFO_CLK:
80 if (tmr_id > 3) {
81 return E_NOT_SUPPORTED;
82 }
83 clockSource = MXC_TMR_CLK3;
84 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO);
85 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERFO_FREQ);
86 break;
87
88 default:
89 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, PeripheralClock);
90 break;
91 }
92
93 #ifndef MSDK_NO_GPIO_CLK_INIT
94 //enable peripheral clock and configure gpio pins
95 switch (tmr_id) {
96 case 0:
97 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR0);
98 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0);
99
100 if (init_pins) {
101 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
102 MXC_GPIO_Config(&gpio_cfg_tmr0);
103 }
104 }
105
106 break;
107
108 case 1:
109 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR1);
110 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1);
111
112 if (init_pins) {
113 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
114 MXC_GPIO_Config(&gpio_cfg_tmr1);
115 }
116 }
117
118 break;
119
120 case 2:
121 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR2);
122 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2);
123
124 if (init_pins) {
125 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
126 MXC_GPIO_Config(&gpio_cfg_tmr2);
127 }
128 }
129
130 break;
131
132 case 3:
133 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR3);
134 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR3);
135
136 if (init_pins) {
137 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
138 MXC_GPIO_Config(&gpio_cfg_tmr3);
139 }
140 }
141
142 break;
143
144 case 4:
145 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4);
146 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4);
147
148 if (init_pins) {
149 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
150 MXC_GPIO_Config(&gpio_cfg_tmr4);
151 #if TARGET_NUM == 32670
152 MXC_MCR->lppioctrl |= MXC_F_MCR_LPPIOCTRL_LPTMR0_I | MXC_F_MCR_LPPIOCTRL_LPTMR0_O;
153 #endif
154 } else {
155 return E_NOT_SUPPORTED;
156 }
157 }
158
159 break;
160
161 case 5:
162 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5);
163 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5);
164
165 if (init_pins) {
166 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
167 MXC_GPIO_Config(&gpio_cfg_tmr5);
168 #if TARGET_NUM == 32670
169 MXC_MCR->lppioctrl |= MXC_F_MCR_LPPIOCTRL_LPTMR1_I | MXC_F_MCR_LPPIOCTRL_LPTMR1_O;
170 #endif
171 } else {
172 return E_NOT_SUPPORTED;
173 }
174 }
175
176 break;
177 }
178 #else
179 (void)init_pins;
180 #endif
181
182 return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource);
183 }
184
MXC_TMR_Shutdown(mxc_tmr_regs_t * tmr)185 void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
186 {
187 int tmr_id = MXC_TMR_GET_IDX(tmr);
188
189 MXC_ASSERT(tmr_id >= 0);
190
191 MXC_TMR_RevB_Shutdown((mxc_tmr_revb_regs_t *)tmr);
192
193 // System settigns
194 //diasble peripheral clock
195 switch (tmr_id) {
196 case 0:
197 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0);
198 break;
199
200 case 1:
201 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1);
202 break;
203
204 case 2:
205 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
206 break;
207
208 case 3:
209 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR3);
210 break;
211
212 case 4:
213 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR4);
214 #if TARGET_NUM == 32670
215 MXC_MCR->lppioctrl &= ~(MXC_F_MCR_LPPIOCTRL_LPTMR0_I | MXC_F_MCR_LPPIOCTRL_LPTMR0_O);
216 #endif
217 break;
218
219 case 5:
220 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR5);
221 #if TARGET_NUM == 32670
222 MXC_MCR->lppioctrl &= ~(MXC_F_MCR_LPPIOCTRL_LPTMR1_I | MXC_F_MCR_LPPIOCTRL_LPTMR1_O);
223 #endif
224 break;
225 }
226 }
227
MXC_TMR_Start(mxc_tmr_regs_t * tmr)228 void MXC_TMR_Start(mxc_tmr_regs_t *tmr)
229 {
230 MXC_TMR_RevB_Start((mxc_tmr_revb_regs_t *)tmr);
231 }
232
MXC_TMR_Stop(mxc_tmr_regs_t * tmr)233 void MXC_TMR_Stop(mxc_tmr_regs_t *tmr)
234 {
235 MXC_TMR_RevB_Stop((mxc_tmr_revb_regs_t *)tmr);
236 }
237
MXC_TMR_SetPWM(mxc_tmr_regs_t * tmr,uint32_t pwm)238 int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm)
239 {
240 return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t *)tmr, pwm);
241 }
242
MXC_TMR_GetCompare(mxc_tmr_regs_t * tmr)243 uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr)
244 {
245 return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr);
246 }
247
MXC_TMR_GetCapture(mxc_tmr_regs_t * tmr)248 uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr)
249 {
250 return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr);
251 }
252
MXC_TMR_GetPeriod(mxc_tmr_regs_t * tmr,mxc_tmr_clock_t clock,uint32_t prescalar,uint32_t frequency)253 uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar,
254 uint32_t frequency)
255 {
256 uint32_t clockFrequency = PeripheralClock;
257 int tmr_id = MXC_TMR_GET_IDX(tmr);
258
259 MXC_ASSERT(tmr_id >= 0);
260
261 if (tmr_id > 3) {
262 switch (clock) {
263 case MXC_TMR_APB_CLK:
264 clockFrequency = (PeripheralClock / 4);
265 break;
266
267 case MXC_TMR_ERTCO_CLK:
268 clockFrequency = ERTCO_FREQ;
269 break;
270
271 case MXC_TMR_INRO_CLK:
272 clockFrequency = INRO_FREQ;
273 break;
274
275 default:
276 break;
277 }
278 } else {
279 switch (clock) {
280 case MXC_TMR_APB_CLK:
281 clockFrequency = PeripheralClock;
282 break;
283
284 case MXC_TMR_IBRO_CLK:
285 clockFrequency = IBRO_FREQ;
286 break;
287
288 case MXC_TMR_ERFO_CLK:
289 clockFrequency = ERFO_FREQ;
290 break;
291
292 default:
293 break;
294 }
295 }
296
297 return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t *)tmr, clockFrequency, prescalar, frequency);
298 }
299
MXC_TMR_GetCount(mxc_tmr_regs_t * tmr)300 uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr)
301 {
302 return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t *)tmr);
303 }
304
MXC_TMR_ClearFlags(mxc_tmr_regs_t * tmr)305 void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr)
306 {
307 MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t *)tmr);
308 }
309
MXC_TMR_GetFlags(mxc_tmr_regs_t * tmr)310 uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr)
311 {
312 return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t *)tmr);
313 }
314
MXC_TMR_EnableInt(mxc_tmr_regs_t * tmr)315 void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr)
316 {
317 MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t *)tmr);
318 }
319
MXC_TMR_DisableInt(mxc_tmr_regs_t * tmr)320 void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr)
321 {
322 MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t *)tmr);
323 }
324
MXC_TMR_EnableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)325 void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
326 {
327 MXC_TMR_RevB_EnableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
328 }
329
MXC_TMR_DisableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)330 void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
331 {
332 MXC_TMR_RevB_DisableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
333 }
334
MXC_TMR_SetCompare(mxc_tmr_regs_t * tmr,uint32_t cmp_cnt)335 void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
336 {
337 MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t *)tmr, cmp_cnt);
338 }
339
MXC_TMR_SetCount(mxc_tmr_regs_t * tmr,uint32_t cnt)340 void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
341 {
342 MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t *)tmr, cnt);
343 }
344
MXC_TMR_Delay(mxc_tmr_regs_t * tmr,uint32_t us)345 void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
346 {
347 MXC_TMR_Common_Delay(tmr, us);
348 }
349
MXC_TMR_TO_Start(mxc_tmr_regs_t * tmr,uint32_t us)350 void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us)
351 {
352 MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t *)tmr, us);
353 }
354
MXC_TMR_TO_Check(mxc_tmr_regs_t * tmr)355 int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr)
356 {
357 return MXC_TMR_Common_TO_Check(tmr);
358 }
359
MXC_TMR_TO_Stop(mxc_tmr_regs_t * tmr)360 void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr)
361 {
362 MXC_TMR_Common_TO_Stop(tmr);
363 }
364
MXC_TMR_TO_Clear(mxc_tmr_regs_t * tmr)365 void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr)
366 {
367 MXC_TMR_Common_TO_Clear(tmr);
368 }
369
MXC_TMR_TO_Elapsed(mxc_tmr_regs_t * tmr)370 unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr)
371 {
372 return MXC_TMR_Common_TO_Elapsed(tmr);
373 }
374
MXC_TMR_TO_Remaining(mxc_tmr_regs_t * tmr)375 unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr)
376 {
377 return MXC_TMR_Common_TO_Remaining(tmr);
378 }
379
MXC_TMR_SW_Start(mxc_tmr_regs_t * tmr)380 void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr)
381 {
382 MXC_TMR_Common_SW_Start(tmr);
383 }
384
MXC_TMR_SW_Stop(mxc_tmr_regs_t * tmr)385 unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr)
386 {
387 return MXC_TMR_Common_SW_Stop(tmr);
388 }
389
MXC_TMR_GetTime(mxc_tmr_regs_t * tmr,uint32_t ticks,uint32_t * time,mxc_tmr_unit_t * units)390 int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
391 {
392 return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t *)tmr, ticks, time, units);
393 }
394
