1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "tmr.h"
22 #include "tmr_revb.h"
23 #include "tmr_common.h"
24 #include "lpgcr_regs.h"
25 #include "stdbool.h"
26
MXC_TMR_Init(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg,bool init_pins)27 int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
28 {
29 uint8_t tmr_id;
30 uint8_t clockSource = MXC_TMR_CLK0;
31
32 if (cfg == NULL) {
33 return E_NULL_PTR;
34 }
35
36 tmr_id = MXC_TMR_GET_IDX(tmr);
37 MXC_ASSERT(tmr_id >= 0);
38
39 switch (cfg->clock) {
40 case MXC_TMR_ISO_CLK:
41 if (tmr_id > 3) { // Timers 4-5 do not support this clock source
42 return E_NOT_SUPPORTED;
43 }
44
45 clockSource = MXC_TMR_CLK1;
46 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ISO);
47 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ISO_FREQ);
48 break;
49
50 case MXC_TMR_IBRO_CLK:
51 if (tmr_id > 3) { // Timers 4-5 do not support this clock source
52 return E_NOT_SUPPORTED;
53 }
54
55 clockSource = MXC_TMR_CLK2;
56 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
57 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, IBRO_FREQ);
58 break;
59
60 case MXC_TMR_ERTCO_CLK:
61 if (tmr_id == 4) {
62 clockSource = MXC_TMR_CLK1;
63 } else if (tmr_id < 4) {
64 clockSource = MXC_TMR_CLK3;
65 } else { // Timers 5 do not support this clock source
66 return E_NOT_SUPPORTED;
67 }
68
69 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO);
70 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ);
71 break;
72
73 case MXC_TMR_INRO_CLK:
74 if (tmr_id < 4) { // Timers 0-3 do not support this clock source
75 return E_NOT_SUPPORTED;
76 }
77
78 clockSource = MXC_TMR_CLK2;
79 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO);
80 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, INRO_FREQ);
81 break;
82
83 default:
84 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, PeripheralClock);
85 break;
86 }
87
88 #ifndef MSDK_NO_GPIO_CLK_INIT
89 //enable peripheral clock and configure gpio pins
90 switch (tmr_id) {
91 case 0:
92 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR0);
93 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0);
94
95 if (init_pins) {
96 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
97 MXC_GPIO_Config(&gpio_cfg_tmr0);
98 } else {
99 MXC_GPIO_Config(&gpio_cfg_tmr0b);
100 }
101 }
102
103 break;
104
105 case 1:
106 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR1);
107 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1);
108
109 if (init_pins) {
110 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
111 MXC_GPIO_Config(&gpio_cfg_tmr1);
112 } else {
113 MXC_GPIO_Config(&gpio_cfg_tmr1b);
114 }
115 }
116
117 break;
118
119 case 2:
120 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR2);
121 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2);
122
123 if (init_pins) {
124 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
125 MXC_GPIO_Config(&gpio_cfg_tmr2);
126 } else {
127 MXC_GPIO_Config(&gpio_cfg_tmr2b);
128 }
129 }
130
131 break;
132
133 case 3:
134 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR3);
135 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR3);
136
137 if (init_pins) {
138 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
139 MXC_GPIO_Config(&gpio_cfg_tmr3);
140 } else {
141 MXC_GPIO_Config(&gpio_cfg_tmr3b);
142 }
143 }
144
145 break;
146
147 case 4:
148 MXC_GPIO_Config(&gpio_cfg_tmr4);
149 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4);
150 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4);
151 break;
152
153 case 5:
154 MXC_GPIO_Config(&gpio_cfg_tmr5);
155 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5);
156 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5);
157 break;
158 }
159 #else
160 (void)init_pins;
161 #endif
162
163 return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource);
164 }
165
MXC_TMR_Shutdown(mxc_tmr_regs_t * tmr)166 void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
167 {
168 MXC_ASSERT(MXC_TMR_GET_IDX(tmr) >= 0);
169
170 MXC_TMR_RevB_Shutdown((mxc_tmr_revb_regs_t *)tmr);
171
172 // System settigns
173 //diasble peripheral clock
174 if (tmr == MXC_TMR0) {
175 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0);
176 }
177
178 if (tmr == MXC_TMR1) {
179 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1);
180 }
181
182 if (tmr == MXC_TMR2) {
183 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
184 }
185
186 if (tmr == MXC_TMR3) {
187 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR3);
188 }
189
190 if (tmr == MXC_TMR4) {
191 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR4);
192 }
193
194 if (tmr == MXC_TMR5) {
195 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR5);
196 }
197 }
198
MXC_TMR_Start(mxc_tmr_regs_t * tmr)199 void MXC_TMR_Start(mxc_tmr_regs_t *tmr)
200 {
201 MXC_TMR_RevB_Start((mxc_tmr_revb_regs_t *)tmr);
202 }
203
MXC_TMR_Stop(mxc_tmr_regs_t * tmr)204 void MXC_TMR_Stop(mxc_tmr_regs_t *tmr)
205 {
206 MXC_TMR_RevB_Stop((mxc_tmr_revb_regs_t *)tmr);
207 }
208
MXC_TMR_SetPWM(mxc_tmr_regs_t * tmr,uint32_t pwm)209 int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm)
210 {
211 return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t *)tmr, pwm);
212 }
213
MXC_TMR_GetCompare(mxc_tmr_regs_t * tmr)214 uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr)
215 {
216 return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr);
217 }
218
MXC_TMR_GetCapture(mxc_tmr_regs_t * tmr)219 uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr)
220 {
221 return MXC_TMR_RevB_GetCapture((mxc_tmr_revb_regs_t *)tmr);
222 }
223
MXC_TMR_GetPeriod(mxc_tmr_regs_t * tmr,mxc_tmr_clock_t clock,uint32_t prescalar,uint32_t frequency)224 uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar,
225 uint32_t frequency)
226 {
227 uint32_t clockFrequency = PeripheralClock;
228 uint8_t tmr_id = MXC_TMR_GET_IDX(tmr);
229
230 MXC_ASSERT(tmr_id >= 0);
231
232 if (tmr_id > 3) {
233 switch (clock) {
234 case MXC_TMR_APB_CLK:
235 clockFrequency = IBRO_FREQ;
236 break;
237
238 case MXC_TMR_ERTCO_CLK:
239 clockFrequency = ERTCO_FREQ;
240 break;
241
242 case MXC_TMR_8K_CLK:
243 clockFrequency = INRO_FREQ;
244 break;
245
246 default:
247 break;
248 }
249 } else {
250 switch (clock) {
251 case MXC_TMR_APB_CLK:
252 clockFrequency = PeripheralClock;
253 break;
254
255 case MXC_TMR_ISO_CLK:
256 clockFrequency = ISO_FREQ;
257 break;
258
259 case MXC_TMR_IBRO_CLK:
260 clockFrequency = IBRO_FREQ;
261 break;
262
263 case MXC_TMR_ERTCO_CLK:
264 clockFrequency = ERTCO_FREQ;
265 break;
266
267 default:
268 break;
269 }
270 }
271
272 return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t *)tmr, clockFrequency, prescalar, frequency);
273 }
274
MXC_TMR_GetCount(mxc_tmr_regs_t * tmr)275 uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr)
276 {
277 return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t *)tmr);
278 }
279
MXC_TMR_ClearFlags(mxc_tmr_regs_t * tmr)280 void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr)
281 {
282 MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t *)tmr);
283 }
284
MXC_TMR_GetFlags(mxc_tmr_regs_t * tmr)285 uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr)
286 {
287 return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t *)tmr);
288 }
289
MXC_TMR_EnableInt(mxc_tmr_regs_t * tmr)290 void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr)
291 {
292 MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t *)tmr);
293 }
294
MXC_TMR_DisableInt(mxc_tmr_regs_t * tmr)295 void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr)
296 {
297 MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t *)tmr);
298 }
299
MXC_TMR_EnableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)300 void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
301 {
302 MXC_TMR_RevB_EnableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
303 }
304
MXC_TMR_DisableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)305 void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
306 {
307 MXC_TMR_RevB_DisableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
308 }
309
MXC_TMR_SetCompare(mxc_tmr_regs_t * tmr,uint32_t cmp_cnt)310 void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
311 {
312 MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t *)tmr, cmp_cnt);
313 }
314
MXC_TMR_SetCount(mxc_tmr_regs_t * tmr,uint32_t cnt)315 void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
316 {
317 MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t *)tmr, cnt);
318 }
319
MXC_TMR_Delay(mxc_tmr_regs_t * tmr,uint32_t us)320 void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
321 {
322 MXC_TMR_Common_Delay(tmr, us);
323 }
324
MXC_TMR_TO_Start(mxc_tmr_regs_t * tmr,uint32_t us)325 void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us)
326 {
327 MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t *)tmr, us);
328 }
329
MXC_TMR_TO_Check(mxc_tmr_regs_t * tmr)330 int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr)
331 {
332 return MXC_TMR_Common_TO_Check(tmr);
333 }
334
MXC_TMR_TO_Stop(mxc_tmr_regs_t * tmr)335 void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr)
336 {
337 MXC_TMR_Common_TO_Stop(tmr);
338 }
339
MXC_TMR_TO_Clear(mxc_tmr_regs_t * tmr)340 void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr)
341 {
342 MXC_TMR_Common_TO_Clear(tmr);
343 }
344
MXC_TMR_TO_Elapsed(mxc_tmr_regs_t * tmr)345 unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr)
346 {
347 return MXC_TMR_Common_TO_Elapsed(tmr);
348 }
349
MXC_TMR_TO_Remaining(mxc_tmr_regs_t * tmr)350 unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr)
351 {
352 return MXC_TMR_Common_TO_Remaining(tmr);
353 }
354
MXC_TMR_SW_Start(mxc_tmr_regs_t * tmr)355 void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr)
356 {
357 return MXC_TMR_Common_SW_Start(tmr);
358 }
359
MXC_TMR_SW_Stop(mxc_tmr_regs_t * tmr)360 unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr)
361 {
362 return MXC_TMR_Common_SW_Stop(tmr);
363 }
364
MXC_TMR_GetTime(mxc_tmr_regs_t * tmr,uint32_t ticks,uint32_t * time,mxc_tmr_unit_t * units)365 int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
366 {
367 return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t *)tmr, ticks, time, units);
368 }
369
MXC_TMR_GetTicks(mxc_tmr_regs_t * tmr,uint32_t time,mxc_tmr_unit_t units,uint32_t * ticks)370 int MXC_TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, uint32_t *ticks)
371 {
372 return MXC_TMR_RevB_GetTicks((mxc_tmr_revb_regs_t *)tmr, time, units, ticks);
373 }
374
