1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "tmr.h"
22 #include "tmr_revb.h"
23 #include "tmr_common.h"
24 #include "lpgcr_regs.h"
25 #include "stdbool.h"
26
MXC_TMR_Init(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg,bool init_pins)27 int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
28 {
29 int tmr_id = MXC_TMR_GET_IDX(tmr);
30 uint8_t clockSource = MXC_TMR_CLK0;
31
32 if (cfg == NULL) {
33 return E_NULL_PTR;
34 }
35
36 MXC_ASSERT(tmr_id >= 0);
37
38 switch (cfg->clock) {
39 case MXC_TMR_ISO_CLK:
40 if (tmr_id > 3) { // Timers 4-5 do not support this clock source
41 return E_NOT_SUPPORTED;
42 }
43
44 clockSource = MXC_TMR_CLK1;
45 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ISO);
46 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ISO_FREQ);
47 break;
48
49 case MXC_TMR_IBRO_CLK:
50 if (tmr_id > 3) {
51 clockSource = MXC_TMR_CLK0;
52 } else {
53 clockSource = MXC_TMR_CLK2;
54 }
55
56 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
57 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, IBRO_FREQ);
58 break;
59
60 case MXC_TMR_ERTCO_CLK:
61 if (tmr_id == 4) {
62 clockSource = MXC_TMR_CLK1;
63 } else if (tmr_id < 4) {
64 clockSource = MXC_TMR_CLK3;
65 } else { // Timer 5 does not support this clock source
66 return E_NOT_SUPPORTED;
67 }
68
69 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO);
70 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ);
71 break;
72
73 case MXC_TMR_INRO_CLK:
74 if (tmr_id < 4) { // Timers 0-3 do not support this clock source
75 return E_NOT_SUPPORTED;
76 }
77
78 clockSource = MXC_TMR_CLK2;
79 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO);
80 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, INRO_FREQ);
81 break;
82
83 // IBRO/8
84 case MXC_TMR_IBRO_DIV8_CLK:
85 if (tmr_id != 5) { // Only Timer 5 supports this clock source divide
86 return E_NOT_SUPPORTED;
87 }
88
89 clockSource = MXC_TMR_CLK1;
90 MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
91 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, (IBRO_FREQ / 8));
92 break;
93
94 default:
95 // PCLK
96 MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, PeripheralClock);
97 break;
98 }
99
100 #ifndef MSDK_NO_GPIO_CLK_INIT
101 //enable peripheral clock and configure gpio pins
102 switch (tmr_id) {
103 case 0:
104 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR0);
105 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0);
106
107 if (init_pins) {
108 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
109 MXC_GPIO_Config(&gpio_cfg_tmr0);
110 } else {
111 MXC_GPIO_Config(&gpio_cfg_tmr0b);
112 }
113 }
114
115 break;
116
117 case 1:
118 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR1);
119 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1);
120
121 if (init_pins) {
122 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
123 MXC_GPIO_Config(&gpio_cfg_tmr1);
124 } else {
125 MXC_GPIO_Config(&gpio_cfg_tmr1b);
126 }
127 }
128
129 break;
130
131 case 2:
132 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR2);
133 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2);
134
135 if (init_pins) {
136 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
137 MXC_GPIO_Config(&gpio_cfg_tmr2);
138 } else {
139 MXC_GPIO_Config(&gpio_cfg_tmr2b);
140 }
141 }
142
143 break;
144
145 case 3:
146 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR3);
147 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR3);
148
149 if (init_pins) {
150 if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) {
151 MXC_GPIO_Config(&gpio_cfg_tmr3);
152 } else {
153 MXC_GPIO_Config(&gpio_cfg_tmr3b);
154 }
155 }
156
157 break;
158
159 case 4:
160 MXC_GPIO_Config(&gpio_cfg_tmr4);
161 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4);
162 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4);
163 break;
164
165 case 5:
166 MXC_GPIO_Config(&gpio_cfg_tmr5);
167 MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5);
168 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5);
169 break;
170 }
171 #else
172 (void)init_pins;
173 #endif
174
175 return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource);
176 }
177
MXC_TMR_Shutdown(mxc_tmr_regs_t * tmr)178 void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
179 {
180 MXC_ASSERT(MXC_TMR_GET_IDX(tmr) >= 0);
181
182 MXC_TMR_RevB_Shutdown((mxc_tmr_revb_regs_t *)tmr);
183
184 // System settigns
185 //diasble peripheral clock
186 if (tmr == MXC_TMR0) {
187 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0);
188 }
189
190 if (tmr == MXC_TMR1) {
191 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1);
192 }
193
194 if (tmr == MXC_TMR2) {
195 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
196 }
197
198 if (tmr == MXC_TMR3) {
199 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR3);
200 }
201
202 if (tmr == MXC_TMR4) {
203 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR4);
204 }
205
206 if (tmr == MXC_TMR5) {
207 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR5);
208 }
209 }
210
MXC_TMR_Start(mxc_tmr_regs_t * tmr)211 void MXC_TMR_Start(mxc_tmr_regs_t *tmr)
212 {
213 MXC_TMR_RevB_Start((mxc_tmr_revb_regs_t *)tmr);
214 }
215
MXC_TMR_Stop(mxc_tmr_regs_t * tmr)216 void MXC_TMR_Stop(mxc_tmr_regs_t *tmr)
217 {
218 MXC_TMR_RevB_Stop((mxc_tmr_revb_regs_t *)tmr);
219 }
220
MXC_TMR_SetPWM(mxc_tmr_regs_t * tmr,uint32_t pwm)221 int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm)
222 {
223 return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t *)tmr, pwm);
224 }
225
MXC_TMR_GetCompare(mxc_tmr_regs_t * tmr)226 uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr)
227 {
228 return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr);
229 }
230
MXC_TMR_GetCapture(mxc_tmr_regs_t * tmr)231 uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr)
232 {
233 return MXC_TMR_RevB_GetCapture((mxc_tmr_revb_regs_t *)tmr);
234 }
235
MXC_TMR_GetPeriod(mxc_tmr_regs_t * tmr,mxc_tmr_clock_t clock,uint32_t prescalar,uint32_t frequency)236 uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar,
237 uint32_t frequency)
238 {
239 uint32_t clockFrequency = PeripheralClock;
240 int tmr_id = MXC_TMR_GET_IDX(tmr);
241
242 MXC_ASSERT(tmr_id >= 0);
243
244 if (tmr_id > 3) {
245 switch (clock) {
246 case MXC_TMR_IBRO_CLK:
247 clockFrequency = IBRO_FREQ;
248 break;
249
250 case MXC_TMR_ERTCO_CLK:
251 clockFrequency = ERTCO_FREQ;
252 break;
253
254 case MXC_TMR_INRO_CLK:
255 clockFrequency = INRO_FREQ;
256 break;
257
258 default:
259 MXC_ASSERT(clock == MXC_TMR_IBRO_CLK || clock == MXC_TMR_ERTCO_CLK ||
260 clock == MXC_TMR_INRO_CLK);
261 break;
262 }
263 } else {
264 switch (clock) {
265 case MXC_TMR_APB_CLK:
266 clockFrequency = PeripheralClock;
267 break;
268
269 case MXC_TMR_ISO_CLK:
270 clockFrequency = ISO_FREQ;
271 break;
272
273 case MXC_TMR_IBRO_CLK:
274 clockFrequency = IBRO_FREQ;
275 break;
276
277 case MXC_TMR_ERTCO_CLK:
278 clockFrequency = ERTCO_FREQ;
279 break;
280
281 default:
282 MXC_ASSERT(clock == MXC_TMR_APB_CLK || clock == MXC_TMR_ISO_CLK ||
283 clock == MXC_TMR_IBRO_CLK || clock == MXC_TMR_ERTCO_CLK);
284 break;
285 }
286 }
287
288 return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t *)tmr, clockFrequency, prescalar, frequency);
289 }
290
MXC_TMR_GetCount(mxc_tmr_regs_t * tmr)291 uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr)
292 {
293 return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t *)tmr);
294 }
295
MXC_TMR_ClearFlags(mxc_tmr_regs_t * tmr)296 void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr)
297 {
298 MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t *)tmr);
299 }
300
MXC_TMR_GetFlags(mxc_tmr_regs_t * tmr)301 uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr)
302 {
303 return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t *)tmr);
304 }
305
MXC_TMR_EnableInt(mxc_tmr_regs_t * tmr)306 void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr)
307 {
308 MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t *)tmr);
309 }
310
MXC_TMR_DisableInt(mxc_tmr_regs_t * tmr)311 void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr)
312 {
313 MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t *)tmr);
314 }
315
MXC_TMR_EnableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)316 void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
317 {
318 MXC_TMR_RevB_EnableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
319 }
320
MXC_TMR_DisableWakeup(mxc_tmr_regs_t * tmr,mxc_tmr_cfg_t * cfg)321 void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg)
322 {
323 MXC_TMR_RevB_DisableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg);
324 }
325
MXC_TMR_SetCompare(mxc_tmr_regs_t * tmr,uint32_t cmp_cnt)326 void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
327 {
328 MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t *)tmr, cmp_cnt);
329 }
330
MXC_TMR_SetCount(mxc_tmr_regs_t * tmr,uint32_t cnt)331 void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
332 {
333 MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t *)tmr, cnt);
334 }
335
MXC_TMR_Delay(mxc_tmr_regs_t * tmr,uint32_t us)336 void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us)
337 {
338 MXC_TMR_Common_Delay(tmr, us);
339 }
340
MXC_TMR_TO_Start(mxc_tmr_regs_t * tmr,uint32_t us)341 void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us)
342 {
343 MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t *)tmr, us);
344 }
345
MXC_TMR_TO_Check(mxc_tmr_regs_t * tmr)346 int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr)
347 {
348 return MXC_TMR_Common_TO_Check(tmr);
349 }
350
MXC_TMR_TO_Stop(mxc_tmr_regs_t * tmr)351 void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr)
352 {
353 MXC_TMR_Common_TO_Stop(tmr);
354 }
355
MXC_TMR_TO_Clear(mxc_tmr_regs_t * tmr)356 void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr)
357 {
358 MXC_TMR_Common_TO_Clear(tmr);
359 }
360
MXC_TMR_TO_Elapsed(mxc_tmr_regs_t * tmr)361 unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr)
362 {
363 return MXC_TMR_Common_TO_Elapsed(tmr);
364 }
365
MXC_TMR_TO_Remaining(mxc_tmr_regs_t * tmr)366 unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr)
367 {
368 return MXC_TMR_Common_TO_Remaining(tmr);
369 }
370
MXC_TMR_SW_Start(mxc_tmr_regs_t * tmr)371 void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr)
372 {
373 MXC_TMR_Common_SW_Start(tmr);
374 }
375
MXC_TMR_SW_Stop(mxc_tmr_regs_t * tmr)376 unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr)
377 {
378 return MXC_TMR_Common_SW_Stop(tmr);
379 }
380
MXC_TMR_GetTime(mxc_tmr_regs_t * tmr,uint32_t ticks,uint32_t * time,mxc_tmr_unit_t * units)381 int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units)
382 {
383 return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t *)tmr, ticks, time, units);
384 }
385
