1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include <string.h>
22 #include <stdio.h>
23 #include <stdlib.h>
24 #include "max32690.h"
25 #include "gcr_regs.h"
26 #include "mxc_sys.h"
27 #include "icc.h"
28
29 extern void (*const __isr_vector[])(void);
30
31 uint32_t SystemCoreClock;
32 volatile uint32_t mailbox __attribute__((section(".mailbox")));
33
34 /*
35 The libc implementation from GCC 11+ depends on _getpid and _kill in some places.
36 There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore
37 we implement stub functions that return an error code to resolve linker warnings.
38 */
_getpid(void)39 __weak int _getpid(void)
40 {
41 return E_NOT_SUPPORTED;
42 }
43
_kill(void)44 __weak int _kill(void)
45 {
46 return E_NOT_SUPPORTED;
47 }
48
SystemCoreClockUpdate(void)49 __weak void SystemCoreClockUpdate(void)
50 {
51 uint32_t base_freq, div, clk_src;
52
53 // Get the clock source and frequency
54 clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL);
55 switch (clk_src) {
56 case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK:
57 base_freq = EXTCLK_FREQ;
58 break;
59 case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO:
60 base_freq = INRO_FREQ;
61 break;
62 case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO:
63 base_freq = IPO_FREQ;
64 break;
65 case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO:
66 base_freq = IBRO_FREQ;
67 break;
68 case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO:
69 base_freq = ISO_FREQ;
70 break;
71 case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO:
72 base_freq = ERTCO_FREQ;
73 break;
74 case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO:
75 base_freq = ERFO_FREQ;
76 break;
77 default:
78 // Codes 001 and 111 are reserved.
79 // This code should never execute, however, initialize to safe value.
80 base_freq = HIRC_FREQ;
81 break;
82 }
83
84 div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS;
85
86 SystemCoreClock = base_freq >> div;
87 }
88
89 /* This function is called before C runtime initialization and can be
90 * implemented by the application for early initializations. If a value other
91 * than '0' is returned, the C runtime initialization will be skipped.
92 *
93 * You may over-ride this function in your program by defining a custom
94 * PreInit(), but care should be taken to reproduce the initialization steps
95 * or a non-functional system may result.
96 */
PreInit(void)97 __weak int PreInit(void)
98 {
99 /* Do nothing */
100 return 0;
101 }
102
103 /* This function can be implemented by the application to initialize the board */
Board_Init(void)104 __weak int Board_Init(void)
105 {
106 /* Do nothing */
107 return 0;
108 }
109
PalSysInit(void)110 __weak void PalSysInit(void) {}
111
112 /* This function is called just before control is transferred to main().
113 *
114 * You may over-ride this function in your program by defining a custom
115 * SystemInit(), but care should be taken to reproduce the initialization
116 * steps or a non-functional system may result.
117 */
SystemInit(void)118 __weak void SystemInit(void)
119 {
120 #ifdef DEBUG
121 /* Delay to prevent bricks */
122 volatile int i;
123 for (i = 0; i < 0x3FFFF; i++) {}
124 #endif
125
126 /* Configure the interrupt controller to use the application vector table in */
127 /* the application space */
128 #if defined(__CC_ARM) || defined(__GNUC__)
129 /* IAR sets the VTOR pointer incorrectly and causes stack corruption */
130 SCB->VTOR = (uint32_t)__isr_vector;
131 #endif /* __CC_ARM || __GNUC__ */
132
133 *(volatile uint32_t *)0x40000c00 = 1; // Enable test mode
134 *(volatile uint32_t *)0x4000040c = (1 << 6); // Disable cache read buffer
135 *(volatile uint32_t *)0x40000c00 = 0; // Disable test mode
136
137 MXC_ICC_Enable(MXC_ICC0);
138 MXC_ICC_Disable(MXC_ICC0);
139 MXC_ICC_Enable(MXC_ICC0);
140
141 /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
142 /* Grant full access, per "Table B3-24 CPACR bit assignments". */
143 /* DDI0403D "ARMv7-M Architecture Reference Manual" */
144 SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
145 __DSB();
146 __ISB();
147
148 MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO);
149 SystemCoreClockUpdate();
150
151 PalSysInit();
152
153 Board_Init();
154
155 __enable_irq();
156 }
157
