1 /*******************************************************************************
2 * File Name: cycfg_qspi_memslot.c
3 *
4 * Description:
5 * Provides definitions of the SMIF-driver memory configuration.
6 * This file was automatically generated and should not be modified.
7 * QSPI Configurator 2.20.0.2857
8 *
9 ********************************************************************************
10 * Copyright 2020 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 *     http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 ********************************************************************************/
25 
26 #include "cycfg_qspi_memslot.h"
27 
28 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
29 {
30     /* The 8-bit command. 1 x I/O read command. */
31     .command = 0xECU,
32     /* The width of the command transfer. */
33     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
34     /* The width of the address transfer. */
35     .addrWidth = CY_SMIF_WIDTH_QUAD,
36     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
37     .mode = 0x01U,
38     /* The width of the mode command transfer. */
39     .modeWidth = CY_SMIF_WIDTH_QUAD,
40     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
41     .dummyCycles = 4U,
42     /* The width of the data transfer. */
43     .dataWidth = CY_SMIF_WIDTH_QUAD
44 };
45 
46 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
47 {
48     /* The 8-bit command. 1 x I/O read command. */
49     .command = 0x06U,
50     /* The width of the command transfer. */
51     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
52     /* The width of the address transfer. */
53     .addrWidth = CY_SMIF_WIDTH_SINGLE,
54     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
55     .mode = 0xFFFFFFFFU,
56     /* The width of the mode command transfer. */
57     .modeWidth = CY_SMIF_WIDTH_SINGLE,
58     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
59     .dummyCycles = 0U,
60     /* The width of the data transfer. */
61     .dataWidth = CY_SMIF_WIDTH_SINGLE
62 };
63 
64 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
65 {
66     /* The 8-bit command. 1 x I/O read command. */
67     .command = 0x04U,
68     /* The width of the command transfer. */
69     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
70     /* The width of the address transfer. */
71     .addrWidth = CY_SMIF_WIDTH_SINGLE,
72     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
73     .mode = 0xFFFFFFFFU,
74     /* The width of the mode command transfer. */
75     .modeWidth = CY_SMIF_WIDTH_SINGLE,
76     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
77     .dummyCycles = 0U,
78     /* The width of the data transfer. */
79     .dataWidth = CY_SMIF_WIDTH_SINGLE
80 };
81 
82 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
83 {
84     /* The 8-bit command. 1 x I/O read command. */
85     .command = 0xDCU,
86     /* The width of the command transfer. */
87     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
88     /* The width of the address transfer. */
89     .addrWidth = CY_SMIF_WIDTH_SINGLE,
90     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
91     .mode = 0xFFFFFFFFU,
92     /* The width of the mode command transfer. */
93     .modeWidth = CY_SMIF_WIDTH_SINGLE,
94     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
95     .dummyCycles = 0U,
96     /* The width of the data transfer. */
97     .dataWidth = CY_SMIF_WIDTH_SINGLE
98 };
99 
100 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
101 {
102     /* The 8-bit command. 1 x I/O read command. */
103     .command = 0x60U,
104     /* The width of the command transfer. */
105     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
106     /* The width of the address transfer. */
107     .addrWidth = CY_SMIF_WIDTH_SINGLE,
108     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
109     .mode = 0xFFFFFFFFU,
110     /* The width of the mode command transfer. */
111     .modeWidth = CY_SMIF_WIDTH_SINGLE,
112     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
113     .dummyCycles = 0U,
114     /* The width of the data transfer. */
115     .dataWidth = CY_SMIF_WIDTH_SINGLE
116 };
117 
118 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
119 {
120     /* The 8-bit command. 1 x I/O read command. */
121     .command = 0x34U,
122     /* The width of the command transfer. */
123     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
124     /* The width of the address transfer. */
125     .addrWidth = CY_SMIF_WIDTH_SINGLE,
126     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
127     .mode = 0xFFFFFFFFU,
128     /* The width of the mode command transfer. */
129     .modeWidth = CY_SMIF_WIDTH_QUAD,
130     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
131     .dummyCycles = 0U,
132     /* The width of the data transfer. */
133     .dataWidth = CY_SMIF_WIDTH_QUAD
134 };
135 
136 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
137 {
138     /* The 8-bit command. 1 x I/O read command. */
139     .command = 0x35U,
140     /* The width of the command transfer. */
141     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
142     /* The width of the address transfer. */
143     .addrWidth = CY_SMIF_WIDTH_SINGLE,
144     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
145     .mode = 0xFFFFFFFFU,
146     /* The width of the mode command transfer. */
147     .modeWidth = CY_SMIF_WIDTH_SINGLE,
148     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
149     .dummyCycles = 0U,
150     /* The width of the data transfer. */
151     .dataWidth = CY_SMIF_WIDTH_SINGLE
152 };
153 
154 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
155 {
156     /* The 8-bit command. 1 x I/O read command. */
157     .command = 0x05U,
158     /* The width of the command transfer. */
159     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
160     /* The width of the address transfer. */
161     .addrWidth = CY_SMIF_WIDTH_SINGLE,
162     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
163     .mode = 0xFFFFFFFFU,
164     /* The width of the mode command transfer. */
165     .modeWidth = CY_SMIF_WIDTH_SINGLE,
166     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
167     .dummyCycles = 0U,
168     /* The width of the data transfer. */
169     .dataWidth = CY_SMIF_WIDTH_SINGLE
170 };
171 
172 const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
173 {
174     /* The 8-bit command. 1 x I/O read command. */
175     .command = 0x01U,
176     /* The width of the command transfer. */
177     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
178     /* The width of the address transfer. */
179     .addrWidth = CY_SMIF_WIDTH_SINGLE,
180     /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
181     .mode = 0xFFFFFFFFU,
182     /* The width of the mode command transfer. */
183     .modeWidth = CY_SMIF_WIDTH_SINGLE,
184     /* The number of dummy cycles. A zero value suggests no dummy cycles. */
185     .dummyCycles = 0U,
186     /* The width of the data transfer. */
187     .dataWidth = CY_SMIF_WIDTH_SINGLE
188 };
189 
190 const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
191 {
192     /* Specifies the number of address bytes used by the memory slave device. */
193     .numOfAddrBytes = 0x04U,
194     /* The size of the memory. */
195     .memSize = 0x04000000U,
196     /* Specifies the Read command. */
197     .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
198     /* Specifies the Write Enable command. */
199     .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
200     /* Specifies the Write Disable command. */
201     .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
202     /* Specifies the Erase command. */
203     .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
204     /* Specifies the sector size of each erase. */
205     .eraseSize = 0x00040000U,
206     /* Specifies the Chip Erase command. */
207     .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
208     /* Specifies the Program command. */
209     .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
210     /* Specifies the page size for programming. */
211     .programSize = 0x00000200U,
212     /* Specifies the command to read the QE-containing status register. */
213     .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
214     /* Specifies the command to read the WIP-containing status register. */
215     .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
216     /* Specifies the command to write into the QE-containing status register. */
217     .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
218     /* The mask for the status register. */
219     .stsRegBusyMask = 0x01U,
220     /* The mask for the status register. */
221     .stsRegQuadEnableMask = 0x02U,
222     /* The max time for the erase type-1 cycle-time in ms. */
223     .eraseTime = 2600U,
224     /* The max time for the chip-erase cycle-time in ms. */
225     .chipEraseTime = 460000U,
226     /* The max time for the page-program cycle-time in us. */
227     .programTime = 1300U,
228 #if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
229     /* Points to NULL or to structure with info about sectors for hybrid memory. */
230     .hybridRegionCount = 0U,
231     .hybridRegionInfo = NULL
232 #endif
233 };
234 
235 const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
236 {
237     /* Determines the slot number where the memory device is placed. */
238     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
239     /* Flags. */
240     .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
241     /* The data-line selection options for a slave device. */
242     .dataSelect = CY_SMIF_DATA_SEL0,
243     /* The base address the memory slave is mapped to in the PSoC memory map.
244     Valid when the memory-mapped mode is enabled. */
245     .baseAddress = 0x18000000U,
246     /* The size allocated in the PSoC memory map, for the memory slave device.
247     The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
248     .memMappedSize = 0x4000000U,
249     /* If this memory device is one of the devices in the dual quad SPI configuration.
250     Valid when the memory mapped mode is enabled. */
251     .dualQuadSlots = 0,
252     /* The configuration of the device. */
253     .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
254 };
255 
256 const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
257    &S25FL512S_SlaveSlot_0
258 };
259 
260 const cy_stc_smif_block_config_t smifBlockConfig =
261 {
262     /* The number of SMIF memories defined. */
263     .memCount = CY_SMIF_DEVICE_NUM,
264     /* The pointer to the array of memory config structures of size memCount. */
265     .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
266     /* The version of the SMIF driver. */
267     .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
268     /* The version of the SMIF driver. */
269     .minorVersion = CY_SMIF_DRV_VERSION_MINOR
270 };
271 
272