1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include <stdio.h>
22 #include <stddef.h>
23 #include <stdint.h>
24 #include "mxc_device.h"
25 #include "mxc_assert.h"
26 #include "mxc_lock.h"
27 #include "mxc_sys.h"
28 #include "mxc_delay.h"
29 #include "i2c_regs.h"
30 #include "dma_regs.h"
31 #include "i2c.h"
32 #include "i2c_reva.h"
33
34 /* **** Variable Declaration **** */
35 uint32_t interruptCheck = MXC_F_I2C_INTFL0_ADDR_MATCH | MXC_F_I2C_INTFL0_DNR_ERR;
36
37 /* **** Function Prototypes **** */
38
39 /* ************************************************************************* */
40 /* Control/Configuration functions */
41 /* ************************************************************************* */
MXC_I2C_Init(mxc_i2c_regs_t * i2c,int masterMode,unsigned int slaveAddr)42 int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr)
43 {
44 if (i2c == NULL) {
45 return E_NULL_PTR;
46 }
47
48 MXC_I2C_Shutdown(i2c); // Clear everything out
49
50 if (i2c == MXC_I2C0) {
51 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0);
52 MXC_GPIO_Config(&gpio_cfg_i2c0);
53 } else if (i2c == MXC_I2C1) {
54 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1);
55 MXC_GPIO_Config(&gpio_cfg_i2c1);
56 } else if (i2c == MXC_I2C2) {
57 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2);
58 MXC_GPIO_Config(&gpio_cfg_i2c2);
59 } else {
60 return E_NO_DEVICE;
61 }
62
63 return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t *)i2c, masterMode, slaveAddr);
64 }
65
MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t * i2c,unsigned int slaveAddr,int idx)66 int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx)
67 {
68 if (idx != 0) {
69 // MAX78002 does not support multiple slave addresses
70 return E_NOT_SUPPORTED;
71 }
72
73 return MXC_I2C_RevA_SetSlaveAddr((mxc_i2c_reva_regs_t *)i2c, slaveAddr, idx);
74 }
75
MXC_I2C_Shutdown(mxc_i2c_regs_t * i2c)76 int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c)
77 {
78 // Configure GPIO for I2C
79 if (i2c == MXC_I2C0) {
80 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0);
81 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0);
82 } else if (i2c == MXC_I2C1) {
83 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
84 MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1);
85 } else if (i2c == MXC_I2C2) {
86 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C2);
87 MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2);
88 } else {
89 return E_NO_DEVICE;
90 }
91
92 return MXC_I2C_RevA_Shutdown((mxc_i2c_reva_regs_t *)i2c);
93 }
94
MXC_I2C_Reset(mxc_i2c_regs_t * i2c)95 int MXC_I2C_Reset(mxc_i2c_regs_t *i2c)
96 {
97 // Configure GPIO for I2C
98 if (i2c == MXC_I2C0) {
99 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0);
100 } else if (i2c == MXC_I2C1) {
101 MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1);
102 } else if (i2c == MXC_I2C2) {
103 MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2);
104 } else {
105 return E_NO_DEVICE;
106 }
107
108 return E_NO_ERROR;
109 }
110
MXC_I2C_SetFrequency(mxc_i2c_regs_t * i2c,unsigned int hz)111 int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz)
112 {
113 return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t *)i2c, hz);
114 }
115
MXC_I2C_GetFrequency(mxc_i2c_regs_t * i2c)116 int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c)
117 {
118 return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t *)i2c);
119 }
120
MXC_I2C_ReadyForSleep(mxc_i2c_regs_t * i2c)121 int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c)
122 {
123 return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t *)i2c);
124 }
125
MXC_I2C_SetClockStretching(mxc_i2c_regs_t * i2c,int enable)126 int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable)
127 {
128 return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t *)i2c, enable);
129 }
130
MXC_I2C_GetClockStretching(mxc_i2c_regs_t * i2c)131 int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c)
132 {
133 return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t *)i2c);
134 }
135
MXC_I2C_DMA_Init(mxc_i2c_regs_t * i2c,mxc_dma_regs_t * dma,bool use_dma_tx,bool use_dma_rx)136 int MXC_I2C_DMA_Init(mxc_i2c_regs_t *i2c, mxc_dma_regs_t *dma, bool use_dma_tx, bool use_dma_rx)
137 {
138 return MXC_I2C_RevA_DMA_Init((mxc_i2c_reva_regs_t *)i2c, (mxc_dma_reva_regs_t *)dma, use_dma_tx,
139 use_dma_rx);
140 }
141
MXC_I2C_DMA_GetTXChannel(mxc_i2c_regs_t * i2c)142 int MXC_I2C_DMA_GetTXChannel(mxc_i2c_regs_t *i2c)
143 {
144 return MXC_I2C_RevA_DMA_GetTXChannel((mxc_i2c_reva_regs_t *)i2c);
145 }
146
MXC_I2C_DMA_GetRXChannel(mxc_i2c_regs_t * i2c)147 int MXC_I2C_DMA_GetRXChannel(mxc_i2c_regs_t *i2c)
148 {
149 return MXC_I2C_RevA_DMA_GetRXChannel((mxc_i2c_reva_regs_t *)i2c);
150 }
151
MXC_I2C_DMA_SetRequestSelect(mxc_i2c_regs_t * i2c,uint8_t * txData,uint8_t * rxData)152 int MXC_I2C_DMA_SetRequestSelect(mxc_i2c_regs_t *i2c, uint8_t *txData, uint8_t *rxData)
153 {
154 int i2cNum;
155 int txReqSel = -1;
156 int rxReqSel = -1;
157
158 if (i2c == NULL) {
159 return E_NULL_PTR;
160 }
161
162 i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
163
164 if (txData != NULL) {
165 switch (i2cNum) {
166 case 0:
167 txReqSel = MXC_DMA_REQUEST_I2C0TX;
168 break;
169
170 case 1:
171 txReqSel = MXC_DMA_REQUEST_I2C1TX;
172 break;
173
174 case 2:
175 txReqSel = MXC_DMA_REQUEST_I2C2TX;
176 break;
177
178 default:
179 return E_BAD_PARAM;
180 }
181 }
182
183 if (rxData != NULL) {
184 switch (i2cNum) {
185 case 0:
186 rxReqSel = MXC_DMA_REQUEST_I2C0RX;
187 break;
188
189 case 1:
190 rxReqSel = MXC_DMA_REQUEST_I2C1RX;
191 break;
192
193 case 2:
194 rxReqSel = MXC_DMA_REQUEST_I2C2RX;
195 break;
196
197 default:
198 return E_BAD_PARAM;
199 }
200 }
201
202 return MXC_I2C_RevA_DMA_SetRequestSelect((mxc_i2c_reva_regs_t *)i2c,
203 (mxc_dma_reva_regs_t *)MXC_DMA, txReqSel, rxReqSel);
204 }
205
206 /* ************************************************************************* */
207 /* Low-level functions */
208 /* ************************************************************************* */
MXC_I2C_Start(mxc_i2c_regs_t * i2c)209 int MXC_I2C_Start(mxc_i2c_regs_t *i2c)
210 {
211 return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t *)i2c);
212 }
213
MXC_I2C_Stop(mxc_i2c_regs_t * i2c)214 int MXC_I2C_Stop(mxc_i2c_regs_t *i2c)
215 {
216 return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t *)i2c);
217 }
218
MXC_I2C_WriteByte(mxc_i2c_regs_t * i2c,unsigned char byte)219 int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte)
220 {
221 return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t *)i2c, byte);
222 }
223
MXC_I2C_ReadByte(mxc_i2c_regs_t * i2c,unsigned char * byte,int ack)224 int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack)
225 {
226 return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t *)i2c, byte, ack);
227 }
228
MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t * i2c,unsigned char * byte,mxc_i2c_getAck_t getAck)229 int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck)
230 {
231 return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t *)i2c, byte,
232 (mxc_i2c_reva_getAck_t)getAck);
233 }
234
MXC_I2C_Write(mxc_i2c_regs_t * i2c,unsigned char * bytes,unsigned int * len)235 int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len)
236 {
237 return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t *)i2c, bytes, len);
238 }
239
MXC_I2C_Read(mxc_i2c_regs_t * i2c,unsigned char * bytes,unsigned int * len,int ack)240 int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack)
241 {
242 return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t *)i2c, bytes, len, ack);
243 }
244
MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t * i2c,volatile unsigned char * bytes,unsigned int len)245 int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len)
246 {
247 return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len);
248 }
249
MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t * i2c,unsigned char * bytes,unsigned int len,mxc_i2c_dma_complete_cb_t callback)250 int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
251 mxc_i2c_dma_complete_cb_t callback)
252 {
253 // The callback parameter was previously unused but keeping it for backwards-compatibility.
254 return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, MXC_DMA);
255 }
256
MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t * i2c)257 int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c)
258 {
259 return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c);
260 }
261
MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t * i2c,volatile unsigned char * bytes,unsigned int len)262 int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len)
263 {
264 return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len);
265 }
266
MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t * i2c,unsigned char * bytes,unsigned int len,mxc_i2c_dma_complete_cb_t callback)267 int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len,
268 mxc_i2c_dma_complete_cb_t callback)
269 {
270 // The callback parameter was previously unused but keeping it for backwards-compatibility.
271 return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, MXC_DMA);
272 }
273
MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t * i2c)274 int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c)
275 {
276 return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c);
277 }
278
MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t * i2c)279 void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c)
280 {
281 MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t *)i2c);
282 }
283
MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t * i2c)284 void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c)
285 {
286 MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t *)i2c);
287 }
288
MXC_I2C_GetFlags(mxc_i2c_regs_t * i2c,unsigned int * flags0,unsigned int * flags1)289 int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1)
290 {
291 return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1);
292 }
293
MXC_I2C_ClearFlags(mxc_i2c_regs_t * i2c,unsigned int flags0,unsigned int flags1)294 void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1)
295 {
296 MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1);
297 }
298
MXC_I2C_EnableInt(mxc_i2c_regs_t * i2c,unsigned int flags0,unsigned int flags1)299 void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1)
300 {
301 MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1);
302 }
303
MXC_I2C_DisableInt(mxc_i2c_regs_t * i2c,unsigned int flags0,unsigned int flags1)304 void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1)
305 {
306 MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1);
307 }
308
MXC_I2C_EnablePreload(mxc_i2c_regs_t * i2c)309 void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c)
310 {
311 MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t *)i2c);
312 }
313
MXC_I2C_DisablePreload(mxc_i2c_regs_t * i2c)314 void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c)
315 {
316 MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t *)i2c);
317 }
318
MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t * i2c)319 void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c)
320 {
321 MXC_I2C_RevA_EnableGeneralCall((mxc_i2c_reva_regs_t *)i2c);
322 }
323
MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t * i2c)324 void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c)
325 {
326 MXC_I2C_RevA_DisableGeneralCall((mxc_i2c_reva_regs_t *)i2c);
327 }
328
MXC_I2C_SetTimeout(mxc_i2c_regs_t * i2c,unsigned int timeout)329 void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout)
330 {
331 MXC_I2C_RevA_SetTimeout((mxc_i2c_reva_regs_t *)i2c, timeout);
332 }
333
MXC_I2C_GetTimeout(mxc_i2c_regs_t * i2c)334 unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c)
335 {
336 return MXC_I2C_RevA_GetTimeout((mxc_i2c_reva_regs_t *)i2c);
337 }
338
MXC_I2C_Recover(mxc_i2c_regs_t * i2c,unsigned int retries)339 int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries)
340 {
341 return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t *)i2c, retries);
342 }
343
344 /* ************************************************************************* */
345 /* Transaction level functions */
346 /* ************************************************************************* */
347
MXC_I2C_MasterTransaction(mxc_i2c_req_t * req)348 int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req)
349 {
350 return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t *)req);
351 }
352
MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t * req)353 int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req)
354 {
355 return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t *)req);
356 }
357
MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t * req)358 int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req)
359 {
360 return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t *)req, MXC_DMA);
361 }
362
MXC_I2C_SlaveTransaction(mxc_i2c_regs_t * i2c,mxc_i2c_slave_handler_t callback)363 int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback)
364 {
365 return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c,
366 (mxc_i2c_reva_slave_handler_t)callback, interruptCheck);
367 }
368
MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t * i2c,mxc_i2c_slave_handler_t callback)369 int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback)
370 {
371 return MXC_I2C_RevA_SlaveTransactionAsync(
372 (mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck);
373 }
374
MXC_I2C_SetRXThreshold(mxc_i2c_regs_t * i2c,unsigned int numBytes)375 int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes)
376 {
377 return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes);
378 }
379
MXC_I2C_GetRXThreshold(mxc_i2c_regs_t * i2c)380 int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c)
381 {
382 return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t *)i2c);
383 }
384
MXC_I2C_SetTXThreshold(mxc_i2c_regs_t * i2c,unsigned int numBytes)385 int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes)
386 {
387 return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes);
388 }
389
MXC_I2C_GetTXThreshold(mxc_i2c_regs_t * i2c)390 int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c)
391 {
392 return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c);
393 }
394
MXC_I2C_AsyncStop(mxc_i2c_regs_t * i2c)395 void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c)
396 {
397 MXC_I2C_RevA_AsyncStop((mxc_i2c_reva_regs_t *)i2c);
398 }
399
MXC_I2C_AbortAsync(mxc_i2c_regs_t * i2c)400 void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c)
401 {
402 MXC_I2C_RevA_AbortAsync((mxc_i2c_reva_regs_t *)i2c);
403 }
404
MXC_I2C_AsyncHandler(mxc_i2c_regs_t * i2c)405 void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c)
406 {
407 MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck);
408 }
409
MXC_I2C_DMACallback(int ch,int error)410 void MXC_I2C_DMACallback(int ch, int error)
411 {
412 MXC_I2C_RevA_DMACallback(ch, error);
413 }
414