1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2025 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /* **** Includes **** */
22 #include <stddef.h>
23 #include "mxc_errors.h"
24 #include "mxc_assert.h"
25 #include "mxc_sys.h"
26 #include "gpio.h"
27 #include "gpio_common.h"
28 #include "gpio_reva.h"
29
30 /* **** Definitions **** */
31
32 /* **** Globals **** */
33
34 // static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *);
35 // static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT];
36
37 /* **** Functions **** */
38
MXC_GPIO_Init(uint32_t port)39 int MXC_GPIO_Init(uint32_t port)
40 {
41 if (port == MXC_GPIO_PORT_0) {
42 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0);
43 } else if (port == MXC_GPIO_PORT_1) {
44 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1);
45 } else if (port == MXC_GPIO_PORT_2) {
46 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO2);
47 } else if (port == MXC_GPIO_PORT_3) {
48 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO3);
49 } else {
50 return E_BAD_PARAM;
51 }
52 return MXC_GPIO_Common_Init(port);
53 }
54
55 /* ************************************************************************** */
MXC_GPIO_Shutdown(uint32_t port)56 int MXC_GPIO_Shutdown(uint32_t port)
57 {
58 if (port == MXC_GPIO_PORT_0) {
59 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0);
60 } else if (port == MXC_GPIO_PORT_1) {
61 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO1);
62 } else if (port == MXC_GPIO_PORT_2) {
63 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO2);
64 } else if (port == MXC_GPIO_PORT_3) {
65 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO3);
66 } else {
67 return E_BAD_PARAM;
68 }
69
70 return E_NO_ERROR;
71 }
72
73 /* ************************************************************************** */
MXC_GPIO_Reset(uint32_t port)74 int MXC_GPIO_Reset(uint32_t port)
75 {
76 if (port == MXC_GPIO_PORT_0) {
77 MXC_SYS_Reset_Periph(MXC_SYS_RESET_GPIO0);
78 } else if (port == MXC_GPIO_PORT_1) {
79 MXC_SYS_Reset_Periph(MXC_SYS_RESET_GPIO1);
80 } else if (port == MXC_GPIO_PORT_2) {
81 MXC_SYS_Reset_Periph(MXC_SYS_RESET_GPIO2);
82 } else if (port == MXC_GPIO_PORT_3) {
83 MXC_SYS_Reset_Periph(MXC_SYS_RESET_GPIO3);
84 } else {
85 return E_BAD_PARAM;
86 }
87
88 return E_NO_ERROR;
89 }
90
91 /* ************************************************************************** */
92 /*
93 * GPIO_EN2 | GPIO_EN1 | GPIO_EN | Function
94 * --------------|---------------------|---------------------|----------------------
95 * 0 | 0 | 0 | Alternative 1
96 * 0 | 1 | 0 | Alternative 2
97 * 0 | 0 | 1 | GPIO (default)
98 */
MXC_GPIO_Config(const mxc_gpio_cfg_t * cfg)99 int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg)
100 {
101 int err;
102 mxc_gpio_regs_t *gpio = cfg->port;
103
104 // Configure the vssel
105 err = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask);
106 if (err != E_NO_ERROR) {
107 return err;
108 }
109
110 // Set the GPIO type
111 if ((err = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask)) !=
112 E_NO_ERROR) {
113 return err;
114 }
115
116 // Configure the pad
117 switch (cfg->pad) {
118 case MXC_GPIO_PAD_NONE:
119 gpio->pdpu_sel0 &= ~cfg->mask;
120 gpio->pdpu_sel1 &= ~cfg->mask;
121 gpio->pssel &= ~cfg->mask;
122 break;
123 case MXC_GPIO_PAD_WEAK_PULL_UP:
124 gpio->pdpu_sel0 |= cfg->mask;
125 gpio->pdpu_sel1 &= ~cfg->mask;
126 gpio->pssel |= cfg->mask;
127 break;
128 case MXC_GPIO_PAD_WEAK_PULL_DOWN:
129 gpio->pdpu_sel0 &= ~cfg->mask;
130 gpio->pdpu_sel1 |= cfg->mask;
131 gpio->pssel |= cfg->mask;
132 break;
133 case MXC_GPIO_PAD_PULL_UP:
134 gpio->pdpu_sel0 |= cfg->mask;
135 gpio->pdpu_sel1 &= ~cfg->mask;
136 gpio->pssel &= ~cfg->mask;
137 break;
138 case MXC_GPIO_PAD_PULL_DOWN:
139 gpio->pdpu_sel0 &= ~cfg->mask;
140 gpio->pdpu_sel1 |= cfg->mask;
141 gpio->pssel &= ~cfg->mask;
142 break;
143 default:
144 return E_BAD_PARAM;
145 }
146
147 // Configure the drive strength
148 if (cfg->func == MXC_GPIO_FUNC_IN) {
149 return E_NO_ERROR;
150 } else {
151 return MXC_GPIO_SetDriveStrength(gpio, cfg->drvstr, cfg->mask);
152 }
153 }
154
155 /* ************************************************************************** */
MXC_GPIO_InGet(mxc_gpio_regs_t * port,uint32_t mask)156 uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask)
157 {
158 return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask);
159 }
160
161 /* ************************************************************************** */
MXC_GPIO_OutSet(mxc_gpio_regs_t * port,uint32_t mask)162 void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask)
163 {
164 MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask);
165 }
166
167 /* ************************************************************************** */
MXC_GPIO_OutClr(mxc_gpio_regs_t * port,uint32_t mask)168 void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask)
169 {
170 MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask);
171 }
172
173 /* ************************************************************************** */
MXC_GPIO_OutGet(mxc_gpio_regs_t * port,uint32_t mask)174 uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask)
175 {
176 return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask);
177 }
178
179 /* ************************************************************************** */
MXC_GPIO_OutPut(mxc_gpio_regs_t * port,uint32_t mask,uint32_t val)180 void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val)
181 {
182 return MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val);
183 }
184
185 /* ************************************************************************** */
MXC_GPIO_OutToggle(mxc_gpio_regs_t * port,uint32_t mask)186 void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask)
187 {
188 MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask);
189 }
190
191 /* ************************************************************************** */
MXC_GPIO_IntConfig(const mxc_gpio_cfg_t * cfg,mxc_gpio_int_pol_t pol)192 int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
193 {
194 return MXC_GPIO_RevA_IntConfig(cfg, pol);
195 }
196
197 /* ************************************************************************** */
MXC_GPIO_EnableInt(mxc_gpio_regs_t * port,uint32_t mask)198 void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask)
199 {
200 MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask);
201 }
202
203 /* ************************************************************************** */
MXC_GPIO_DisableInt(mxc_gpio_regs_t * port,uint32_t mask)204 void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask)
205 {
206 MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask);
207 }
208
209 /* ************************************************************************** */
MXC_GPIO_GetFlags(mxc_gpio_regs_t * port)210 uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port)
211 {
212 return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port);
213 }
214
215 /* ************************************************************************** */
MXC_GPIO_ClearFlags(mxc_gpio_regs_t * port,uint32_t flags)216 void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags)
217 {
218 MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags);
219 }
220
221 /* ************************************************************************** */
MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t * cfg,mxc_gpio_callback_fn func,void * cbdata)222 void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata)
223 {
224 MXC_GPIO_Common_RegisterCallback(cfg, func, cbdata);
225 }
226
227 /* ************************************************************************** */
MXC_GPIO_Handler(unsigned int port)228 void MXC_GPIO_Handler(unsigned int port)
229 {
230 MXC_GPIO_Common_Handler(port);
231 }
232
233 /* ************************************************************************** */
MXC_GPIO_SetVSSEL(mxc_gpio_regs_t * port,mxc_gpio_vssel_t vssel,uint32_t mask)234 int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask)
235 {
236 return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask);
237 }
238
239 /* ************************************************************************** */
MXC_GPIO_SetWakeEn(mxc_gpio_regs_t * port,uint32_t mask)240 void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask)
241 {
242 MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask);
243 }
244
245 /* ************************************************************************** */
MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t * port,uint32_t mask)246 void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask)
247 {
248 MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask);
249 }
250
251 /* ************************************************************************** */
MXC_GPIO_GetWakeEn(mxc_gpio_regs_t * port)252 uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port)
253 {
254 return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port);
255 }
256
257 /* ************************************************************************** */
MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t * port,mxc_gpio_drvstr_t drvstr,uint32_t mask)258 int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask)
259 {
260 return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask);
261 }
262
