1/* 2 * Copyright (c) 2017-2022 Arm Limited. All rights reserved. 3 * Copyright (c) 2020-2021 IAR Systems AB 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 * This file is derivative of ../armclang/tfm_common_s.sct.template 18 */ 19 20#include "region_defs.h" 21 22define block ER_TFM_CODE with fixed order, alignment = 8, maximum size = S_CODE_SIZE { 23 readonly section .intvec, 24#ifndef S_RAM_CODE_START 25 rw section .textrw object *.o, /* place __ramfunc in ROM if no TFM_RAM_CODE block */ 26#endif 27 readonly 28}; 29 30define block TFM_UNPRIV_CODE with alignment = GTZC_FLASH_ALIGN { 31 section SFN, 32 ro section .rodata object tfm_*_secure_api.o, 33 ro object *6M_tl*.a, 34 ro object *7M_tl*.a, 35 ro object *libtfm_sprt.a, 36 ro object psa_interface_*.o, 37 ro object tfm_psa_call_pack.o, 38 ro object tfm_log_raw.o, 39 ro object stm32u5xx_hal*.o, 40 ro object tick.o 41 }; 42 43 /**** Section for holding partition RO load data */ 44 /* 45 * Sort the partition info by priority to guarantee the initing order. 46 * The first loaded partition will be inited at last in SFN model. 47 */ 48define block TFM_SP_LOAD_LIST with alignment = 4 { 49 ro section .part_load_priority_lowest object load_info_*.o, 50 ro section .part_load_priority_low object load_info_*.o, 51 ro section .part_load_priority_normal object load_info_*.o, 52 ro section .part_load_priority_high object load_info_*.o, 53}; 54 55 /**** PSA RoT RO part (CODE + RODATA) start here */ 56 /* 57 * This empty, zero long execution region is here to mark the start address 58 * of PSA RoT code. 59 */ 60define block TFM_PSA_CODE_START with alignment = 32, size = 0 { }; 61 62 define block TFM_PSA_ROT_LINKER with alignment = 32 { 63 ro object *tfm_psa_rot_partition*, 64 }; 65 66 /* 67 * This empty, zero long execution region is here to mark the end address 68 * of PSA RoT code. 69 */ 70define block TFM_PSA_CODE_END with alignment = 32, size = 0 { }; 71 72 define block TFM_APP_ROT_LINKER with alignment = 32 { 73 ro object *tfm_app_rot_partition*, 74 }; 75 76 /* 77 * This empty, zero long execution region is here to mark the end address 78 * of APP RoT code. 79 */ 80define block TFM_APP_CODE_END with alignment = 32, size = 0 { }; 81 82 83 /**** Base address of secure data area */ 84define block TFM_SECURE_DATA_START with size = 0 { }; 85 86 /* Shared area between BL2 and runtime to exchange data */ 87define block TFM_SHARED_DATA with alignment = 32, size = BOOT_TFM_SHARED_DATA_SIZE { }; 88define block ARM_LIB_STACK with alignment = 32, size = S_MSP_STACK_SIZE - 0x8 { }; 89define overlay STACK_DATA {block TFM_SHARED_DATA}; 90define overlay STACK_DATA {block ARM_LIB_STACK}; 91 92define block STACKSEAL with size = 0x8 { }; 93 94keep {block TFM_SHARED_DATA, block ARM_LIB_STACK}; 95 96#if defined(CONFIG_TFM_PARTITION_META) 97define block TFM_SP_META_PTR with alignment = 32 { 98 zi section .bss.SP_META_PTR_SPRTL_INST 99 }; 100#endif 101 102define block TFM_APP_RW_STACK_START with alignment = GTZC_RAM_ALIGN, size = 0 { }; 103 104 define block TFM_APP_ROT_LINKER_DATA with alignment = 32 { 105 rw object *tfm_app_rot_partition*, 106 }; 107 108 109 /* 110 * This empty, zero long execution region is here to mark the end address 111 * of APP RoT RW and Stack. 112 */ 113define block TFM_APP_RW_STACK_END with alignment = GTZC_RAM_ALIGN, size = 0 { }; 114 115define block HEAP with alignment = 8, size = S_HEAP_SIZE { }; 116define block ARM_LIB_HEAP with alignment = 8, size = S_HEAP_SIZE { }; 117define overlay HEAP_OVL {block HEAP}; 118define overlay HEAP_OVL {block ARM_LIB_HEAP}; 119keep {block HEAP, block ARM_LIB_HEAP}; 120 121define block ER_TFM_DATA with alignment = 8 {readwrite}; 122 123/* The runtime partition placed order is same as load partition */ 124define block ER_PART_RT_POOL with alignment = 4 { 125 zi section .bss.part_runtime_priority_lowest, 126 zi section .bss.part_runtime_priority_low, 127 zi section .bss.part_runtime_priority_normal, 128 zi section .bss.part_runtime_priority_high, 129}; 130 131/* The runtime service placed order is same as load partition */ 132define block ER_SERV_RT_POOL with alignment = 4 { 133 zi section .bss.serv_runtime_priority_lowest, 134 zi section .bss.serv_runtime_priority_low, 135 zi section .bss.serv_runtime_priority_normal, 136 zi section .bss.serv_runtime_priority_high, 137}; 138 139keep {block ER_PART_RT_POOL, block ER_SERV_RT_POOL}; 140 141 /**** PSA RoT DATA start here */ 142 /* 143 * This empty, zero long execution region is here to mark the start address 144 * of PSA RoT RW and Stack. 145 */ 146define block TFM_PSA_RW_STACK_START with alignment = 32, size = 0 { }; 147 148 define block TFM_PSA_ROT_LINKER_DATA with alignment = 32 { 149 rw object *tfm_psa_rot_partition*, 150 }; 151 152 153 /* 154 * This empty, zero long execution region is here to mark the end address 155 * of PSA RoT RW and Stack. 156 */ 157define block TFM_PSA_RW_STACK_END with alignment = 32, size = 0x0 { }; 158 159#ifdef RAM_VECTORS_SUPPORT 160define block ER_RAM_VECTORS with alignment = 256 { section .ramvec }; 161#endif 162 163#if defined (S_RAM_CODE_START) 164define block TFM_RAM_CODE with alignment = 8 { 165 rw section .textrw, /* __ramfunc */ 166}; 167place at address S_RAM_CODE_START { block TFM_RAM_CODE }; 168#endif 169 170 /* This empty, zero long execution region is here to mark the limit address 171 * of the last execution region that is allocated in SRAM. 172 */ 173define block SRAM_WATERMARK with size = 0 { }; 174 175define block LR_CODE with fixed order { 176 block ER_TFM_CODE, 177 178 block TFM_SP_LOAD_LIST, 179 180 block TFM_PSA_CODE_START, 181 182 block TFM_PSA_ROT_LINKER, 183 184 block TFM_PSA_CODE_END, 185/**** UnPrivileged Flash start here , UNPRIV_BLOCK is align to match GTZC constrains */ 186 187 block TFM_UNPRIV_CODE, 188 189/**** APPLICATION RoT RO part (CODE + RODATA) start here */ 190 191 block TFM_APP_ROT_LINKER, 192 193 /* 194 * This empty, zero long execution region is here to mark the end address 195 * of APP RoT code. 196 */ 197 block TFM_APP_CODE_END, 198 }; 199 200do not initialize { 201 section .noinit, 202 rw section .ramvec 203 }; 204initialize by copy with packing = none { readwrite } 205#ifndef S_RAM_CODE_START 206 except { section .textrw } 207#endif 208 ; 209if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 210{ 211 // Required in a multi-threaded application 212 initialize by copy { section __DLIB_PERTHREAD }; 213} 214 215place at address S_CODE_START { block LR_CODE }; 216 217define block DATA with fixed order { 218 219 /**** Unpriv DATA start here */ 220 /* 221 * This empty, zero long execution region is here to mark the start address 222 * of unpriv data. 223 */ 224 block TFM_APP_RW_STACK_START, 225 /* Shared area between BL2 and runtime to exchange data */ 226 227#if defined(CONFIG_TFM_PARTITION_META) 228 block TFM_SP_META_PTR, 229#endif 230 231 block TFM_APP_ROT_LINKER_DATA, 232 233 /* 234 * This empty, zero long execution region is here to mark the end address 235 * of APP RoT RW and Stack. 236 */ 237 block TFM_APP_RW_STACK_END, 238 239 /* Privileged RAM starts here */ 240 /**** Base address of secure data area */ 241 block TFM_SECURE_DATA_START, 242 243 244 overlay HEAP_OVL, 245 246 block ER_TFM_DATA, 247 248 block ER_PART_RT_POOL, 249 250 block ER_SERV_RT_POOL, 251 252 /**** PSA RoT DATA start here */ 253 /* 254 * This empty, zero long execution region is here to mark the start address 255 * of PSA RoT RW and Stack. 256 */ 257 block TFM_PSA_RW_STACK_START, 258 259 block TFM_PSA_ROT_LINKER_DATA, 260 261 overlay STACK_DATA, 262 block STACKSEAL, 263 /* 264 * This empty, zero long execution region is here to mark the end address 265 * of PSA RoT RW and Stack. 266 */ 267 block TFM_PSA_RW_STACK_END, 268 269 /* This empty, zero long execution region is here to mark the limit address 270 * of the last execution region that is allocated in SRAM. 271 */ 272 block SRAM_WATERMARK, 273 274 /* Make sure that the sections allocated in the SRAM does not exceed the 275 * size of the SRAM available. 276 */ 277}; 278 279place at address S_DATA_START { block DATA }; 280 281 /* 282 * Place the CMSE Veneers (containing the SG instruction) in a separate 283 * 32 bytes aligned region so that the SAU can be programmed to 284 * just set this region as Non-Secure Callable. 285 */ 286define block LR_VENEER with alignment = 0x20, size = CMSE_VENEER_REGION_SIZE {section Veneer$$CMSE}; 287place at address CMSE_VENEER_REGION_START {block LR_VENEER}; 288 289 /* Reserved place for NS application. 290 * No code will be placed here, just address of this region is used in the 291 * secure code to configure certain HW components. This generates an empty 292 * execution region description warning during linking. 293 */ 294define block LR_NS_PARTITION with size = NS_PARTITION_SIZE { }; 295place at address NS_PARTITION_START { block LR_NS_PARTITION }; 296 297#ifdef BL2 298 /* Reserved place for new image in case of firmware upgrade. 299 * No code will be placed here, just address of this region is used in the 300 * secure code to configure certain HW components. This generates an empty 301 * execution region description warning during linking. 302 */ 303define block LR_SECONDARY_PARTITION with size = SECONDARY_PARTITION_SIZE { }; 304place at address SECONDARY_PARTITION_START { block LR_SECONDARY_PARTITION }; 305#endif /* BL2 */ 306