1;/*
2; * Copyright (c) 2017-2021 ARM Limited
3; * Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved.
4; * Copyright (c) 2020-2021 IAR Systems AB
5; *
6; * Licensed under the Apache License, Version 2.0 (the "License");
7; * you may not use this file except in compliance with the License.
8; * You may obtain a copy of the License at
9; *
10; *     http://www.apache.org/licenses/LICENSE-2.0
11; *
12; * Unless required by applicable law or agreed to in writing, software
13; * distributed under the License is distributed on an "AS IS" BASIS,
14; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15; * See the License for the specific language governing permissions and
16; * limitations under the License.
17; */
18;
19; This file is adapted from ../armclang/startup_psoc64_s.s
20; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
21
22;/*
23;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
24;*/
25
26; <h> Stack Configuration
27;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
28; </h>
29
30; Address of the NMI handler in ROM
31CY_NMI_HANLDER_ADDR    EQU    0x0000000D
32
33; Address of CPU VTOR register
34CY_CPU_VTOR_ADDR       EQU    0xE000ED08
35
36                PRESERVE8
37
38; Vector Table Mapped to Address 0 at Reset
39
40                SECTION  ARM_LIB_STACK:DATA:NOROOT(3)
41
42                SECTION  .intvec:CODE:NOROOT(2)
43
44                EXTERN   __iar_program_start
45                EXTERN   SystemInit
46                PUBLIC   __vector_table
47                PUBLIC   __Vectors
48                PUBLIC   __Vectors_End
49                PUBLIC   __Vectors_Size
50                PUBLIC  __ramVectors
51
52                IMPORT  HardFault_Handler
53                IMPORT  SVC_Handler
54                IMPORT  PendSV_Handler
55                IMPORT  tfm_mailbox_irq_handler
56                IMPORT  Cy_SysIpcPipeIsrCm0
57
58                DATA
59
60__vector_table       ;Core Interrupts
61                DCD     sfe(ARM_LIB_STACK)        ; Top of Stack
62                DCD     Reset_Handler             ; Reset Handler
63                DCD     CY_NMI_HANLDER_ADDR       ; NMI Handler
64                DCD     HardFault_Handler         ; Hard Fault Handler
65                DCD     0                         ; Reserved
66                DCD     0                         ; Reserved
67                DCD     0                         ; Reserved
68                DCD     0                         ; Reserved
69                DCD     0                         ; Reserved
70                DCD     0                         ; Reserved
71                DCD     0                         ; Reserved
72                DCD     SVC_Handler               ; SVCall Handler
73                DCD     0                         ; Reserved
74                DCD     0                         ; Reserved
75                DCD     PendSV_Handler            ; PendSV Handler
76                DCD     SysTick_Handler           ; SysTick Handler
77
78                ; External interrupts                           Description
79                DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0
80                DCD     Cy_SysIpcPipeIsrCm0
81                DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2
82                DCD     TFM_TIMER0_IRQ_Handler                ; Secure Timer IRQ
83                DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4
84                DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5
85                DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6
86                DCD     tfm_mailbox_irq_handler               ; CPU User Interrupt #7
87                DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0
88                DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1
89                DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2
90                DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3
91                DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4
92                DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5
93                DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6
94                DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7
95
96__Vectors_End
97
98__Vectors       EQU     __vector_table
99__Vectors_Size  EQU     __Vectors_End - __Vectors
100
101                SECTION  .ramvec:DATA:NOROOT(2)
102__ramVectors
103                DS8   __Vectors_Size
104
105; Reset Handler
106                PUBWEAK  Reset_Handler
107                SECTION  .text:CODE:REORDER:NOROOT(2)
108Reset_Handler
109                CPSID   i              ; Disable IRQs
110#ifdef RAM_VECTORS_SUPPORT
111                ; Copy vectors from ROM to RAM
112                LDR     r1, =__Vectors
113                LDR     r0, =__ramVectors
114                LDR     r2, =__Vectors_Size
115Vectors_Copy
116                LDR     r3, [r1]
117                STR     r3, [r0]
118                ADDS    r0, r0, #4
119                ADDS    r1, r1, #4
120                SUBS    r2, r2, #4
121                CMP     r2, #0
122                BNE     Vectors_Copy
123
124                ; Update Vector Table Offset Register. */
125                LDR     r0, =__ramVectors
126#else
127                LDR     R0, =__Vectors
128#endif
129                LDR     r1, =CY_CPU_VTOR_ADDR
130                STR     r0, [r1]
131                DSB     #0xF
132
133                LDR     R0, =SystemInit
134                BLX     R0
135                LDR     R0, =__iar_program_start
136                BX      R0
137End_Of_Main
138                B       .
139
140
141; Dummy Exception Handlers (infinite loops which can be modified)
142Default_Handler MACRO handler_name
143                PUBWEAK  handler_name
144handler_name
145                B       .
146                ENDM
147
148                Default_Handler SysTick_Handler
149                Default_Handler NvicMux0_IRQHandler
150                Default_Handler NvicMux2_IRQHandler
151                Default_Handler TFM_TIMER0_IRQ_Handler
152                Default_Handler NvicMux4_IRQHandler
153                Default_Handler NvicMux5_IRQHandler
154                Default_Handler NvicMux6_IRQHandler
155                Default_Handler Internal0_IRQHandler
156                Default_Handler Internal1_IRQHandler
157                Default_Handler Internal2_IRQHandler
158                Default_Handler Internal3_IRQHandler
159                Default_Handler Internal4_IRQHandler
160                Default_Handler Internal5_IRQHandler
161                Default_Handler Internal6_IRQHandler
162                Default_Handler Internal7_IRQHandler
163
164                END
165