1/* 2 * Copyright (c) 2009-2022 ARM Limited. All rights reserved. 3 * Copyright (c) 2019-2020, Cypress Semiconductor Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 * 7 * Licensed under the Apache License, Version 2.0 (the License); you may 8 * not use this file except in compliance with the License. 9 * You may obtain a copy of the License at 10 * 11 * www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 * See the License for the specific language governing permissions and 17 * limitations under the License. 18 */ 19 20/* adapted from Cypress PSoC64 Peripheral-Driver-Library v1.3.1 21 startup_psoc6_02_cm4.S*/ 22 23#include "tfm_plat_config.h" 24 25 /* The CPU VTOR register */ 26 #define CY_CPU_VTOR_ADDR 0xE000ED08 27 28 .syntax unified 29 .arch armv7-m 30 31 .section .vectors 32 .align 2 33 .globl __Vectors 34__Vectors: 35 .long __StackTop /* Top of Stack */ 36 .long Reset_Handler /* Reset Handler */ 37 .long NMI_Handler /* NMI Handler */ 38 .long HardFault_Handler /* Hard Fault Handler */ 39 .long MemManage_Handler /* MPU Fault Handler */ 40 .long BusFault_Handler /* Bus Fault Handler */ 41 .long UsageFault_Handler /* Usage Fault Handler */ 42 .long 0 /* Reserved */ 43 .long 0 /* Reserved */ 44 .long 0 /* Reserved */ 45 .long 0 /* Reserved */ 46 .long SVC_Handler /* SVCall Handler */ 47 .long DebugMon_Handler /* Debug Monitor Handler */ 48 .long 0 /* Reserved */ 49 .long PendSV_Handler /* PendSV Handler */ 50 .long SysTick_Handler /* SysTick Handler */ 51 52 /* External interrupts Description */ 53 .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ 54 .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ 55 .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ 56 .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ 57 .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ 58 .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ 59 .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ 60 .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ 61 .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ 62 .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ 63 .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ 64 .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ 65 .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ 66 .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ 67 .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ 68 .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ 69 .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ 70 .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ 71 .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ 72 .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 73 .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 74 .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ 75 .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 76 .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ 77 .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ 78 .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ 79 .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ 80 .long Cy_SysIpcPipeIsrCm4 81 .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ 82 .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ 83 .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ 84 .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ 85 .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ 86 .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ 87 .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ 88 .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ 89 .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ 90 .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ 91 .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ 92 .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ 93 .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ 94 .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ 95 .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ 96 .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ 97 .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ 98 .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ 99 .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ 100 .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ 101 .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ 102 .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ 103 .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ 104 .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ 105 .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ 106 .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ 107 .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ 108 .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ 109 .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ 110 .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ 111 .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ 112 .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ 113 .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ 114 .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ 115 .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ 116 .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ 117 .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ 118 .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ 119 .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ 120 .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ 121 .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ 122 .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ 123 .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ 124 .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ 125 .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ 126 .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ 127 .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ 128 .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ 129 .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ 130 .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ 131 .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ 132 .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ 133 .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ 134 .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ 135 .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ 136 .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ 137 .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ 138 .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ 139 .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ 140 .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ 141 .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ 142 .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ 143 .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ 144 .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ 145 .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ 146 .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ 147 .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ 148 .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ 149 .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ 150 .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ 151 .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ 152 .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ 153 .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ 154 .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ 155 .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ 156 .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ 157 .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ 158 .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ 159 .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ 160 .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ 161 .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ 162 .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ 163 .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ 164 .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ 165 .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ 166 .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ 167 .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ 168 .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ 169 .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ 170 .long Cy_Flash_ResumeIrqHandler /* FLASH Macro Interrupt */ 171 .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ 172 .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ 173 .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ 174 .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ 175 .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ 176 .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ 177 .long TIMER1_Handler /* TCPWM #0, Counter #1 */ 178 .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ 179 .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ 180 .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ 181 .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ 182 .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ 183 .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ 184 .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ 185 .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ 186 .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ 187 .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ 188 .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ 189 .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ 190 .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ 191 .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ 192 .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ 193 .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ 194 .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ 195 .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ 196 .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ 197 .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ 198 .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ 199 .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ 200 .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ 201 .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ 202 .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ 203 .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ 204 .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ 205 .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ 206 .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ 207 .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ 208 .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ 209 .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ 210 .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ 211 .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ 212 .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ 213 .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ 214 .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ 215 .long usb_interrupt_med_IRQHandler /* USB Interrupt */ 216 .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ 217 .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ 218 .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ 219 .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ 220 .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ 221 222 223 .size __Vectors, . - __Vectors 224 .equ __VectorsSize, . - __Vectors 225 226#ifdef RAM_VECTORS_SUPPORT 227 .section .ram_vectors 228 .align 2 229 .globl __ramVectors 230__ramVectors: 231 .space __VectorsSize 232 .size __ramVectors, . - __ramVectors 233#else 234 /* vectors relocation is not supported, 235 but allocate __ramVectors for PDL code */ 236 .globl __ramVectors 237 .equ __ramVectors, 0 238#endif 239 240 .text 241 .thumb 242 .thumb_func 243 .align 2 244 245 /* Device startup customization */ 246 .weak Cy_OnResetUser 247 .func Cy_OnResetUser, Cy_OnResetUser 248 .type Cy_OnResetUser, %function 249 250Cy_OnResetUser: 251 bx lr 252 .size Cy_OnResetUser, . - Cy_OnResetUser 253 .endfunc 254 255 /* Saves and disables the interrupts */ 256 .global Cy_SaveIRQ 257 .func Cy_SaveIRQ, Cy_SaveIRQ 258 .type Cy_SaveIRQ, %function 259 260Cy_SaveIRQ: 261 mrs r0, PRIMASK 262 cpsid i 263 bx lr 264 .size Cy_SaveIRQ, . - Cy_SaveIRQ 265 .endfunc 266 267 /* Restores the interrupts */ 268 .global Cy_RestoreIRQ 269 .func Cy_RestoreIRQ, Cy_RestoreIRQ 270 .type Cy_RestoreIRQ, %function 271 272Cy_RestoreIRQ: 273 msr PRIMASK, r0 274 bx lr 275 .size Cy_RestoreIRQ, . - Cy_RestoreIRQ 276 .endfunc 277 278 /* Reset handler */ 279 .weak Reset_Handler 280 .type Reset_Handler, %function 281 282Reset_Handler: 283 bl Cy_OnResetUser 284 cpsid i 285 286/* Firstly it copies data from read only memory to RAM. There are two schemes 287 * to copy. One can copy more than one sections. Another can only copy 288 * one section. The former scheme needs more instructions and read-only 289 * data to implement than the latter. 290 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ 291 292#ifdef __STARTUP_COPY_MULTIPLE 293/* Multiple sections scheme. 294 * 295 * Between symbol address __copy_table_start__ and __copy_table_end__, 296 * there are array of triplets, each of which specify: 297 * offset 0: LMA of start of a section to copy from 298 * offset 4: VMA of start of a section to copy to 299 * offset 8: size of the section to copy. 300 * 301 * All addresses must be aligned to 4 bytes boundary. 302 */ 303 ldr r4, =__copy_table_start__ 304 ldr r5, =__copy_table_end__ 305.L_loop0: 306 cmp r4, r5 307 bge .L_loop0_done 308 ldr r1, [r4] 309 ldr r2, [r4, #4] 310 ldr r3, [r4, #8] 311 lsls r3, r3, #2 312.L_loop0_0: 313 subs r3, #4 314 blt .L_loop0_0_done 315 ldr r0, [r1, r3] 316 str r0, [r2, r3] 317 b .L_loop0_0 318.L_loop0_0_done: 319 adds r4, #12 320 b .L_loop0 321.L_loop0_done: 322#else 323/* Single section scheme. 324 * 325 * The ranges of copy from/to are specified by following symbols 326 * __etext: LMA of start of the section to copy from. Usually end of text 327 * __data_start__: VMA of start of the section to copy to 328 * __data_end__: VMA of end of the section to copy to 329 * 330 * All addresses must be aligned to 4 bytes boundary. 331 */ 332 ldr r1, =__etext 333 ldr r2, =__data_start__ 334 ldr r3, =__data_end__ 335 subs r3, r2 336 ble .L_loop1_done 337.L_loop1: 338 subs r3, #4 339 ldr r0, [r1,r3] 340 str r0, [r2,r3] 341 bgt .L_loop1 342.L_loop1_done: 343#endif /*__STARTUP_COPY_MULTIPLE */ 344/* This part of work usually is done in C library startup code. Otherwise, 345 * define this macro to enable it in this startup. 346 * 347 * There are two schemes too. One can clear multiple BSS sections. Another 348 * can only clear one section. The former is more size expensive than the 349 * latter. 350 * 351 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. 352 * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. 353 */ 354#ifdef __STARTUP_CLEAR_BSS_MULTIPLE 355/* Multiple sections scheme. 356 * 357 * Between symbol address __copy_table_start__ and __copy_table_end__, 358 * there are array of tuples specifying: 359 * offset 0: Start of a BSS section 360 * offset 4: Size of this BSS section. 361 */ 362 ldr r3, =__zero_table_start__ 363 ldr r4, =__zero_table_end__ 364.L_loop2: 365 cmp r3, r4 366 bge .L_loop2_done 367 ldr r1, [r3] 368 ldr r2, [r3, #4] 369 lsls r2, r2, #2 370 movs r0, 0 371.L_loop2_0: 372 subs r2, #4 373 blt .L_loop2_0_done 374 str r0, [r1, r2] 375 b .L_loop2_0 376.L_loop2_0_done: 377 adds r3, #8 378 b .L_loop2 379.L_loop2_done: 380#elif defined (__STARTUP_CLEAR_BSS) 381/* Single BSS section scheme. 382 * 383 * The BSS section is specified by following symbols 384 * __bss_start__: start of the BSS section. 385 * __bss_end__: end of the BSS section. 386 * 387 * Both addresses must be aligned to 4 bytes boundary. 388 */ 389 ldr r1, =__bss_start__ 390 ldr r2, =__bss_end__ 391 movs r0, 0 392 subs r2, r1 393 ble .L_loop3_done 394.L_loop3: 395 subs r2, #4 396 str r0, [r1, r2] 397 bgt .L_loop3 398.L_loop3_done: 399#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ 400 401#ifdef RAM_VECTORS_SUPPORT 402 /* Update Vector Table Offset Register. */ 403 ldr r0, =__ramVectors 404#else 405 ldr r0, =__Vectors 406#endif 407 ldr r1, =CY_CPU_VTOR_ADDR 408 str r0, [r1] 409 dsb 0xF 410 411 /* Enable the FPU if used */ 412 bl Cy_SystemInitFpuEnable 413 414#ifndef __NO_SYSTEM_INIT 415 bl SystemInit 416#endif 417 418 cpsie i 419 420#ifndef __START 421#define __START _start 422#endif 423 bl __START 424 425 /* Should never get here */ 426 b . 427 428 .pool 429 .size Reset_Handler, . - Reset_Handler 430 431 .align 1 432 .thumb_func 433 .weak Default_Handler 434 .type Default_Handler, %function 435 436Default_Handler: 437 b . 438 .size Default_Handler, . - Default_Handler 439 440 441 .weak Cy_SysLib_FaultHandler 442 .type Cy_SysLib_FaultHandler, %function 443 444Cy_SysLib_FaultHandler: 445 b . 446 .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler 447 .type Fault_Handler, %function 448 449Fault_Handler: 450 /* Storing LR content for Creator call stack trace */ 451 push {LR} 452 movs r0, #4 453 mov r1, LR 454 tst r0, r1 455 beq .L_MSP 456 mrs r0, PSP 457 b .L_API_call 458.L_MSP: 459 mrs r0, MSP 460.L_API_call: 461 /* Compensation of stack pointer address due to pushing 4 bytes of LR */ 462 adds r0, r0, #4 463 bl Cy_SysLib_FaultHandler 464 b . 465 .size Fault_Handler, . - Fault_Handler 466 467.macro def_fault_Handler fault_handler_name 468 .weak \fault_handler_name 469 .set \fault_handler_name, Fault_Handler 470 .endm 471 472/* Macro to define default handlers. Default handler 473 * will be weak symbol and just dead loops. They can be 474 * overwritten by other handlers */ 475 .macro def_irq_handler handler_name 476 .weak \handler_name 477 .set \handler_name, Default_Handler 478 .endm 479 480 def_irq_handler NMI_Handler 481 482 def_fault_Handler HardFault_Handler 483 def_fault_Handler MemManage_Handler 484 def_fault_Handler BusFault_Handler 485 def_fault_Handler UsageFault_Handler 486 487 def_irq_handler DebugMon_Handler 488 def_irq_handler SysTick_Handler 489 490 def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ 491 def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ 492 def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ 493 def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ 494 def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ 495 def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ 496 def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ 497 def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ 498 def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ 499 def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ 500 def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ 501 def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ 502 def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ 503 def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ 504 def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ 505 def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ 506 def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ 507 def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ 508 def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ 509 def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 510 def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ 511 def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ 512 def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ 513 def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ 514 def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ 515 def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ 516 def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ 517 def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ 518 def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ 519 def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ 520 def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ 521 def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ 522 def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ 523 def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ 524 def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ 525 def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ 526 def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ 527 def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ 528 def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ 529 def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ 530 def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ 531 def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ 532 def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ 533 def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ 534 def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ 535 def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ 536 def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ 537 def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ 538 def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ 539 def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ 540 def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ 541 def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ 542 def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ 543 def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ 544 def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ 545 def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ 546 def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ 547 def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ 548 def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ 549 def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ 550 def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ 551 def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ 552 def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ 553 def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ 554 def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ 555 def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ 556 def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ 557 def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ 558 def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ 559 def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ 560 def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ 561 def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ 562 def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ 563 def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ 564 def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ 565 def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ 566 def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ 567 def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ 568 def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ 569 def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ 570 def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ 571 def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ 572 def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ 573 def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ 574 def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ 575 def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ 576 def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ 577 def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ 578 def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ 579 def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ 580 def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ 581 def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ 582 def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ 583 def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ 584 def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ 585 def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ 586 def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ 587 def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ 588 def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ 589 def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ 590 def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ 591 def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ 592 def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ 593 def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ 594 def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ 595 def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ 596 def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ 597 def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ 598 def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ 599 def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ 600 def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ 601 def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ 602 def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ 603 def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ 604 def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ 605 def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ 606 def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ 607 def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ 608 def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ 609 def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ 610 def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ 611 def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ 612 def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ 613 def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ 614 def_irq_handler TIMER1_Handler /* TCPWM #0, Counter #1 */ 615 def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ 616 def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ 617 def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ 618 def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ 619 def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ 620 def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ 621 def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ 622 def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ 623 def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ 624 def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ 625 def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ 626 def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ 627 def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ 628 def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ 629 def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ 630 def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ 631 def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ 632 def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ 633 def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ 634 def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ 635 def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ 636 def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ 637 def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ 638 def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ 639 def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ 640 def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ 641 def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ 642 def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ 643 def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ 644 def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ 645 def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ 646 def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ 647 def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ 648 def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ 649 def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ 650 def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ 651 def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ 652 def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ 653 def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ 654 def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ 655 def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ 656 def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ 657 def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ 658 659 .end 660 661 662/* [] END OF FILE */ 663
