1/*
2 * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *     http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "region_defs.h"
18
19LR_CODE S_CODE_START S_CODE_SIZE {
20
21    /****  This initial section contains common code for secure binary */
22    ER_TFM_CODE S_CODE_START {
23        *.o (RESET +First)
24        *libplatform_s* (.text*, .rodata*)
25        *libtfm_spm* (+RO)
26    }
27
28    /**** Section for holding partition RO load data */
29    /*
30     * Sort the partition info by priority to guarantee the initing order.
31     * The first loaded partition will be inited at last in SFN model.
32     */
33    TFM_SP_LOAD_LIST +0 ALIGN 4 {
34        *(.part_load_priority_lowest)
35        *(.part_load_priority_low)
36        *(.part_load_priority_normal)
37        *(.part_load_priority_high)
38    }
39
40    /**** PSA RoT RO part (CODE + RODATA) start here */
41    /*
42     * This empty, zero long execution region is here to mark the start address
43     * of PSA RoT code.
44     */
45    TFM_PSA_CODE_START +0 ALIGN 32 EMPTY 0x0 {
46    }
47
48    TFM_PSA_ROT_LINKER +0 ALIGN 32 {
49        *tfm_psa_rot_partition* (+RO-CODE, +RO-DATA)
50        *libplatform_s* (TFM_*_PSA-ROT_ATTR_FN)
51        *.o (TFM_*_PSA-ROT_ATTR_FN)
52    }
53
54    /*
55     * This empty, zero long execution region is here to mark the end address
56     * of PSA RoT code.
57     */
58    TFM_PSA_CODE_END +0 ALIGN 32 EMPTY 0x0 {
59    }
60    /**** Unprivileged Secure code start here */
61    TFM_UNPRIV_CODE  AlignExpr(+0, GTZC_FLASH_ALIGN) FIXED {
62        *(SFN)
63        * (+RO)
64    }
65    /**** APPLICATION RoT RO part (CODE + RODATA) start here */
66    /*
67     * This empty, zero long execution region is here to mark the start address
68     * of APP RoT code.
69     */
70    TFM_APP_CODE_START +0 ALIGN 32 EMPTY 0x0 {
71    }
72
73    TFM_APP_ROT_LINKER +0 ALIGN 32 {
74        *tfm_app_rot_partition* (+RO-CODE, +RO-DATA)
75        *libplatform_s* (TFM_*_APP-ROT_ATTR_FN)
76        *.o (TFM_*_APP-ROT_ATTR_FN)
77    }
78
79    /*
80     * This empty, zero long execution region is here to mark the end address
81     * of APP RoT code.
82     */
83    TFM_APP_CODE_END +0 ALIGN 32 EMPTY 0x0 {
84    }
85
86    /**** Base address of secure data area */
87    TFM_SECURE_DATA_START S_DATA_START {
88    }
89    /*
90     * This empty, zero long execution region is here to mark the start address
91     * of unpriv data.
92     */
93    TFM_APP_RW_STACK_START +0 ALIGN GTZC_RAM_ALIGN EMPTY 0x0 {
94    }
95
96
97#if defined(CONFIG_TFM_PARTITION_META)
98    TFM_SP_META_PTR +0 ALIGN 32 {
99        *(.bss.SP_META_PTR_SPRTL_INST)
100    }
101#endif
102
103    /**** APP RoT DATA start here */
104
105    TFM_APP_ROT_LINKER_DATA +0 ALIGN 32 {
106        *tfm_app_rot_partition* (+RW +ZI)
107        *.o(TFM_*_APP-ROT_ATTR_RW)
108        *.o(TFM_*_APP-ROT_ATTR_ZI)
109    }
110
111    /*
112     * This empty, zero long execution region is here to mark the end address
113     * of APP RoT RW and Stack.
114     */
115    TFM_APP_RW_STACK_END +0 ALIGN GTZC_RAM_ALIGN EMPTY 0x0 {
116    }
117        /* Shared area between BL2 and runtime to exchange data */
118    TFM_SHARED_DATA +0 ALIGN 32 OVERLAY EMPTY BOOT_TFM_SHARED_DATA_SIZE {
119    }
120
121    /* MSP */
122    ARM_LIB_STACK +0 ALIGN 32 OVERLAY EMPTY S_MSP_STACK_SIZE - 0x8 {
123    }
124
125    STACKSEAL +0 EMPTY 0x8 {
126    }
127
128    ARM_LIB_HEAP +0 ALIGN 8 EMPTY S_HEAP_SIZE {
129    }
130
131    ER_TFM_DATA +0 {
132        * (+RW +ZI)
133    }
134
135    /**** The runtime partition placed order is same as load partition */
136    ER_PART_RT_POOL +0 ALIGN 4 {
137        *(.bss.part_runtime_priority_lowest)
138        *(.bss.part_runtime_priority_low)
139        *(.bss.part_runtime_priority_normal)
140        *(.bss.part_runtime_priority_high)
141    }
142
143    /**** The runtime service placed order is same as load partition */
144    ER_SERV_RT_POOL +0 ALIGN 4 {
145        *(.bss.serv_runtime_priority_lowest)
146        *(.bss.serv_runtime_priority_low)
147        *(.bss.serv_runtime_priority_normal)
148        *(.bss.serv_runtime_priority_high)
149    }
150
151    /**** PSA RoT DATA start here */
152    /*
153     * This empty, zero long execution region is here to mark the start address
154     * of PSA RoT RW and Stack.
155     */
156    TFM_PSA_RW_STACK_START +0 ALIGN 32 EMPTY 0x0 {
157    }
158
159    TFM_PSA_ROT_LINKER_DATA +0 ALIGN 32 {
160        *tfm_psa_rot_partition* (+RW +ZI)
161        *.o(TFM_*_PSA-ROT_ATTR_RW)
162        *.o(TFM_*_PSA-ROT_ATTR_ZI)
163    }
164
165    /*
166     * This empty, zero long execution region is here to mark the end address
167     * of PSA RoT RW and Stack.
168     */
169    TFM_PSA_RW_STACK_END +0 ALIGN 32 EMPTY 0x0 {
170    }
171
172#if defined(PSA_PROXY_SHARED_MEMORY_BASE)
173    PSA_PROXY_SHARED_MEMORY PSA_PROXY_SHARED_MEMORY_BASE PSA_PROXY_SHARED_MEMORY_SIZE {
174        *(PSA_PROXY_SHARED_MEMORY_SECTION)
175    }
176#endif
177
178    /* This empty, zero long execution region is here to mark the limit address
179     * of the last execution region that is allocated in SRAM.
180     */
181    SRAM_WATERMARK +0 EMPTY 0x0 {
182    }
183
184    /* Make sure that the sections allocated in the SRAM does not exceed the
185     * size of the SRAM available.
186     */
187    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
188}
189
190LR_VENEER CMSE_VENEER_REGION_START {
191    /*
192     * Place the CMSE Veneers (containing the SG instruction) in a separate
193     * 32 bytes aligned region so that the SAU can be programmed to
194     * just set this region as Non-Secure Callable.
195     */
196    CMSE_VENEER CMSE_VENEER_REGION_START CMSE_VENEER_REGION_SIZE {
197        *(Veneer$$CMSE)
198    }
199}
200
201LR_NS_PARTITION NS_PARTITION_START {
202    /* Reserved place for NS application.
203     * No code will be placed here, just address of this region is used in the
204     * secure code to configure certain HW components. This generates an empty
205     * execution region description warning during linking.
206     */
207    ER_NS_PARTITION NS_PARTITION_START UNINIT NS_PARTITION_SIZE {
208    }
209}
210
211#ifdef BL2
212LR_SECONDARY_PARTITION SECONDARY_PARTITION_START {
213    /* Reserved place for new image in case of firmware upgrade.
214     * No code will be placed here, just address of this region is used in the
215     * secure code to configure certain HW components. This generates an empty
216     * execution region description warning during linking.
217     */
218    ER_SECONDARY_PARTITION SECONDARY_PARTITION_START \
219        UNINIT SECONDARY_PARTITION_SIZE {
220    }
221}
222#endif /* BL2 */
223