1;/*
2; * Copyright (c) 2017-2021 ARM Limited
3; * Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved.
4; *
5; * Licensed under the Apache License, Version 2.0 (the "License");
6; * you may not use this file except in compliance with the License.
7; * You may obtain a copy of the License at
8; *
9; *     http://www.apache.org/licenses/LICENSE-2.0
10; *
11; * Unless required by applicable law or agreed to in writing, software
12; * distributed under the License is distributed on an "AS IS" BASIS,
13; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14; * See the License for the specific language governing permissions and
15; * limitations under the License.
16; */
17;
18; adapted from Cypress PSoC64 Peripheral-Driver-Library v1.3.1
19; startup_psoc6_02_cm0plus.s
20;
21;/*
22;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
23;*/
24
25
26; <h> Stack Configuration
27;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
28; </h>
29
30; Address of the NMI handler in ROM
31CY_NMI_HANLDER_ADDR    EQU    0x0000000D
32
33; Address of CPU VTOR register
34CY_CPU_VTOR_ADDR       EQU    0xE000ED08
35
36                PRESERVE8
37
38                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
39
40; Vector Table Mapped to Address 0 at Reset
41
42                AREA    RESET, DATA, READONLY
43                EXPORT  __Vectors
44                EXPORT  __Vectors_End
45                EXPORT  __Vectors_Size
46                EXPORT  __ramVectors
47
48                IMPORT  HardFault_Handler
49                IMPORT  SVC_Handler
50                IMPORT  PendSV_Handler
51                IMPORT  tfm_mailbox_irq_handler
52                IMPORT  Cy_SysIpcPipeIsrCm0
53
54__Vectors       ;Core Interrupts
55                DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|  ; Top of Stack
56                DCD     Reset_Handler             ; Reset Handler
57                DCD     CY_NMI_HANLDER_ADDR       ; NMI Handler
58                DCD     HardFault_Handler         ; Hard Fault Handler
59                DCD     0                         ; Reserved
60                DCD     0                         ; Reserved
61                DCD     0                         ; Reserved
62                DCD     0                         ; Reserved
63                DCD     0                         ; Reserved
64                DCD     0                         ; Reserved
65                DCD     0                         ; Reserved
66                DCD     SVC_Handler               ; SVCall Handler
67                DCD     0                         ; Reserved
68                DCD     0                         ; Reserved
69                DCD     PendSV_Handler            ; PendSV Handler
70                DCD     SysTick_Handler           ; SysTick Handler
71
72                ; External interrupts                           Description
73                DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0
74                DCD     Cy_SysIpcPipeIsrCm0
75                DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2
76                DCD     TFM_TIMER0_IRQ_Handler                ; Secure Timer IRQ
77                DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4
78                DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5
79                DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6
80                DCD     tfm_mailbox_irq_handler               ; CPU User Interrupt #7
81                DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0
82                DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1
83                DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2
84                DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3
85                DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4
86                DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5
87                DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6
88                DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7
89
90__Vectors_End
91
92__Vectors_Size  EQU     __Vectors_End - __Vectors
93
94                AREA    RESET_RAM, READWRITE, NOINIT
95__ramVectors
96                SPACE   __Vectors_Size
97
98; Reset Handler
99                AREA    |.text|, CODE, READONLY
100Reset_Handler   PROC
101                EXPORT  Reset_Handler             [WEAK]
102                IMPORT  SystemInit
103                IMPORT  __main
104                CPSID   i              ; Disable IRQs
105
106                EXTERN RAM_VECTORS_SUPPORT
107                IF :DEF:RAM_VECTORS_SUPPORT
108                ; Copy vectors from ROM to RAM
109                LDR r1, =__Vectors
110                LDR r0, =__ramVectors
111                LDR r2, =__Vectors_Size
112Vectors_Copy
113                LDR r3, [r1]
114                STR r3, [r0]
115                ADDS r0, r0, #4
116                ADDS r1, r1, #4
117                SUBS r2, r2, #4
118                CMP r2, #0
119                BNE Vectors_Copy
120
121                ; Update Vector Table Offset Register.
122                LDR r0, =__ramVectors
123
124                ELSE
125
126                LDR     R0, =__Vectors
127
128                ENDIF
129
130                LDR r1, =CY_CPU_VTOR_ADDR
131                STR r0, [r1]
132                DSB 0xF
133
134                LDR     R0, =SystemInit
135                BLX     R0
136                MOV     R3, SP
137                MOVS    R1, #2
138
139                MOV     SP, R3
140                LDR     R0, =__main
141                BX      R0
142                ENDP
143End_Of_Main
144                B       .
145
146
147; Dummy Exception Handlers (infinite loops which can be modified)
148                MACRO
149                Default_Handler $handler_name
150$handler_name   PROC
151                EXPORT  $handler_name             [WEAK]
152                B       .
153                ENDP
154                MEND
155
156                Default_Handler SysTick_Handler
157                Default_Handler NvicMux0_IRQHandler
158                Default_Handler NvicMux2_IRQHandler
159                Default_Handler TFM_TIMER0_IRQ_Handler
160                Default_Handler NvicMux4_IRQHandler
161                Default_Handler NvicMux5_IRQHandler
162                Default_Handler NvicMux6_IRQHandler
163                Default_Handler Internal0_IRQHandler
164                Default_Handler Internal1_IRQHandler
165                Default_Handler Internal2_IRQHandler
166                Default_Handler Internal3_IRQHandler
167                Default_Handler Internal4_IRQHandler
168                Default_Handler Internal5_IRQHandler
169                Default_Handler Internal6_IRQHandler
170                Default_Handler Internal7_IRQHandler
171
172                ALIGN
173
174                END
175