1 /**
2 ******************************************************************************
3 * @file system_stm32u5xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32u5xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | MSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 4000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * APB3 Prescaler | 1
41 *-----------------------------------------------------------------------------
42 * PLL1_SRC | No clock
43 *-----------------------------------------------------------------------------
44 * PLL1_M | 1
45 *-----------------------------------------------------------------------------
46 * PLL1_N | 8
47 *-----------------------------------------------------------------------------
48 * PLL1_P | 7
49 *-----------------------------------------------------------------------------
50 * PLL1_Q | 2
51 *-----------------------------------------------------------------------------
52 * PLL1_R | 2
53 *-----------------------------------------------------------------------------
54 * PLL2_SRC | NA
55 *-----------------------------------------------------------------------------
56 * PLL2_M | NA
57 *-----------------------------------------------------------------------------
58 * PLL2_N | NA
59 *-----------------------------------------------------------------------------
60 * PLL2_P | NA
61 *-----------------------------------------------------------------------------
62 * PLL2_Q | NA
63 *-----------------------------------------------------------------------------
64 * PLL2_R | NA
65 *-----------------------------------------------------------------------------
66 * PLL3_SRC | NA
67 *-----------------------------------------------------------------------------
68 * PLL3_M | NA
69 *-----------------------------------------------------------------------------
70 * PLL3_N | NA
71 *-----------------------------------------------------------------------------
72 * PLL3_P | NA
73 *-----------------------------------------------------------------------------
74 * Require 48MHz for USB FS, | Disabled
75 * SDIO and RNG clock |
76 *-----------------------------------------------------------------------------
77 *=============================================================================
78 ******************************************************************************
79 * @attention
80 *
81 * <h2><center>© Copyright (c) 2020 STMicroelectronics.
82 * All rights reserved.</center></h2>
83 *
84 * This software component is licensed by ST under BSD 3-Clause license,
85 * the "License"; You may not use this file except in compliance with the
86 * License. You may obtain a copy of the License at:
87 * opensource.org/licenses/BSD-3-Clause
88 *
89 ******************************************************************************
90 */
91
92 /** @addtogroup CMSIS
93 * @{
94 */
95
96 /** @addtogroup STM32U5xx_system
97 * @{
98 */
99
100 /** @addtogroup STM32U5xx_System_Private_Includes
101 * @{
102 */
103
104 #include "stm32u5xx.h"
105 #include <math.h>
106
107 /**
108 * @}
109 */
110
111 /** @addtogroup STM32U5xx_System_Private_TypesDefinitions
112 * @{
113 */
114
115 /**
116 * @}
117 */
118
119 /** @addtogroup STM32U5xx_System_Private_Defines
120 * @{
121 */
122
123 #if !defined (HSE_VALUE)
124 #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
125 #endif /* HSE_VALUE */
126
127 #if !defined (MSI_VALUE)
128 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
129 #endif /* MSI_VALUE */
130
131 #if !defined (HSI_VALUE)
132 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
133 #endif /* HSI_VALUE */
134
135 /************************* Miscellaneous Configuration ************************/
136 /*!< Uncomment the following line if you need to relocate your vector Table in
137 Internal SRAM. */
138 /* #define VECT_TAB_SRAM */
139 #define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
140 This value must be a multiple of 0x200. */
141 /******************************************************************************/
142
143 /**
144 * @}
145 */
146
147 /** @addtogroup STM32U5xx_System_Private_Macros
148 * @{
149 */
150
151 /**
152 * @}
153 */
154
155 /** @addtogroup STM32U5xx_System_Private_Variables
156 * @{
157 */
158 /* The SystemCoreClock variable is updated in three ways:
159 1) by calling CMSIS function SystemCoreClockUpdate()
160 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
161 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
162 Note: If you use this function to configure the system clock; then there
163 is no need to call the 2 first functions listed above, since SystemCoreClock
164 variable is updated automatically.
165 */
166 uint32_t SystemCoreClock = 4000000U;
167
168 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
169 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
170 const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
171 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
172 /**
173 * @}
174 */
175
176 /** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
177 * @{
178 */
179 static void SetSysClock(void);
180
181 /**
182 * @}
183 */
184
185 /** @addtogroup STM32U5xx_System_Private_Functions
186 * @{
187 */
188
189 /**
190 * @brief Setup the microcontroller system.
191 * @param None
192 * @retval None
193 */
194
SystemInit(void)195 void SystemInit(void)
196 {
197 /* FPU settings ------------------------------------------------------------*/
198 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
199 SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
200 #endif
201
202 /* Configure the System clock source, PLL Multiplier and Divider factors,
203 AHB/APBx prescalers and Flash settings for System clock 160 MHz ---------*/
204 SetSysClock();
205 }
206
207 /**
208 * @brief Update SystemCoreClock variable according to Clock Register Values.
209 * The SystemCoreClock variable contains the core clock (HCLK), it can
210 * be used by the user application to setup the SysTick timer or configure
211 * other parameters.
212 *
213 * @note Each time the core clock (HCLK) changes, this function must be called
214 * to update SystemCoreClock variable value. Otherwise, any configuration
215 * based on this variable will be incorrect.
216 *
217 * @note - The system frequency computed by this function is not the real
218 * frequency in the chip. It is calculated based on the predefined
219 * constant and the selected clock source:
220 *
221 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
222 *
223 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
224 *
225 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
226 *
227 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
228 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
229 *
230 * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
231 * 4 MHz) but the real value may vary depending on the variations
232 * in voltage and temperature.
233 *
234 * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
235 * 16 MHz) but the real value may vary depending on the variations
236 * in voltage and temperature.
237 *
238 * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
239 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
240 * frequency of the crystal used. Otherwise, this function may
241 * have wrong result.
242 *
243 * - The result of this function could be not correct when using fractional
244 * value for HSE crystal.
245 *
246 * @param None
247 * @retval None
248 */
SystemCoreClockUpdate(void)249 void SystemCoreClockUpdate(void)
250 {
251 uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange;
252 float_t fracn1, pllvco;
253
254 /* Get MSI Range frequency--------------------------------------------------*/
255 if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
256 {
257 /* MSISRANGE from RCC_CSR applies */
258 msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
259 }
260 else
261 {
262 /* MSIRANGE from RCC_CR applies */
263 msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
264 }
265
266 /*MSI frequency range in HZ*/
267 msirange = MSIRangeTable[msirange];
268
269 /* Get SYSCLK source -------------------------------------------------------*/
270 switch (RCC->CFGR1 & RCC_CFGR1_SWS)
271 {
272 case 0x00: /* MSI used as system clock source */
273 SystemCoreClock = msirange;
274 break;
275
276 case 0x04: /* HSI used as system clock source */
277 SystemCoreClock = HSI_VALUE;
278 break;
279
280 case 0x08: /* HSE used as system clock source */
281 SystemCoreClock = HSE_VALUE;
282 break;
283
284 case 0x0C: /* PLL used as system clock source */
285 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
286 SYSCLK = PLL_VCO / PLLR
287 */
288 pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
289 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
290 pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
291 fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
292
293 switch (pllsource)
294 {
295 case 0x00: /* No clock sent to PLL*/
296 pllvco = (float_t)0U;
297 break;
298
299 case 0x02: /* HSI used as PLL clock source */
300 pllvco = ((float_t)HSI_VALUE / (float_t)pllm);
301 break;
302
303 case 0x03: /* HSE used as PLL clock source */
304 pllvco = ((float_t)HSE_VALUE / (float_t)pllm);
305 break;
306
307 default: /* MSI used as PLL clock source */
308 pllvco = ((float_t)msirange / (float_t)pllm);
309 break;
310 }
311
312 pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U);
313 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U );
314 SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr);
315 break;
316
317 default:
318 SystemCoreClock = msirange;
319 break;
320 }
321 /* Compute HCLK clock frequency --------------------------------------------*/
322 /* Get HCLK prescaler */
323 tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
324 /* HCLK clock frequency */
325 SystemCoreClock >>= tmp;
326 }
327
328 /**
329 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
330 * AHB/APBx prescalers and Flash settings for System clock 160MHz
331 * @retval None
332 */
SetSysClock(void)333 static void SetSysClock(void)
334 {
335 __IO uint32_t tmp;
336
337 /* Enable PWR clock */
338 RCC->AHB3ENR |= RCC_AHB3ENR_PWREN;
339 tmp = RCC->AHB3ENR;
340 UNUSED(tmp);
341
342 /* Set the regulator supply output voltage to range 1 for frequency above 100 Mhz */
343 PWR->VOSR |= PWR_VOSR_VOS; /* voltage range 1 */
344 while ((PWR->VOSR & PWR_VOSR_VOSRDY) != PWR_VOSR_VOSRDY)
345 {
346 }
347
348 /* Set Flash latency prior to system clock change */
349 FLASH->ACR = FLASH_ACR_LATENCY_4WS;
350 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_4WS)
351 {
352 }
353
354 /* Configure PLL clock source (MSI) */
355 RCC->PLL1CFGR = RCC_PLL1CFGR_PLL1SRC_0;
356
357 /* Enable the EPOD to reach max frequency */
358 PWR->VOSR |= PWR_VOSR_BOOSTEN;
359 while ((PWR->VOSR & PWR_VOSR_BOOSTRDY) != PWR_VOSR_BOOSTRDY)
360 {
361 }
362
363 /* Main PLL configuration and activation */
364 RCC->PLL1CFGR |= RCC_PLL1CFGR_PLL1REN;
365 RCC->PLL1DIVR = ((2U-1U) << RCC_PLL1DIVR_PLL1R_Pos) |
366 ((2U-1U) << RCC_PLL1DIVR_PLL1Q_Pos) |
367 ((2U-1U) << RCC_PLL1DIVR_PLL1P_Pos) |
368 ((80U-1U) << RCC_PLL1DIVR_PLL1N_Pos);
369 RCC->CR |= RCC_CR_PLL1ON;
370 while ((RCC->CR & RCC_CR_PLL1RDY) != RCC_CR_PLL1RDY)
371 {
372 }
373
374 /* Set PLL1 as System Clock Source */
375 RCC->CFGR1 = RCC_CFGR1_SW;
376 while ((RCC->CFGR1 & RCC_CFGR1_SWS) != RCC_CFGR1_SWS)
377 {
378 }
379
380 /* Enable the secure Internal High Speed oscillator (SHSI) for HW crypto peripherals */
381 RCC->CR |= RCC_CR_SHSION;
382 }
383
384 /**
385 * @}
386 */
387
388 /**
389 * @}
390 */
391
392 /**
393 * @}
394 */
395
396 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
397
