1 /**
2 ******************************************************************************
3 * @file system_stm32l5xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32l5xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | MSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 4000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * PLL_SRC | No clock
41 *-----------------------------------------------------------------------------
42 * PLL_M | 1
43 *-----------------------------------------------------------------------------
44 * PLL_N | 8
45 *-----------------------------------------------------------------------------
46 * PLL_P | 7
47 *-----------------------------------------------------------------------------
48 * PLL_Q | 2
49 *-----------------------------------------------------------------------------
50 * PLL_R | 2
51 *-----------------------------------------------------------------------------
52 * PLLSAI1_SRC | NA
53 *-----------------------------------------------------------------------------
54 * PLLSAI1_M | NA
55 *-----------------------------------------------------------------------------
56 * PLLSAI1_N | NA
57 *-----------------------------------------------------------------------------
58 * PLLSAI1_P | NA
59 *-----------------------------------------------------------------------------
60 * PLLSAI1_Q | NA
61 *-----------------------------------------------------------------------------
62 * PLLSAI1_R | NA
63 *-----------------------------------------------------------------------------
64 * PLLSAI2_SRC | NA
65 *-----------------------------------------------------------------------------
66 * PLLSAI2_M | NA
67 *-----------------------------------------------------------------------------
68 * PLLSAI2_N | NA
69 *-----------------------------------------------------------------------------
70 * PLLSAI2_P | NA
71 *-----------------------------------------------------------------------------
72 * Require 48MHz for USB FS, | Disabled
73 * SDIO and RNG clock |
74 *-----------------------------------------------------------------------------
75 *=============================================================================
76 ******************************************************************************
77 * @attention
78 *
79 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
80 * All rights reserved.</center></h2>
81 *
82 * This software component is licensed by ST under BSD 3-Clause license,
83 * the "License"; You may not use this file except in compliance with the
84 * License. You may obtain a copy of the License at:
85 * opensource.org/licenses/BSD-3-Clause
86 *
87 ******************************************************************************
88 */
89
90 /** @addtogroup CMSIS
91 * @{
92 */
93
94 /** @addtogroup STM32L5xx_System
95 * @{
96 */
97
98 /** @addtogroup STM32L5xx_System_Private_Includes
99 * @{
100 */
101
102 #include "stm32l5xx.h"
103
104 /**
105 * @}
106 */
107
108 /** @addtogroup STM32L5xx_System_Private_TypesDefinitions
109 * @{
110 */
111
112 /**
113 * @}
114 */
115
116 /** @addtogroup STM32L5xx_System_Private_Defines
117 * @{
118 */
119
120 #if !defined (HSE_VALUE)
121 #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
122 #endif /* HSE_VALUE */
123
124 #if !defined (MSI_VALUE)
125 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
126 #endif /* MSI_VALUE */
127
128 #if !defined (HSI_VALUE)
129 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
130 #endif /* HSI_VALUE */
131
132 /* Note: Following vector table addresses must be defined in line with linker
133 configuration. */
134 /*!< Uncomment the following line if you need to relocate the vector table
135 anywhere in Flash or Sram, else the vector table is kept at the automatic
136 remap of boot address selected */
137 /* #define USER_VECT_TAB_ADDRESS */
138
139 #if defined(USER_VECT_TAB_ADDRESS)
140 /*!< Uncomment the following line if you need to relocate your vector Table
141 in Sram else user remap will be done in Flash. */
142 /* #define VECT_TAB_SRAM */
143
144 #if defined(VECT_TAB_SRAM)
145 #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
146 This value must be a multiple of 0x200. */
147 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
148 This value must be a multiple of 0x200. */
149 #else
150 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
151 This value must be a multiple of 0x200. */
152 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
153 This value must be a multiple of 0x200. */
154 #endif /* VECT_TAB_SRAM */
155 #endif /* USER_VECT_TAB_ADDRESS */
156
157 /******************************************************************************/
158 /**
159 * @}
160 */
161
162 /** @addtogroup STM32L5xx_System_Private_Macros
163 * @{
164 */
165
166 /**
167 * @}
168 */
169
170 /** @addtogroup STM32L5xx_System_Private_Variables
171 * @{
172 */
173 /* The SystemCoreClock variable is updated in three ways:
174 1) by calling CMSIS function SystemCoreClockUpdate()
175 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
176 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
177 Note: If you use this function to configure the system clock; then there
178 is no need to call the 2 first functions listed above, since SystemCoreClock
179 variable is updated automatically.
180 */
181 uint32_t SystemCoreClock = 4000000U;
182
183 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
184 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
185 const uint32_t MSIRangeTable[16] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
186 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U, \
187 0U, 0U, 0U, 0U}; /* MISRAC-2012: 0U for unexpected value */
188 /**
189 * @}
190 */
191
192 /** @addtogroup STM32L5xx_System_Private_FunctionPrototypes
193 * @{
194 */
195
196 /**
197 * @}
198 */
199
200 /** @addtogroup STM32L5xx_System_Private_Functions
201 * @{
202 */
203
204 /**
205 * @brief Setup the microcontroller system.
206 * @retval None
207 */
208
SystemInit(void)209 void SystemInit(void)
210 {
211 /* Configure the Vector Table location -------------------------------------*/
212 #if defined(USER_VECT_TAB_ADDRESS)
213 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
214 #endif
215 }
216
217 /**
218 * @brief Update SystemCoreClock variable according to Clock Register Values.
219 * The SystemCoreClock variable contains the core clock (HCLK), it can
220 * be used by the user application to setup the SysTick timer or configure
221 * other parameters.
222 *
223 * @note Each time the core clock (HCLK) changes, this function must be called
224 * to update SystemCoreClock variable value. Otherwise, any configuration
225 * based on this variable will be incorrect.
226 *
227 * @note - The system frequency computed by this function is not the real
228 * frequency in the chip. It is calculated based on the predefined
229 * constant and the selected clock source:
230 *
231 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
232 *
233 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
234 *
235 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
236 *
237 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
238 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
239 *
240 * (*) MSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
241 * 4 MHz) but the real value may vary depending on the variations
242 * in voltage and temperature.
243 *
244 * (**) HSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
245 * 16 MHz) but the real value may vary depending on the variations
246 * in voltage and temperature.
247 *
248 * (***) HSE_VALUE is a constant defined in stm32l5xx_hal.h file (default value
249 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
250 * frequency of the crystal used. Otherwise, this function may
251 * have wrong result.
252 *
253 * - The result of this function could be not correct when using fractional
254 * value for HSE crystal.
255 *
256 * @retval None
257 */
SystemCoreClockUpdate(void)258 void SystemCoreClockUpdate(void)
259 {
260 uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
261
262 /* Get MSI Range frequency--------------------------------------------------*/
263 if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
264 { /* MSISRANGE from RCC_CSR applies */
265 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
266 }
267 else
268 { /* MSIRANGE from RCC_CR applies */
269 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
270 }
271 /*MSI frequency range in HZ*/
272 msirange = MSIRangeTable[msirange];
273
274 /* Get SYSCLK source -------------------------------------------------------*/
275 switch (RCC->CFGR & RCC_CFGR_SWS)
276 {
277 case 0x00: /* MSI used as system clock source */
278 SystemCoreClock = msirange;
279 break;
280
281 case 0x04: /* HSI used as system clock source */
282 SystemCoreClock = HSI_VALUE;
283 break;
284
285 case 0x08: /* HSE used as system clock source */
286 SystemCoreClock = HSE_VALUE;
287 break;
288
289 case 0x0C: /* PLL used as system clock source */
290 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
291 SYSCLK = PLL_VCO / PLLR
292 */
293 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
294 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
295
296 switch (pllsource)
297 {
298 case 0x02: /* HSI used as PLL clock source */
299 pllvco = (HSI_VALUE / pllm);
300 break;
301
302 case 0x03: /* HSE used as PLL clock source */
303 pllvco = (HSE_VALUE / pllm);
304 break;
305
306 default: /* MSI used as PLL clock source */
307 pllvco = (msirange / pllm);
308 break;
309 }
310 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
311 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
312 SystemCoreClock = pllvco/pllr;
313 break;
314
315 default:
316 SystemCoreClock = msirange;
317 break;
318 }
319 /* Compute HCLK clock frequency --------------------------------------------*/
320 /* Get HCLK prescaler */
321 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
322 /* HCLK clock frequency */
323 SystemCoreClock >>= tmp;
324 }
325
326
327 /**
328 * @}
329 */
330
331 /**
332 * @}
333 */
334
335 /**
336 * @}
337 */
338
339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
340
