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/hal_gigadevice-latest/
DREADME.md70 easily results in name collision with ZephyrRTOS core and libraries. To avoid
74 - Public API funtions must be prefixed with `gd32_`.
75 - Public defines and enum values must be uppercase and prefixed with `GD32_`.
99 - `<firmware_library>_timer.h/c`: `timer_init()` should be prefixed with
101 - `<firmware_library>_can.h/c`: all `CAN_` macros that collide with any
102 macro defined at `/include/drivers/can.h` should be prefixed with `GD32_`
108 conflict resolution. See below list with the proposed solution:
116 - i2c-gd32 driver needs to know the clock frequency boundary. Fix it with
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_i2c.h11 Redistribution and use in source and binary forms, with or without modification,
18 and/or other materials provided with the distribution.
217 …2_t)0x00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1…
218 …2_t)0x00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2…
219 …2_t)0x00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3…
220 …2_t)0x00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4…
221 …2_t)0x00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5…
222 …2_t)0x00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6…
223 …2_t)0x00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7…
224 …2_t)0x00000008U) /*!< digital filter is enabled and filter spikes with a length of up to 8…
[all …]
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_i2c.h11 Redistribution and use in source and binary forms, with or without modification,
18 and/or other materials provided with the distribution.
215 …2_t)0x00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1…
216 …2_t)0x00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2…
217 …2_t)0x00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3…
218 …2_t)0x00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4…
219 …2_t)0x00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5…
220 …2_t)0x00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6…
221 …2_t)0x00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7…
222 …2_t)0x00000008U) /*!< digital filter is enabled and filter spikes with a length of up to 8…
[all …]
/hal_gigadevice-latest/scripts/
Dgd32pinctrl.py80 """Generate AFIO header with pin configurations.
91 with open(outdir / get_header_fname(series, variant), "w") as f:
103 """Generate AF header with pin configurations.
114 with open(outdir / get_header_fname(series, variant), "w") as f:
135 Dictionary with pins configuration.
225 Dictionary with pins configuration.
270 indir: Directory with pin configuration files.
312 help="Directory with pin configuration files",
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_i2c.c11 Redistribution and use in source and binary forms, with or without modification,
18 and/or other materials provided with the distribution.
111 …\arg FILTER_LENGTH_1: digital filter is enabled and filter spikes with a length of up to 1 …
112 …\arg FILTER_LENGTH_2: digital filter is enabled and filter spikes with a length of up to 2 …
113 …\arg FILTER_LENGTH_3: digital filter is enabled and filter spikes with a length of up to 3 …
114 …\arg FILTER_LENGTH_4: digital filter is enabled and filter spikes with a length of up to 4 …
115 …\arg FILTER_LENGTH_5: digital filter is enabled and filter spikes with a length of up to 5 …
116 …\arg FILTER_LENGTH_6: digital filter is enabled and filter spikes with a length of up to 6 …
117 …\arg FILTER_LENGTH_7: digital filter is enabled and filter spikes with a length of up to 7 …
118 …\arg FILTER_LENGTH_8: digital filter is enabled and filter spikes with a length of up to 8 …
[all …]
Dgd32l23x_cau.c11 Redistribution and use in source and binary forms, with or without modification,
18 and/or other materials provided with the distribution.
64 \brief initialize the CAU encrypt and decrypt parameter struct with the default values
81 /* set the CAU encrypt and decrypt parameters struct with the default values */ in cau_struct_para_init()
94 \brief initialize the key parameter structure with the default values
109 /* set the key parameters struct with the default values */ in cau_key_struct_para_init()
121 \brief initialize the vectors parameter struct with the default values
132 /* set the vectors parameters struct with the default values */ in cau_iv_struct_para_init()
140 \brief initialize the context parameter struct with the default values
164 /* set the vectors parameters with the default values */ in cau_context_struct_para_init()
[all …]
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_i2c.c11 Redistribution and use in source and binary forms, with or without modification,
18 and/or other materials provided with the distribution.
106 …\arg FILTER_LENGTH_1: digital filter is enabled and filter spikes with a length of up to 1 …
107 …\arg FILTER_LENGTH_2: digital filter is enabled and filter spikes with a length of up to 2 …
108 …\arg FILTER_LENGTH_3: digital filter is enabled and filter spikes with a length of up to 3 …
109 …\arg FILTER_LENGTH_4: digital filter is enabled and filter spikes with a length of up to 4 …
110 …\arg FILTER_LENGTH_5: digital filter is enabled and filter spikes with a length of up to 5 …
111 …\arg FILTER_LENGTH_6: digital filter is enabled and filter spikes with a length of up to 6 …
112 …\arg FILTER_LENGTH_7: digital filter is enabled and filter spikes with a length of up to 7 …
113 …\arg FILTER_LENGTH_8: digital filter is enabled and filter spikes with a length of up to 8 …
[all …]
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_bkp.c14 Redistribution and use in source and binary forms, with or without modification,
21 and/or other materials provided with the distribution.
156 /* configure BKP_OCTL_ROSEL with outputsel */ in bkp_rtc_output_select()
176 /* configure BKP_OCTL_CCOSEL with clocksel */ in bkp_rtc_clock_output_select()
196 /* configure BKP_OCTL_CALDIR with direction */ in bkp_rtc_clock_calibration_direction_select()
214 /* configure BKP_OCTL_RCCV with value */ in bkp_rtc_calibration_value_set()
256 /* configure BKP_TPCTL_TPAL with level */ in bkp_tamper_active_level_set()
Dgd32e10x_gpio.c14 Redistribution and use in source and binary forms, with or without modification,
21 and/or other materials provided with the distribution.
110 \arg GPIO_MODE_OUT_OD: GPIO output with open-drain
111 \arg GPIO_MODE_OUT_PP: GPIO output with push-pull
112 \arg GPIO_MODE_AF_OD: AFIO output with open-drain
113 \arg GPIO_MODE_AF_PP: AFIO output with push-pull
148 /* configure the eight low port pins with GPIO_CTL0 */ in gpio_init()
172 /* configure the eight high port pins with GPIO_CTL1 */ in gpio_init()
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_ipa.c14 Redistribution and use in source and binary forms, with or without modification,
21 and/or other materials provided with the distribution.
135 …\arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format conve…
137 \arg IPA_FILL_UP_DE: fill up destination memory with specific color
148 …\brief initialize the structure of IPA foreground parameter struct with the default values, it …
166 /* initialize the struct parameters with default values */ in ipa_foreground_struct_para_init()
225 …\brief initialize the structure of IPA background parameter struct with the default values, it …
243 /* initialize the struct parameters with default values */ in ipa_background_struct_para_init()
302 …\brief initialize the structure of IPA destination parameter struct with the default values, it…
320 /* initialize the struct parameters with default values */ in ipa_destination_struct_para_init()
Dgd32f4xx_tli.c14 Redistribution and use in source and binary forms, with or without modification,
21 and/or other materials provided with the distribution.
56 …\brief initialize the parameters of TLI parameter structure with the default values, it is sugg…
79 /* initialize the struct parameters with default values */ in tli_struct_para_init()
202 …\brief initialize the parameters of TLI layer structure with the default values, it is suggested
228 /* initialize the struct parameters with default values */ in tli_layer_struct_para_init()
357 …\brief initialize the parameters of TLI layer LUT structure with the default values, it is sugg…
369 /* initialize the struct parameters with default values */ in tli_lut_struct_para_init()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_bkp.c12 Redistribution and use in source and binary forms, with or without modification,
19 and/or other materials provided with the distribution.
154 /* configure BKP_OCTL_ROSEL with outputsel */ in bkp_rtc_output_select()
172 /* configure BKP_OCTL_RCCV with value */ in bkp_rtc_calibration_value_set()
214 /* configure BKP_TPCTL_TPAL with level */ in bkp_tamper_active_level_set()
Dgd32vf103_gpio.c12 Redistribution and use in source and binary forms, with or without modification,
19 and/or other materials provided with the distribution.
108 \arg GPIO_MODE_OUT_OD: GPIO output with open-drain
109 \arg GPIO_MODE_OUT_PP: GPIO output with push-pull
110 \arg GPIO_MODE_AF_OD: AFIO output with open-drain
111 \arg GPIO_MODE_AF_PP: AFIO output with push-pull
140 /* configure the eight low port pins with GPIO_CTL0 */ in gpio_init()
164 /* configure the eight high port pins with GPIO_CTL1 */ in gpio_init()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_sqpi.c13 Redistribution and use in source and binary forms, with or without modification,
20 and/or other materials provided with the distribution.
52 \brief initialize the parameters of SQPI struct with the default values
59 /* set the SQPI struct with the default values */ in sqpi_struct_para_init()
Dgd32e50x_gpio.c13 Redistribution and use in source and binary forms, with or without modification,
20 and/or other materials provided with the distribution.
119 \arg GPIO_MODE_OUT_OD: GPIO output with open-drain
120 \arg GPIO_MODE_OUT_PP: GPIO output with push-pull
121 \arg GPIO_MODE_AF_OD: AFIO output with open-drain
122 \arg GPIO_MODE_AF_PP: AFIO output with push-pull
157 /* configure the eight low port pins with GPIO_CTL0 */ in gpio_init()
181 /* configure the eight high port pins with GPIO_CTL1 */ in gpio_init()
541 \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY
542 \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY
/hal_gigadevice-latest/gd32vf103/riscv/include/
Dsystem_gd32vf103.h13 Redistribution and use in source and binary forms, with or without modification,
20 and/or other materials provided with the distribution.
58 /* update the SystemCoreClock with current core clock retrieved from cpu registers */
/hal_gigadevice-latest/gd32l23x/cmsis/gd/gd32l23x/include/
Dsystem_gd32l23x.h10 Redistribution and use in source and binary forms, with or without
16 documentation and/or other materials provided with the distribution.
51 /* update the SystemCoreClock with current core clock retrieved from cpu registers */
/hal_gigadevice-latest/gd32f4xx/cmsis/gd/gd32f4xx/include/
Dsystem_gd32f4xx.h10 Redistribution and use in source and binary forms, with or without
16 documentation and/or other materials provided with the distribution.
51 /* update the SystemCoreClock with current core clock retrieved from cpu registers */
/hal_gigadevice-latest/gd32f3x0/cmsis/gd/gd32f3x0/include/
Dsystem_gd32f3x0.h10 Redistribution and use in source and binary forms, with or without
16 documentation and/or other materials provided with the distribution.
51 /* update the SystemCoreClock with current core clock retrieved from cpu registers */
/hal_gigadevice-latest/gd32f403/cmsis/gd/gd32f403/include/
Dsystem_gd32f403.h10 Redistribution and use in source and binary forms, with or without
16 documentation and/or other materials provided with the distribution.
51 /* update the SystemCoreClock with current core clock retrieved from cpu registers */
/hal_gigadevice-latest/gd32e10x/cmsis/gd/gd32e10x/include/
Dsystem_gd32e10x.h10 Redistribution and use in source and binary forms, with or without
16 documentation and/or other materials provided with the distribution.
51 /* update the SystemCoreClock with current core clock retrieved from cpu registers */
/hal_gigadevice-latest/gd32e50x/cmsis/gd/gd32e50x/include/
Dsystem_gd32e50x.h10 Redistribution and use in source and binary forms, with or without
16 documentation and/or other materials provided with the distribution.
51 /* update the SystemCoreClock with current core clock retrieved from CPU registers */
/hal_gigadevice-latest/gd32a50x/cmsis/gd/gd32a50x/include/
Dsystem_gd32a50x.h10 Redistribution and use in source and binary forms, with or without
16 documentation and/or other materials provided with the distribution.
51 /* update the SystemCoreClock with current core clock retrieved from CPU registers */
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_i2c.h13 Redistribution and use in source and binary forms, with or without modification,
20 and/or other materials provided with the distribution.
523 /* defines which bits of register ADDRESS[7:1] are compared with an incoming address byte */
534 …00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1…
535 …00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2…
536 …00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3…
537 …00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4…
538 …00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5…
539 …00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6…
540 …00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7…
[all …]
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_gpio.c13 Redistribution and use in source and binary forms, with or without modification,
20 and/or other materials provided with the distribution.
119 \arg GPIO_MODE_OUT_OD: GPIO output with open-drain
120 \arg GPIO_MODE_OUT_PP: GPIO output with push-pull
121 \arg GPIO_MODE_AF_OD: AFIO output with open-drain
122 \arg GPIO_MODE_AF_PP: AFIO output with push-pull
157 /* configure the eight low port pins with GPIO_CTL0 */ in gpio_init()
181 /* configure the eight high port pins with GPIO_CTL1 */ in gpio_init()

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