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/Zephyr-latest/samples/subsys/zbus/dyn_channel/
Dsample.yaml10 - "W: size=01"
11 - "W: Content"
12 - "W: 00 |."
13 - "W: size=02"
14 - "W: Content"
15 - "W: 01 01 |.."
16 - "W: size=03"
17 - "W: Content"
18 - "W: 00 00 00 |..."
19 - "W: size=04"
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DREADME.rst28 W: size=01
29 W: Content
30 W: 00 |.
31 W: size=02
32 W: Content
33 W: 01 01 |..
34 W: size=03
35 W: Content
36 W: 00 00 00 |...
37 W: size=04
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/Zephyr-latest/tests/arch/common/stack_unwind/
Dtestcase.yaml19 - "E: 0: fp: \\w+ ra: \\w+"
20 - "E: 1: fp: \\w+ ra: \\w+"
31 - "E: 0: sp: \\w+ ra: \\w+"
32 - "E: 1: sp: \\w+ ra: \\w+"
45 - "E: 0: \\w+"
46 - "E: 1: \\w+"
58 - "E: 0: fp: \\w+ lr: \\w+"
59 - "E: 1: fp: \\w+ lr: \\w+"
75 - "\\[func1\\+0x\\w+\\]"
76 - "\\[func2\\+0x\\w+\\]"
[all …]
/Zephyr-latest/soc/arm/beetle/
Dsoc_registers.h17 /* Offset: 0x000 (r/w) remap control register */
19 /* Offset: 0x004 (r/w) pmu control register */
21 /* Offset: 0x008 (r/w) reset option register */
23 /* Offset: 0x00c (r/w) emi control register */
25 /* Offset: 0x010 (r/w) reset information register */
28 /* Offset: 0x020 (r/w)AHB peripheral access control set */
30 /* Offset: 0x024 (r/w)AHB peripheral access control clear */
33 /* Offset: 0x030 (r/w)APB peripheral access control set */
35 /* Offset: 0x034 (r/w)APB peripheral access control clear */
38 /* Offset: 0x040 (r/w) main clock control register */
[all …]
/Zephyr-latest/include/zephyr/drivers/gpio/
Dgpio_cmsdk_ahb.h17 /* Offset: 0x000 (r/w) data register */
19 /* Offset: 0x004 (r/w) data output latch register */
22 /* Offset: 0x010 (r/w) output enable set register */
24 /* Offset: 0x014 (r/w) output enable clear register */
26 /* Offset: 0x018 (r/w) alternate function set register */
28 /* Offset: 0x01c (r/w) alternate function clear register */
30 /* Offset: 0x020 (r/w) interrupt enable set register */
32 /* Offset: 0x024 (r/w) interrupt enable clear register */
34 /* Offset: 0x028 (r/w) interrupt type set register */
36 /* Offset: 0x02c (r/w) interrupt type clear register */
[all …]
/Zephyr-latest/drivers/ipm/
Dipm_mhu.h27 volatile uint32_t cpu0intr_set; /* ( /W) CPU 0 Interrupt Set Register */
28 volatile uint32_t cpu0intr_clr; /* ( /W) CPU 0 Interrupt Clear Register */
32 volatile uint32_t cpu1intr_set; /* ( /W) CPU 1 Interrupt Set Register */
33 volatile uint32_t cpu1intr_clr; /* ( /W) CPU 1 Interrupt Clear Register */
35 volatile uint32_t pidr4; /* ( /W) Peripheral ID 4 */
37 volatile uint32_t pidr0; /* ( /W) Peripheral ID 0 */
38 volatile uint32_t pidr1; /* ( /W) Peripheral ID 1 */
39 volatile uint32_t pidr2; /* ( /W) Peripheral ID 2 */
40 volatile uint32_t pidr3; /* ( /W) Peripheral ID 3 */
41 volatile uint32_t cidr0; /* ( /W) Component ID 0 */
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/Zephyr-latest/include/zephyr/drivers/pcie/
Dpcie.h381 #define PCIE_CONF_CAPPTR_FIRST(w) (((w) >> 2) & 0x3FU) argument
388 #define PCIE_CONF_CAP_ID(w) ((w) & 0xFFU) argument
389 #define PCIE_CONF_CAP_NEXT(w) (((w) >> 10) & 0x3FU) argument
402 #define PCIE_CONF_EXT_CAP_ID(w) ((w) & 0xFFFFU) argument
403 #define PCIE_CONF_EXT_CAP_VER(w) (((w) >> 16) & 0xFU) argument
404 #define PCIE_CONF_EXT_CAP_NEXT(w) (((w) >> 20) & 0xFFFU) argument
431 #define PCIE_CONF_CLASSREV_CLASS(w) (((w) >> 24) & 0xFFU) argument
432 #define PCIE_CONF_CLASSREV_SUBCLASS(w) (((w) >> 16) & 0xFFU) argument
433 #define PCIE_CONF_CLASSREV_PROGIF(w) (((w) >> 8) & 0xFFU) argument
434 #define PCIE_CONF_CLASSREV_REV(w) ((w) & 0xFFU) argument
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/Zephyr-latest/kernel/include/
Dwait_q.h27 static inline void z_waitq_init(_wait_q_t *w) in z_waitq_init() argument
29 w->waitq = (struct _priq_rb) { in z_waitq_init()
36 static inline struct k_thread *z_waitq_head(_wait_q_t *w) in z_waitq_head() argument
38 return (struct k_thread *)rb_get_min(&w->waitq.tree); in z_waitq_head()
47 static inline void z_waitq_init(_wait_q_t *w)
49 sys_dlist_init(&w->waitq);
52 static inline struct k_thread *z_waitq_head(_wait_q_t *w)
54 return (struct k_thread *)sys_dlist_peek_head(&w->waitq);
/Zephyr-latest/drivers/counter/
Ddualtimer_cmsdk_apb.h16 /* Offset: 0x000 (R/W) Timer 1 Load */
20 /* Offset: 0x008 (R/W) Timer 1 Control */
22 /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
28 /* Offset: 0x018 (R/W) Background Load Register */
32 /* Offset: 0x020 (R/W) Timer 2 Load */
36 /* Offset: 0x028 (R/W) Timer 2 Control */
38 /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
44 /* Offset: 0x038 (R/W) Background Load Register */
48 /* Offset: 0xF00 (R/W) Integration Test Control Register */
50 /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
Dtimer_cmsdk_apb.h16 /* Offset: 0x000 (R/W) control register */
18 /* Offset: 0x004 (R/W) current value register */
20 /* Offset: 0x008 (R/W) reload value register */
25 /* Offset: 0x00C ( /W) interruptclear register */
/Zephyr-latest/tests/benchmarks/latency_measure/
DREADME.rst74 …fifo.get.blocking.k_to_k - Get data from FIFO (w/ ctx switch) : …
75 …fifo.put.wake+ctx.k_to_k - Add data to FIFO (w/ ctx switch) : …
76 …fifo.get.free.blocking.k_to_k - Free when getting data from FIFO (w/ ctx siwtch) : …
77 …fifo.put.alloc.wake+ctx.k_to_k - Allocate to add data to FIFO (w/ ctx switch) : …
82 …lifo.get.blocking.k_to_k - Get data from LIFO (w/ ctx switch) : …
83 …lifo.put.wake+ctx.k_to_k - Add data to LIFO (w/ ctx switch) : …
84 …lifo.get.free.blocking.k_to_k - Free when getting data from LIFO (w/ ctx switch) : …
85 …lifo.put.alloc.wake+ctx.k_to_k - Allocate to add data to LIFO (w/ ctx siwtch) : …
90 …events.wait.blocking.k_to_k - Wait for any events (w/ ctx switch) : …
91 …events.set.wake+ctx.k_to_k - Set events (w/ ctx switch) : …
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/Zephyr-latest/scripts/west_commands/zspdx/
Dsbom.py61 cm_fd = open(queryFilePath, "w")
83 w = Walker(walkerCfg)
84 retval = w.makeDocuments()
94 scanDocument(scannerCfg, w.docSDK)
95 scanDocument(scannerCfg, w.docApp)
96 scanDocument(scannerCfg, w.docZephyr)
97 scanDocument(scannerCfg, w.docBuild)
104 retval = writeSPDX(os.path.join(cfg.spdxDir, "sdk.spdx"), w.docSDK)
110 retval = writeSPDX(os.path.join(cfg.spdxDir, "app.spdx"), w.docApp)
116 writeSPDX(os.path.join(cfg.spdxDir, "zephyr.spdx"), w.docZephyr)
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/Zephyr-latest/drivers/fuel_gauge/bq27z746/
Dbq27z746.h14 #define BQ27Z746_MANUFACTURERACCESS 0x00 /* R/W */
15 #define BQ27Z746_ATRATE 0x02 /* R/W, Unit: mA, Range: -32768..32767 */
37 #define BQ27Z746_TERMINATEVOLTAGE 0x34 /* R/W, Unit: mC, Range: 0..32767 */
42 0x3C /* R/O (sealed), R/W (unsealed or factory access), Unit: mAh, Range: 0..32767 */
43 #define BQ27Z746_ALTMANUFACTURERACCESS 0x3E /* R/W */
47 #define BQ27Z746_VOLTHISETTHRESHOLD 0x62 /* R/W, Unit: mV, Range: 0..5000 */
48 #define BQ27Z746_VOLTHICLEARTHRESHOLD 0x64 /* R/W, Unit: mV, Range: 0..5000 */
49 #define BQ27Z746_VOLTLOSETTHRESHOLD 0x66 /* R/W, Unit: mV, Range: 0..5000 */
50 #define BQ27Z746_VOLTLOCLEARTHRESHOLD 0x68 /* R/W, Unit: mV, Range: 0..5000 */
51 #define BQ27Z746_TEMPHISETTHRESHOLD 0x6A /* R/W, Unit: degree celsius, Range: -128..127 */
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/Zephyr-latest/modules/lvgl/
Dlvgl_display_16bit.c14 uint16_t w = area->x2 - area->x1 + 1; in lvgl_flush_cb_16bit() local
21 flush.desc.buf_size = w * 2U * h; in lvgl_flush_cb_16bit()
22 flush.desc.width = w; in lvgl_flush_cb_16bit()
23 flush.desc.pitch = w; in lvgl_flush_cb_16bit()
Dlvgl_display_32bit.c14 uint16_t w = area->x2 - area->x1 + 1; in lvgl_flush_cb_32bit() local
21 flush.desc.buf_size = w * 4U * h; in lvgl_flush_cb_32bit()
22 flush.desc.width = w; in lvgl_flush_cb_32bit()
23 flush.desc.pitch = w; in lvgl_flush_cb_32bit()
Dlvgl_display_24bit.c14 uint16_t w = area->x2 - area->x1 + 1; in lvgl_flush_cb_24bit() local
21 flush.desc.buf_size = w * 3U * h; in lvgl_flush_cb_24bit()
22 flush.desc.width = w; in lvgl_flush_cb_24bit()
23 flush.desc.pitch = w; in lvgl_flush_cb_24bit()
/Zephyr-latest/subsys/logging/backends/
Dlog_backend_adsp_mtrace.c81 uint32_t w = slot->dsp_ptr; in mtrace_out() local
84 if (w > r) { in mtrace_out()
85 avail = MTRACE_LOG_BUF_SIZE - w + r - 1; in mtrace_out()
86 } else if (w == r) { in mtrace_out()
89 avail = r - w - 1; in mtrace_out()
100 if (w + out >= MTRACE_LOG_BUF_SIZE) { in mtrace_out()
101 size_t tail = MTRACE_LOG_BUF_SIZE - w; in mtrace_out()
104 memcpy(data + w, str, tail); in mtrace_out()
106 w = head; in mtrace_out()
108 memcpy(data + w, str, out); in mtrace_out()
[all …]
/Zephyr-latest/soc/aspeed/ast10x0/tools/
Dgen_uart_booting_image.py24 with open(dst, 'w+b') as w:
25 w.write(dst_image)
/Zephyr-latest/subsys/bluetooth/crypto/
Dbt_crypto.c56 int bt_crypto_f5(const uint8_t *w, const uint8_t *n1, const uint8_t *n2, const bt_addr_le_t *a1, in bt_crypto_f5() argument
73 LOG_DBG("w %s", bt_hex(w, 32)); in bt_crypto_f5()
77 sys_memcpy_swap(ws, w, 32); in bt_crypto_f5()
117 int bt_crypto_f6(const uint8_t *w, const uint8_t *n1, const uint8_t *n2, const uint8_t *r, in bt_crypto_f6() argument
125 LOG_DBG("w %s", bt_hex(w, 16)); in bt_crypto_f6()
146 sys_memcpy_swap(ws, w, 16); in bt_crypto_f6()
192 int bt_crypto_h6(const uint8_t w[16], const uint8_t key_id[4], uint8_t res[16]) in bt_crypto_h6()
198 LOG_DBG("w %s", bt_hex(w, 16)); in bt_crypto_h6()
201 sys_memcpy_swap(ws, w, 16); in bt_crypto_h6()
216 int bt_crypto_h7(const uint8_t salt[16], const uint8_t w[16], uint8_t res[16]) in bt_crypto_h7()
[all …]
Dbt_crypto.h49 * @param[in] w 256-bit
60 int bt_crypto_f5(const uint8_t *w, const uint8_t *n1, const uint8_t *n2, const bt_addr_le_t *a1,
68 * @param[in] w 128-bit
80 int bt_crypto_f6(const uint8_t *w, const uint8_t *n1, const uint8_t *n2, const uint8_t *r,
106 * @param[in] w 128-bit key
113 int bt_crypto_h6(const uint8_t w[16], const uint8_t key_id[4], uint8_t res[16]);
121 * @param[in] w 128-bit input of the AES-CMAC function
127 int bt_crypto_h7(const uint8_t salt[16], const uint8_t w[16], uint8_t res[16]);
/Zephyr-latest/tests/arch/riscv/fpu_sharing/src/
Dmain.c45 __asm__ volatile ("fcvt.s.w fa0, %0" : : "r" (42) : "fa0"); in ZTEST()
55 __asm__ volatile ("fcvt.w.s %0, fa0, rtz" : "=r" (val)); in ZTEST()
84 __asm__ volatile ("fcvt.w.d %0, fa0, rtz" : "=r" (val)); in new_thread_check()
86 __asm__ volatile ("fcvt.w.s %0, fa0, rtz" : "=r" (val)); in new_thread_check()
140 __asm__ volatile ("fcvt.s.w fa1, %0" : : "r" (42) : "fa1"); in thread1_entry()
163 __asm__ volatile ("fcvt.w.s %0, fa1, rtz" : "=r" (val)); in thread1_entry()
213 __asm__ volatile ("fcvt.s.w fa1, %0" : : "r" (37) : "fa1"); in thread2_entry()
223 __asm__ volatile ("fcvt.w.s %0, fa1" : "=r" (val)); in thread2_entry()
235 __asm__ volatile ("fcvt.w.s %0, fa1" : "=r" (val)); in thread2_entry()
279 __asm__ volatile ("fcvt.s.w fa1, %0" : : "r" (987) : "fa1"); in exception_context()
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/Zephyr-latest/tests/kernel/pipe/pipe_api/src/
Dtest_pipe_avail.c62 * @brief Test available read / write space for r < w
69 * r w
77 * r_avail = w - r = 3
80 * w_avail = N - (w - r) = 5
100 * @brief Test available read / write space for w < r
107 * w r
116 * r_avail = N - (r - w) = 5
119 * w_avail = r - w = 3
139 * @brief Test available read / write space for `r == w` and an empty buffer
149 * w
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.c29 uint8_t w; member
46 uint8_t w; member
55 uint8_t w; member
64 uint8_t w; member
76 uint8_t w; member
146 union CLICINTATTR intattr = {.w = 0}; in riscv_clic_irq_priority_set()
176 ECLIC_MTH.w = 0; in nuclei_eclic_init()
177 ECLIC_CFG.w = 0; in nuclei_eclic_init()
Dintc_gicv3_priv.h18 #define GIC_BASER_CACHE_RAWT 0x2UL /* Cacheable R-allocate, W-through */
19 #define GIC_BASER_CACHE_RAWB 0x3UL /* Cacheable R-allocate, W-back */
20 #define GIC_BASER_CACHE_WAWT 0x4UL /* Cacheable W-allocate, W-through */
21 #define GIC_BASER_CACHE_WAWB 0x5UL /* Cacheable W-allocate, W-back */
22 #define GIC_BASER_CACHE_RAWAWT 0x6UL /* Cacheable R-allocate, W-allocate, W-through */
23 #define GIC_BASER_CACHE_RAWAWB 0x7UL /* Cacheable R-allocate, W-allocate, W-back */
/Zephyr-latest/boards/raspberrypi/rpi_pico/
Drpi_pico_rp2040_w.yaml1 identifier: rpi_pico/rp2040/w
2 name: RaspberryPi-Pico-w

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